Preliminary Information Integrated Circuit Systems, Inc. M1040 VCSO BASED CLOCK PLL WITH AUTOSWITCH The M1040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in OC-12/48 class optical networking systems. It features dual differential inputs with two modes of input selection: manual and automatic upon clock failure. The clock multiplication ratios and output divider ratio are pin selectable. This device provides two outputs. External loop components allow the tailoring of PLL loop response. MR_SEL1 MR_SEL0 REF_ACK LOL NBW VCC DNC DNC DNC 28 29 30 31 32 33 34 35 36 P_SEL INIT nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND 18 17 16 15 14 13 12 11 10 M1040 (Top View) 1 2 3 4 5 6 7 8 9 FEATURES MR_SEL2 GND AUTO DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC PIN ASSIGNMENT (9 x 9 mm SMT) 27 26 25 24 23 22 21 20 19 GENERAL DESCRIPTION GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN ◆ Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz) ◆ Output frequencies of 62.5 to 175 MHz *; Two differential LVPECL outputs (CML, LVDS options available) Figure 1: Pin Assignment ◆ Loss of Lock (LOL) indicator output ◆ Narrow Bandwidth control input (NBW pin); Initialization (INIT) input overrides NBW at power-up ◆ Dual reference clock inputs support LVDS, LVPECL, LVCMOS, LVTTL ◆ AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock reselection upon clock failure; Hitless Switching (HS), Phase Build-out (PBO) options enable SONET (GR-253)/SDH (G.813) MTIE/TDEV compliance ◆ Acknowledge pin (REF_ACK pin) indicates the actively selected reference input ◆ Industrial temperature available ◆ Single 3.3V power supply ◆ Small 9 x 9 mm SMT (surface mount) package Example I/O Clock Frequency Combinations Using M1040-11-155.5200 PLL Ratio Input Reference Clock (MHz) (Pin Selectable) 19.44 77.76 155.52 622.08 8 2 1 0.25 Output Clock (MHz) (Pin Selectable) 155.52 or 77.76 Table 1: Example I/O Clock Frequency Combinations * Specify VCSO center frequency at time of order. SIMPLIFIED BLOCK DIAGRAM Loop Filter M1040 NBW PLL Phase Detector MUX DIF_REF0 nDIF_REF0 0 DIF_REF1 nDIF_REF1 1 R Div VCSO REF_ACK REF_SEL 0 1 AUTO M Divider LOL Phase Detector Auto Ref Sel INIT LOL MR_SEL2:0 3 FOUT0 nFOUT0 P Divider M / R Divider (1 or 2) LUT FOUT1 nFOUT1 P_SEL Figure 2: Simplified Block Diagram M1040 Datasheet Rev 0.1 Revised 11Nov2003 M1040 VCSO Based Clock PLL with AutoSwitch Integrated Circuit Systems, Inc. ● Communications Modules ● w w w. i c s t . c o m ● tel (508) 852-5400 M1040 Integrated Circuit Systems, Inc. VCSO BASED CLOCK PLL WITH AUTOSWITCH Preliminary Information PIN DESCRIPTIONS Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC 11, 19, 33 VCC 12 13 15 16 FOUT1 nFOUT1 FOUT0 nFOUT0 17 INIT 18 P_SEL Internal pull-down1 20 nDIF_REF1 Biased to Vcc/2 2 21 DIF_REF1 22 REF_SEL 23 nDIF_REF0 24 DIF_REF0 25 AUTO Input Internal pull-down resistor1 27 28 29 MR_SEL2 MR_SEL1 MR_SEL0 Input Internal pull-UP resistor1 30 REF_ACK Output 31 LOL Output 32 NBW Input 34, 35, 36 DNC Note 1: Note 2: Note 3: Note 4: I/O Configuration Ground Description Power supply ground connections. Input External loop filter connections. See Figure 5, External Loop Filter, on pg. 8. Output Input Power Power supply connection, connect to +3.3V. Output No internal terminator Clock output pair 1. Differential LVPECL. Output No internal terminator Clock output pair 0. Differential LVPECL. Input Internal pull-UP resistor1 Input Internal pull-down resistor1 Input Internal pull-down resistor1 Biased to Vcc/2 3 Input Internal pull-down resistor1 Internal pull-UP resistor1 Power-on Initialization; LVCMOS/LVTTL: Logic 1 allows device to enter narrow mode if selected (in addition must have 8 LOL=0 counts) Logic 0 forced device into wide bandwidth mode. Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 4, P Divider Selector Values and Frequencies, on pg. 3. Reference Differential LVPECL/ LVDS clock input Differential LVPECL/ LVDS, or single pair 1. ended LVCMOS/ LVTTL Reference clock input selection. LVCMOS/LVTTL. Logic 1 selects DIF_REF1/nDIF_REF1 inputs Logic 0 selects DIF_REF0/nDIF_REF0 inputs Reference Differential LVPECL/ LVDS clock input Differential LVPECL/ LVDS, or single pair 0. ended LVCMOS/ LVTTL Automatic/manual reselection mode for clock input: Logic 1 automatic reselection upon clock failure (non-revertive) Logic 0 manual selection only (using REF_SEL) M and R divider value selection. LVCMOS/ LVTTL. See Table 3, M and R Divider Look-Up Tables (LUT) on pg. 3. Reference Acknowledgement pin for input mux state; outputs the currently selected reference input pair: Logic 1 indicates nDIF_REF1, DIF_REF1 Logic 0 indicates nDIF_REF0, DIF_REF0 Loss of Lock indicator output. 4 Logic 1 indicates loss of lock. Logic 0 indicates locked condition. Narrow Bandwidth enable. LVCMOS/LVTTL: Logic 1 - Narrow loop bandwidth, RIN = 2100kΩ. Logic 0 - Wide bandwidth, RIN = 100kΩ. Do Not Connect. Table 2: Pin Descriptions For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 10. Biased to Vcc/2, with 50kΩ to Vcc and 50kΩ to ground. Float if using DIF_REF1 as LVCMOS input. See DC Characteristics on pg. 10. Biased to Vcc/2, with 50kΩ to Vcc and 50kΩ to ground. Float if using DIF_REF0 as LVCMOS input. See DC Characteristics on pg. 10. See LVCMOS Outputs in DC Characteristics on pg. 10. M1040 Datasheet Rev 0.1 Integrated Circuit Systems, Inc. 2 of 12 ● Communications Modules Revised 11Nov2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1040 Integrated Circuit Systems, Inc. VCSO BASED CLOCK PLL WITH AUTOSWITCH Preliminary Information DETAILED BLOCK DIAGRAM R LOOP C LOOP R POST External Loop Filter Components C POST C POST R LOOP OP_IN M1040 nOP_IN C LOOP R POST OP_OUT nOP_OUT nVC VC NBW PLL Phase Detector MUX DIF_REF0 nDIF_REF0 0 DIF_REF1 nDIF_REF1 1 R IN Divider R IN SAW Delay Line Phase Locked Loop (PLL) R Loop Filter Amplifier Phase Shifter VCSO REF_ACK REF_SEL M Divider 0 1 LOL Phase Detector AUTO Auto Ref Sel INIT LOL MR_SEL2:0 3 FOUT0 nFOUT0 P Divider M / R Divider FOUT1 nFOUT1 LUT P_SEL Figure 3: Detailed Block Diagram PLL DIVIDER SELECTION TABLES General Guidelines for M and R Divider Selection M and R Divider Look-Up Tables (LUT) General guidelines for M/R divider selection (see following pages for more detail): The MR_SEL2:0 pins select the feedback and reference divider values M and R to enable adjustment of loop bandwidth and jitter tolerance. The look-up is defined in Table 3. • A lower phase detector frequency should be used for M1040 M/R Divider LUT MR_SEL3:0 M Div R Div Phase Det. Total Fin for Freq. for PLL 155.52MHz 155.52MHz Ratio VCSO (MHz) VCSO (MHz) 000 8 1 8 19.44 19.44 001 64 8 8 19.44 2.43 010 2 1 2 77.76 77.76 011 16 8 2 77.76 9.72 100 1 1 1 155.52 155.52 101 8 8 1 155.52 19.44 N/A N/A N/A 622.08 77.76 110 111 Test Mode1 2 8 0.25 • Post-PLL Divider Table 3: M1040 M/R Divider LUT Note 1: Factory test mode; do not use. • loop timing applications to assure PLL tracking, especially during GR-253 jitter tolerance testing. The recommended maximum phase detector frequency for loop timing mode is 19.44MHz. The LOL pin should not be used during loop timing mode. When LOL is to be used for system health monitoring, the phase detector frequency should be 5MHz or greater. Low phase detector frequencies make LOL overly sensitive, and higher phase detector frequencies make LOL less sensitive. The preceding guideline also applies when using the AutoSwitch Mode, since AutoSwitch uses the LOL output for clock fault detection. The M1040 also features a post-PLL (P) divider for the output clocks. It divides the VCSO frequency to produce one of two selectable output frequencies (1/2 or 1/1 of the VCSO frequency). That selected frequency appears on both clock output pairs. The P_SEL pin selects the value for the P divider. Table 3 provides example Fin and phase detector frequencies with 155.52MHz VCSO devices (e.g., M1040-11-155.5200). See “Ordering Information” on pg. 12. P_SEL P Value 1 0 2 1 M1040-11-155.52 Output Frequency (MHz) 77.76 155.52 Table 4: P Divider Selector Values and Frequencies M1040 Datasheet Rev 0.1 Integrated Circuit Systems, Inc. 3 of 12 ● Communications Modules Revised 11Nov2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1040 Integrated Circuit Systems, Inc. VCSO BASED CLOCK PLL WITH AUTOSWITCH Preliminary Information FUNCTIONAL DESCRIPTION Input Reference Clocks The M1040 is a PLL (Phase Locked Loop) based clock generator that generates two output clocks synchronized to one of two selectable input reference clocks. An internal high “Q” SAW delay line provides a low jitter clock output. Two clock reference inputs and a selection mux are provided. Either reference clock input can accept a differential clock signal (such as LVPECL or LVDS) or a single-ended clock input (LVCMOS or LVTTL on the non-inverting input). A pin-selected look-up table is used to select the PLL feedback divider (M Div) and reference divider (R Div) as shown in Table 3 on pg. 3. The look-up table provides flexibility in both the overall frequency multiplication ratio (total PLL ratio) and phase detector frequency. External loop filter component values influence the PLL bandwidth, which is used to optimize jitter attenuation characteristics. The device features dual differential inputs with two input selection modes: manual and automatic upon clock failure. (The differential inputs are internally configured for easy single-ended operation.) The M1040 also includes: a Loss of Lock (LOL) indicator, a reference mux state acknowledge pin (REF_ACK), a Narrow Bandwidth control input pin (NBW pin), and a Power-on Initialization (INIT) input (which overrides NBW=0 to facilitate acquisition of phase lock). A single-ended reference clock on the unselected reference input can cause an increase in output clock jitter. For this reason, differential reference inputs are preferred; interference from a differential input on the non-selected input is minimal. Implementation of single-ended input has been facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2, with 50kΩ to Vcc and 50kΩ to ground. Figure 4 shows the input clock structure and how it is used with either LVCMOS / LVTTL inputs or a DC- coupled LVPECL clock. LVCMOS/ LVTTL 50k Ω VCC MUX 50k Ω 0 X VCC 50kΩ 1 127 Ω VCC VCC An automatic input reselection feature, or “AutoSwitch” is also included in the M1040. When the AutoSwitch mode is enabled, the device will automatically switch to the other reference clock input when the currently selected reference clock fails. Reference selection is non-revertive, meaning that only one reference reselection will be made each time that AutoSwitch is re-enabled. Differential Inputs In addition to the AutoSwitch feature, Hitless Switching and Phase Build-out options can be ordered with the device. The Hitless Switching and Phase Build-out options help assure SONET/SDH MTIE and TDEV compliance during either a manual or automatic input reference reselection. Differential LVPECL inputs are connected to both reference input pins in the usual manner. The external load termination resistors shown in Figure 4 (the 127Ω and 82Ω resistors) will work for both AC and DC coupled LVPECL reference clock lines. These provide the 50Ω load termination and the VTT bias voltage. Hitless Switching (HS) provides a controlled output clock phase change during a reference clock reselection. HS is triggered by a Loss of Lock detection by the PLL. Single-ended Inputs 82 Ω LVPECL 50k Ω 127 Ω 50kΩ 82 Ω 50kΩ REF_SEL Figure 4: Input Reference Clocks Single-ended inputs (LVCMOS or LVTTL) are connected to the non-inverting reference input pin (DIF_REF0 or DIF_REF1). The inverting reference input pin (nDIF_REF0 or nDIF_REF1) must be left unconnected. In single-ended operation, when the unused inverting input pin (nDIF_REF0 or nDEF_REF1) is left floating (not connected), the input will self-bias at VCC/2. M1040 Datasheet Rev 0.1 Integrated Circuit Systems, Inc. 4 of 12 ● Communications Modules Revised 11Nov2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1040 Integrated Circuit Systems, Inc. VCSO BASED CLOCK PLL WITH AUTOSWITCH Preliminary Information PLL Operation Loss of Lock Indicator Output Pin The M1040 is a complete clock PLL. It uses a phase detector and configurable dividers to synchronize the output of the VCSO with the selected reference clock. Under normal device operation, when the PLL is locked, the LOL Phase Detector drives LOL to logic 0. Under circumstances when the VCSO cannot lock to the input (as measured by a greater than 4 ns discrepancy between the feedback and reference clock rising edges at the LOL Phase Detector) the LOL output goes to logic 1. The LOL pin will return back to logic 0 when the phase detector error is less than 2 ns. The loss of lock indicator is a low current LVCMOS output. The “M” divider divides the VCSO output frequency, feeding the result into the plus input of the phase detector. The output of the “R” divider is fed into the minus input of the phase detector. The phase detector compares its two inputs. The phase detector output, filtered externally, causes the VCSO to increase or decrease in speed as needed to phase- and frequency-lock the VCSO to the reference input. The value of the M divider directly affects closed loop bandwidth. The relationship between the nominal VCSO center frequency (Fvcso), the M divider, the R divider, and the input reference frequency (Fin) is: M Fvcso = Fin × ---R For the available M divider and R divider look-up table combinations, Tables 3 and 4 on pg. 3 list the Total PLL Ratio as well as Fin when using the M1040-11-155.5200. (See “Ordering Information”, pg. 12.) Due to the narrow tuning range of the VCSO (+200ppm), appropriate selection of all of the following are required for the PLL be able to lock: VCSO center frequency, input frequency, and divider selections. Guidelines Using LOL As described, the LOL pin indicates when the PLL is out-of-lock with the input reference. The LOL condition is also used by the AutoSwitch circuit to detect a lost reference, as described in following sections. LOL is also used by the Hitless Switching and Phase Build-out functions (optional device features). To ensure reliable operation of LOL and guard against false out-of-lock indications, the following conditions should be met: • The phase detector frequency should be no less than • Post-PLL Divider The M1040 features a post-PLL (P) divider. By using the P Divider, the device’s output frequency (Fout) can be the VCSO center frequency (Fvcso) or 1/2 Fvcso. The P_SEL pin selects the value for the P divider: logic 1 sets P to 2, logic 0 sets P to 1. (See Table 5 on pg. 6.) When the P divider is included, the complete relationship for the output frequency (Fout) is defined as: M Fvcso = Fin × ----------------Fout = ------------------P R× P M1040 Datasheet Rev 0.1 Integrated Circuit Systems, Inc. 5MHz, and preferably it should be 10MHz or greater. Phase detector frequency is defined by Fin / R. A higher phase detector frequency will result in lower phase error and less chance of false triggering the LOL phase detector. Refer to Tables 3 and 4 on pg. 3 for phase detector frequency when using the M1040-11-155.5200. The input reference should have an intrinsic jitter of less than 1 ns pk-pk. If reference jitter is greater than 1 ns pk-pk, the LOL circuit might falsely trigger. Due to this limitation, the LOL circuit should not be used in loop timing mode, nor should it be used with a noisy reference clock. Likewise, the AutoSwitch, Hitless Switching, or Phase Build-out features should not be used in loop timing mode or with a noisy reference clock, since these features depend on LOL. Reference Acknowledgement (REF_ACK) Output The REF_ACK (reference acknowledgement) pin outputs the value of the reference clock input that is routed to the phase detector. Logic 1 indicates input pair 1 (nDIF_REF1, DIF_REF1); logic 0 indicates input pair 0 (nDIF_REF0, DIF_REF0). The REF_ACK indicator is an LVCMOS output. 5 of 12 ● Communications Modules Revised 11Nov2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1040 Integrated Circuit Systems, Inc. VCSO BASED CLOCK PLL WITH AUTOSWITCH Preliminary Information AutoSwitch (AUTO) Reference Clock Reselection This device offers an automatic reference clock reselection feature for switching input reference clocks upon a reference clock failure. With the AUTO input pin set to high and the LOL output low, the device is placed into automatic reselection (AutoSwitch) mode. Once in AutoSwitch mode, when LOL then goes high (due to a reference clock fault), the input clock reference is automatically reselected internally, as indicated by the state change of the REF_ACK output. Automatic clock reselection is made only once (it is non-revertive). Re-arming of automatic mode requires placing the device into manual selection (Manual Select) mode (AUTO pin low) before returning to AutoSwitch mode (AUTO pin high). Using the AutoSwitch Feature See alsoTable 5, Example AutoSwitch Sequence. In application, the system is powered up with the device in Manual Select mode (AUTO pin is set low), allowing sufficient time for the reference clock and device PLL to settle. The REF_SEL input selects the reference clock to be used in Manual Select mode and the initial reference clock used in AutoSwitch mode. The REF_SEL input state must be maintained when switching to AutoSwitch mode (AUTO pin high) and must still be maintained until a reference fault occurs. Once a reference fault occurs, the LOL output goes high and the input reference is automatically reselected. The REF_ACK output always indicates the reference selection status and the LOL output always indicates the PLL lock status. A successful automatic reselection is indicated by a change of state of the REF_ACK output and a momentary level high of the LOL output (minimum high time is 10 ns). If an automatic reselection is made to a non-valid reference clock (one to which the PLL cannot lock), the REF_ACK output will change state but the LOL output will remain high. No further automatic reselection is made; only one reselection is made each time the AutoSwitch mode is armed. AutoSwitch mode is re-armed by placing the device into Manual Select mode (AUTO pin low) and then into AutoSwitch mode again (AUTO pin high). Following an automatic reselection and prior to selecting Manual Select mode (AUTO pin low), the REF_SEL pin has no control of reference selection. To prevent an unintential reference reselection, AutoSwitch mode must not be re-enabled until the desired state of the REF_SEL pin is set and the LOL output is low. It is recommended to delay the re-arming of AutoSwitch mode, following an automatic reselection, to ensure the PLL is fully locked on the new reference. In most system configurations, where loop bandwidth is in the range of 100-1000 Hz and damping factor below 10, a delay of 500 ms should be sufficient. Until the PLL is fully locked intermittent LOL pulses may occur. Example AutoSwitch Sequence 0 = Low; 1 = High. Example with REF_SEL initially set to 0 (i.e., DIF_REF0 selected) REF_SEL Selected REF_ACK AUTO LOL Conditions Input Clock Input Output Input Output 0 DIF_REF0 0 0 1 0 DIF_REF0 0 0 -0- 0 DIF_REF0 0 -1- 0 Initialization Device power-up. Manual Select mode. DIF_REF0 input selected reference, not yet locked to. LOL to 0: Device locked to reference (may get intermittent LOL pulses until fully locked). AUTO set to 1: Device placed in AutoSwitch mode (with DIF_REF0 as initial reference clock). Operation & Activation Normal operation with AutoSwitch mode armed, with DIF_REF0 as initial reference clock. 0 DIF_REF0 0 1 0 0 0 DIF_REF0 -DIF_REF1- 0 -1- 1 1 -11 LOL to 1: Clock fault on DIF_REF0, loss of lock indicated by LOL pin, ... ... and immediate automatic reselection to DIF_REF1 (indicated by REF_ACK pin). 0 DIF_REF1 1 1 -0- LOL to 0: Device locks to DIF_REF1 (assuming valid clock on DIF_REF1). -1- DIF_REF1 1 1 0 REF_SEL set to 1: Prepares for Manual Selection of DIF_REF1 before then re-arming AutoSwitch. 1 DIF_REF1 1 -0- 0 AUTO set to 0: Manual Select mode entered briefly, manually selecting DIF_REF1 as reference. 1 DIF_REF1 1 -1- 0 AUTO set to 1: Device is placed in AutoSwitch mode (delay recommended to ensure device fully locked), re-initializing AutoSwitch with DIF_REF1 now specified as the initial reference clock. Re-initialization Table 5: Example AutoSwitch Sequence M1040 Datasheet Rev 0.1 Integrated Circuit Systems, Inc. 6 of 12 ● Communications Modules Revised 11Nov2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1040 Integrated Circuit Systems, Inc. VCSO BASED CLOCK PLL WITH AUTOSWITCH Preliminary Information Optional Hitless Switching and Phase Build-out HS/PBO Triggers The M1040 is available with a Hitless Switching feature that is enabled during device manufacturing. In addition, a Phase Build-out feature is also offered. These features are offered as device options and are specified by device order code. Refer to Section , “Ordering Information” on pg. 12. The HS function (or the combined HS/PBO function) is armed after the device locks to the input clock reference. Once armed, HS is triggered by the occurance of a Loss of Lock condition. This would typically occur as a consequence of a clock reference failure, a clock failure upstream to the M1040, or a M1040 clock reference mux reselection. The Hitless Switching feature (with or without Phase Build-out) is designed for applications where switching occurs between two stable system reference clocks. It should not be used in loop timing applications, or when reference clock jitter is greater than 1 ns pk-pk. Hitless Switching is triggered by the LOL circuit, which is activated by a 4 ns phase transient. This magnitude of phase transient can generated by the CDR (Clock & Data Recovery unit) in loop timing mode, especially during a system jitter tolerance test. It can also be generated by some types of Stratum clock DPLLs (digital PLL), especially those that do not include a post de-jitter APLL (analog PLL). When the Hitless Switching feature is enabled, it is always triggered by LOL, whether in AutoSwitch mode (AUTO pin high) or Select mode (AUTO pin low). For example, in Manual mode, the Hitless Switching feature operates when LOL goes high even if there is no reselection of the input mux. This enables the use of an upstream clock mux (such as on the host card), while still providing MTIE compliance when readjusting to the resultant phase change. When the M1040 is operating in wide bandwidth mode (NBW=0), the optional Hitless Switching function puts the device into narrow bandwidth mode when activated. This allows the PLL to lock the new input clock phase gradually. With proper configuration of the external loop filter, the output clock complies with MTIE and TDEV specifications for GR-253 (SONET) and ITU G.813 (SDH) during input reference clock changes. The optional proprietary Phase Build-out (PBO) function enables the PLL to absorb most of the phase change of the input clock. The PBO function selects a new VCSO clock edge for the PLL Phase Detector feedback clock, selecting the edge closest in phase to the new input clock phase. This reduces re-lock time, the generation of wander, and extra output clock cycles. The Hitless Switching and Phase Build-out functions are triggered by the LOL circuit. For proper operation, a low phase detector frequency must be avoided. See Section , “Guidelines Using LOL” on pg. 5 for information regarding the phase detector frequency. M1040 Datasheet Rev 0.1 Integrated Circuit Systems, Inc. When pin AUTO = 1 (automatic reference reselection mode) HS is used in conjunction with input reselection. When AUTO = 0 (manual mode), HS will still occur upon an input phase transient, however the clock input is not reselected (this enables hitless switching when using an external MUX for clock selection). HS/PBO Operation Once triggered, the following HS/PBO sequence occurs: 1. The HS function disables the PLL Phase Detector and puts the device into NBW (narrow bandwidth) mode. The internal resistor Rin is changed to 2100kΩ . See the Narrow Loop Bandwidth Control Pin (NBW Pin) on pg. 7. 2. If included, the PBO function adds to (builds out) the phase in the clock feedback path (in VCSO clock cycle increments) to align the feedback clock with the (new) reference clock input phase. 3. The PLL Phase Detector is enabled, allowing the PLL to re-lock. 4. Once the PLL Phase Detector feedback and input clocks are locked to within 2 ns for eight consecutive cycles, a timer (WBW timer) for resuming wide bandwidth (in 175 ns) is started. 5. When the WBW timer times out, the device reverts to wide loop bandwidth mode (i.e., Rin is returned to 100kΩ) and the HS/PBO function is re-armed. Narrow Loop Bandwidth Control Pin (NBW Pin) A Narrow Loop Bandwidth control pin (NBW pin) is included to adjust the PLL loop bandwidth. In wide bandwidth mode (NBW=0), the internal resistor Rin is 100kΩ . With the NBW pin asserted, the internal resistor Rin is changed to 2100kΩ . This lowers the loop bandwidth by a factor of about 21 (approximately 2100 / 100) and lowers the damping factor by a factor of about 4.6 (the square root of 21), assuming the same loop filter components. 7 of 12 ● Communications Modules Revised 11Nov2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1040 Integrated Circuit Systems, Inc. VCSO BASED CLOCK PLL WITH AUTOSWITCH Preliminary Information Power-Up Initialization Function (INIT Pin) The initialization function provides a short-term override of the narrow bandwidth mode when the device is powered up in order to facilitate phase locking. Because of the differential signal path design, the implementation consists of two identical complementary RC filters as shown in Figure 5. RLOOP When INIT is set to logic 1, initialization is enabled. With NBW set to logic 1 (narrow bandwidth mode), the initialization function puts the PLL into wide bandwidth mode until eight consecutive phase detector cycles occur without a single LOL event. Once the eight valid PLL locked states have occurred, the PLL bandwidth is automatically reduced to narrow bandwidth mode. CLOOP RPOST CPOST CPOST RLOOP OP_IN When INIT is logic 0, the device is forced into wide bandwidth mode unconditionally. nOP_IN 4 RPOST CLOOP OP_OUT 9 nOP_OUT 8 nVC 5 VC 6 7 Figure 5: External Loop Filter External Loop Filter The M1040 requires the use of an external loop filter components. These are connected to the provided filter pins (see Figure 5). PLL bandwidth is affected by the total “M” (feedback divider) value, loop filter component values, and other device parameters. See Table 6, Example External Loop Filter Component Values, below. PLL Simulator Tool Available A free PC software utility is available on the ICS website (www.icst.com). The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application. For guidance on device or loop filter implementation, contact CMBU (Commercial Business Unit) Product Applications at (508) 852-5400. Example External Loop Filter Component Values1 for M1040-yz-155.5200 VCSO Parameters: KVCO = 200kHz/V, RIN = 100kΩ (pin NBW = 0), VCSO Bandwidth = 700kHz. FREF (MHz) Device Configuration Example External Loop Filter Comp. Values FVCSO MR_SEL2:0 MDiv NBW RLOOP CLOOP RPOST CPOST (MHz) PLL Loop Bandwidth Damping Passband Factor Peaking (dB) 10µF 82kΩ 1000pF 315Hz 5.4 0.07 3.9kΩ 10µF 33kΩ 1000pF 715Hz 6.2 0.05 12kΩ 2.2µF 82kΩ 1000pF 275Hz 3.1 0.20 2.7kΩ 10µF 47kΩ 470pF 980Hz 6.0 0.05 5.6kΩ 4.7µF 82kΩ 1000pF 260Hz 3.0 0.20 19.44 2 155.52 000 8 0 6.8kΩ 3 155.52 010 2 0 77.76 2 155.52 0 1 1 16 0 155.52 3 155.52 100 1 0 155.52 2 155.52 101 8 0 77.76 Nominal Performance Using These Values Table 6: Example External Loop Filter Component Values Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and Passband Peaking. For PLL Simulator software, go to www.icst.com. Note 2: Optimal for system clock filtering. Note 3: Optimal for loop timing mode (LOL or Hitless Switching should not be used). M1040 Datasheet Rev 0.1 Integrated Circuit Systems, Inc. 8 of 12 ● Communications Modules Revised 11Nov2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1040 Integrated Circuit Systems, Inc. VCSO BASED CLOCK PLL WITH AUTOSWITCH Preliminary Information ABSOLUTE MAXIMUM RATINGS1 Symbol Parameter Rating Unit VI Inputs -0.5 to VCC +0.5 V VO Outputs -0.5 to VCC +0.5 V VCC Power Supply Voltage TS V 4.6 Storage Temperature o -45 to +100 C Table 7: Absolute Maximum Ratings Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. RECOMMENDED CONDITIONS OF OPERATION Symbol Parameter VCC TA Positive Supply Voltage Ambient Operating Temperature Commercial Industrial Min Typ Max Unit 3.135 3.3 3.465 V 0 -40 oC +70 +85 oC Table 8: Recommended Conditions of Operation M1040 Datasheet Rev 0.1 Integrated Circuit Systems, Inc. 9 of 12 ● Communications Modules Revised 11Nov2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1040 Integrated Circuit Systems, Inc. VCSO BASED CLOCK PLL WITH AUTOSWITCH Preliminary Information ELECTRICAL SPECIFICATIONS DC Characteristics Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 150-175MHz, LVPECL outputs terminated with 50Ω to VCC - 2V Symbol Parameter Power Supply VCC Positive Supply Voltage ICC Power Supply Current All Differential Inputs VP-P Peak to Peak Input Voltage VCMR Common Mode Input CIN Input Capacitance Differential Inputs with Pull-down IIH Input High Current (Pull-down) IIL Input Low Current (Pull-down) Differential Inputs Biased to VCC/2 All LVCMOS / LVTTL Inputs IIH Input High Current (Biased) IIL Input Low Current (Biased) Rbias Biased to Vcc/2 VIH Input High Voltage VIL Input Low Voltage CIN Input Capacitance LVCMOS / LVTTL Inputs with Pull-down LVCMOS / LVTTL Inputs with Pull-UP Differential Outputs IIH Input High Current (Pull-down) IIL Input Low Current (Pull-down) LVCMOS Outputs DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 DIF_REF0, DIF_REF1 Min Typ Max Unit Conditions 3.135 3.3 3.465 V 175 225 V 0.5 Vcc - .85 V 4 pF 150 µA µA -5 Rpulldown Internal Pull-down Resistance 150 µA µA -150 VIN = 0 to 3.456V See Figure 4 2 AUTO, REF_SEL,, P_SEL, MR_SEL2, MR_SEL1, MR_SEL0, INIT, NBW IIH Input High Current (Pull-UP) IIL Input Low Current (Pull-UP) Rpullup Internal Pull-UP Resistance VOH Output High Voltage VOL Output Low Voltage VP-P Peak to Peak Output Voltage 1 VOH Output High Voltage VOL Output Low Voltage Vcc + 0.3 V -0.3 AUTO, REF_SEL, P_SEL 0.8 V 4 pF 150 µA µA -5 Rpulldown Internal Pull-down Resistance M1040 Datasheet Rev 0.1 µA -150 FOUT1, nFOUT1 FOUT0, nFOUT0 Vcc - 1.4 Vcc - 1.0 V Vcc - 2.0 Vcc - 1.7 V 0.4 0.85 V 2.4 VCC V IOH= 1mA GND 0.4 V IOL= 1mA LOL, REF_ACK Communications Modules VCC = 3.456V VIN = 0 V kΩ 50 Table 9: DC Characteristics 10 of 12 ● µA 5 MR_SEL2, MR_SEL1, MR_SEL0, INIT, NBW VCC = VIN = 3.456V kΩ 50 Note 1: Single-ended measurement. See Figure 6, Input and Output Rise and Fall Time, on pg. 11. Integrated Circuit Systems, Inc. VCC = VIN = 3.456V kΩ 50 nDIF_REF0, nDIF_REF1 mA 0.15 Revised 11Nov2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1040 Integrated Circuit Systems, Inc. VCSO BASED CLOCK PLL WITH AUTOSWITCH Preliminary Information ELECTRICAL SPECIFICATIONS (CONTINUED) AC Characteristics Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 150-175MHz, LVPECL outputs terminated with 50Ω to VCC - 2V Symbol Parameter PLL Loop Constants 1 Min Max Unit Conditions 15 700 MHz 175 MHz FIN Input Frequency DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 FOUT Output Frequency FOUT0, nFOUT0, FOUT1, nFOUT1 62.5 APR Absolute Pull-Range of VCSO Commercial ±120 ±50 KVCO VCO Gain RIN Internal Loop Resistor Industrial Wide Bandwidth Narrow Bandwidth BWVCSO VCSO Bandwidth Phase Noise and Jitter 1kHz Offset Φn Single Side Band Phase Noise @155.52MHz J(t) Jitter (rms) @155.52MHz odc Output Duty Cycle 2 tR tF 10kHz Offset 100kHz Offset 12kHz to 20MHz Output Rise Time 2 for FOUT0, nFOUT0, FOUT1, nFOUT1 Output Fall Time 2 for FOUT0, nFOUT0, FOUT1, nFOUT1 Typ ±200 ±150 200 ppm ppm kHz/V 100 kΩ 2100 kΩ 700 kHz -72 -94 -123 dBc/Hz Fin=19.44_MHz dBc/Hz Tot. PLL ratio = 8. See pg. 3 dBc/Hz 0.4 0.6 ps 45 50 55 % 350 450 550 ps 20% to 80% 350 450 550 ps 20% to 80% Table 10: AC Characteristics Note 1: Parameters needed for PLL Simulator software; see Table 6, Example External Loop Filter Component Values, on pg. 8. Note 2: See Parameter Measurement Information on pg. 11. PARAMETER MEASUREMENT INFORMATION Input and Output Rise and Fall Time 80% Output Duty Cycle nFOUT 80% V P -P Clock Inputs 20% and Outputs 20% tF tR Figure 6: Input and Output Rise and Fall Time FOUT odc = Differential Input Level tPW (Output Pulse Width) tPW tPERIOD tPERIOD VCC - 0.85 Figure 8: Output Duty Cycle nDIF_CLK VP-P VCMR Cross Points DIF_CLK + 0.5 Figure 7: Differential Input Level M1040 Datasheet Rev 0.1 Integrated Circuit Systems, Inc. 11 of 12 ● Communications Modules Revised 11Nov2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 Integrated Circuit Systems, Inc. M1040 Preliminary Information VCSO BASED CLOCK PLL WITH AUTOSWITCH DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER Mechanical Dimensions: Figure 9: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier ORDERING INFORMATION Part Numbering Scheme Part Number: Standard VCSO Output Frequencies (MHz)* M1040- 1z - xxx.xxxx Output type 1 = LVPECL (For CML or LVDS clock output, consult factory) Hitless Switching / Phase Build-out Options 1 = none 2 = Hitless Switching 3 = Hitless Switching with Phase Build-out Temperature “ - ” = 0 to +70 oC (commercial) I = - 40 to +85 oC (industrial) PLL Frequency (MHz) See Table 11, right. Consult ICS for other frequencies. 155.5200 167.3280 156.2500 167.3316 156.8324 167.7097 161.1328 168.0400 166.6286 172.6423 167.2820 173.3708 Table 11: Standard VCSO Output Frequencies * Figure 10: Part Numbering Scheme Fout can equal Fvcso divided by: 1 or 2 Consult ICS for the availability of other VCSO frequencies. Example Part Numbers VCSO Frequency (MHz) Temperature commercial industrial commercial industrial 155.52 156.25 Order Part Number (Examples) M1040- 11 - 155.5200 M1040- 11I 155.5200 M1040 - 11 - 156.2500 M1040- 11I 156.2500 Table 12: Example Part Numbers While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M1040 Datasheet Rev 0.1 Integrated Circuit Systems, Inc. 12 of 12 ● Communications Modules Revised 11Nov2003 ● w w w. i c s t . c o m ● tel (508) 852-5400