TI SN75176A

SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D OR P PACKAGE
(TOP VIEW)
Bidirectional Transceiver
Meets or Exceeds the Requirements of
ANSI Standards EIA/TIA-422-B and ITU
Recommendation V.11
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
3-State Driver and Receiver Outputs
Individual Driver and Receiver Enables
Wide Positive and Negative Input /Output
Bus Voltage Ranges
Driver Output Capability . . . ± 60 mA Max
Thermal-Shutdown Protection
Driver Positive- and Negative-Current
Limiting
Receiver Input Impedance . . . 12 kΩ Min
Receiver Input Sensitivity . . . ± 200 mV
Receiver Input Hysteresis . . . 50 mV Typ
Operates From Single 5-V Supply
Low Power Requirements
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
description
The SN75176A differential bus transceiver is a monolithic integrated circuit designed for bidirectional data
communication on multipoint bus-transmission lines. It is designed for balanced transmission lines and meets
ANSI Standard EIA/TIA-422-B and ITU Recommendation V.11.
The SN75176A combines a 3-state differential line driver and a differential input line receiver, both of which
operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables,
respectively, that can be externally connected together to function as a direction control. The driver differential
outputs and the receiver differential inputs are connected internally to form differential input /output (I/O) bus
ports that are designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. These
ports feature wide positive and negative common-mode voltage ranges making the device suitable for party-line
applications.
The driver is designed to handle loads up to 60 mA of sink or source current. The driver features positive- and
negative-current limiting and thermal shutdown for protection from line fault conditions. Thermal shutdown is
designed to occur at a junction temperature of approximately 150°C. The receiver features a minimum input
impedance of 12 kΩ, an input sensitivity of ± 200 mV, and a typical input hysteresis of 50 mV.
The SN75176A can be used in transmission-line applications employing the SN75172 and SN75174 quadruple
differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
The SN75176A is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
Function Tables
DRIVER
OUTPUTS
INPUT
D
ENABLE
DE
H
H
H
L
L
H
L
H
X
L
Z
Z
A
B
RECEIVER
DIFFERENTIAL INPUTS
A–B
ENABLE
RE
OUTPUT
R
VID ≥ 0.2 V
– 0.2 V < VID < 0.2 V
L
H
L
?
VID ≤ – 0.2 V
X
L
L
H
Z
Open
L
?
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
logic symbol†
DE
RE
D
3
2
logic diagram (positive logic)
DE
EN1
EN2
D
1
4
1
R
1
6
7
A
B
RE
R
3
4
2
1
2
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
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6
7
A
B
Bus
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF A AND B I/O PORTS
TYPICAL OF RECEIVER OUTPUT
VCC
VCC
VCC
85 Ω
NOM
R(eq)
16.8 kΩ
NOM
Input
960 Ω
NOM
960 Ω
NOM
Output
GND
Driver input: R(eq) = 3 kΩ NOM
Enable inputs: R(eq) = 8 kΩ NOM
R(eq) = equivalent resistor
Input/Output
Port
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 10 V to 15 V
Enable input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
DISSIPATION RATING TABLE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70_C
POWER RATING
TA = 105_C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
261 mW
P
1100 mW
8.8 mW/°C
704 mW
396 mW
PACKAGE
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SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
recommended operating conditions
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode), VI or VIC
High-level input voltage, VIH
D, DE, and RE
Low-level input voltage, VIL
D, DE, and RE
Low level output current,
current IOL
Low-level
TYP
MAX
UNIT
5
5.25
V
12
V
–7
2
V
0.8
Differential input voltage, VID (see Note 2)
High level output current,
High-level
current IOH
MIN
4.75
Driver
Receiver
Driver
V
– 60
mA
– 400
µA
60
Receiver
8
Operating free-air temperature, TA
0
70
NOTE 2: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
4
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V
± 12
mA
°C
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
– 1.5
V
VIK
Input clamp voltage
II = – 18 mA
VOH
High level output voltage
High-level
VIH = 2 V,,
IOH = – 33 mA
VIL = 0.8 V,,
37
3.7
V
VOL
Low level output voltage
Low-level
VIH = 2 V,,
IOH = 33 mA
VIL = 0.8 V,,
11
1.1
V
|VOD1|
Differential output voltage
IO = 0
RL = 100 Ω,
See Figure 1
2
2.7
RL = 54 Ω,
See Figure 1
1.5
2.4
|VOD2|
Differential output voltage
∆|VOD|
Change in magnitude of differential output voltage ‡
VOC
Common-mode output voltage§
∆|VOC|
Change
g in magnitude
g
of common-mode output
voltage ‡
IO
Output current
IIH
IIL
High-level input current
Low-level input current
VI = 2.4 V
VI = 0.4 V
IOS
Short-circuit output current
VO = – 7 V
VO = VCC
2VOD2
RL = 54 Ω or 100 Ω,
See Figure 1
Output disabled,,
See Note 3
VO = 12 V
VO = – 7 V
Supply current (total package)
No load
V
± 0.2
V
3
V
± 0.2
02
V
1
– 0.8
mA
20
µA
– 400
µA
– 250
250
VO = 12 V
ICC
V
mA
500
Outputs enabled
35
50
Outputs disabled
26
40
mA
† All typical values are at VCC = 5 V and TA = 25°C.
‡ ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC respectively, that occur when the input is changed from a high level to a low
level.
§ In ANSI Standard EIA/TIA-422-B, VOC, which is the average of the two output voltages with respect to GND, is called output offset voltage, VOS.
NOTE 3: This applies for both power on and off; refer to ANSI Standard EIA/TIA-422-B for exact conditions.
switching characteristics, VCC = 5 V, TA = 25°C
PARAMETER
td(OD)
tt(OD)
Differential-output delay time
tPZH
tPZL
tPHZ
tPLZ
TEST CONDITIONS
MIN
TYP
MAX
40
60
UNIT
ns
65
95
ns
RL = 60 Ω
Ω,
See Figure 3
Output enable time to high level
RL = 110 Ω,
See Figure 4
55
90
ns
Output enable time to low level
RL = 110 Ω,
See Figure 5
30
50
ns
Output disable time from high level
RL = 110 Ω,
See Figure 4
85
130
ns
Output disable time from low level
RL = 110 Ω,
See Figure 5
20
40
ns
Differential-output transition time
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5
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT +
VIT–
Positive-going input threshold voltage
Vhys
VIK
Input hysteresis voltage (VIT + – VIT –)
Enable clamp voltage
II = – 18 mA
VOH
High level output voltage
High-level
VID = 200 mV,,
See Figure 2
IOH = – 400 µ
µA,,
VOL
Low level output voltage
Low-level
VID = – 200 mV,,
See Figure 2
IOL = 8 mA,,
IOZ
High-impedance-state output current
VO = 0.4 V to 2.4 V
Negative-going input threshold voltage
II
Line input current
IIH
IIL
High-level enable input current
ri
Input resistance
IOS
Short-circuit output current
ICC
Supply current (total package)
VO = 2.7 V,
VO = 0.5 V,
IO = – 0.4 mA
IO = 8 mA
MIN
TYP†
0.2
– 0.2‡
V
mV
– 1.5
27
2.7
V
V
VI = 12 V
VI = – 7 V
0 45
0.45
V
± 20
µA
1
– 0.8
VIH = 2.7 V
VIL = 0.4 V
mA
20
µA
– 100
µA
– 85
mA
12
kΩ
– 15
No load
UNIT
V
50
Other input = 0 V,,
See Note 3
Low-level enable input current
MAX
Outputs enabled
35
50
Outputs disabled
26
40
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 3: This applies for both power on and power off. Refer to ANSI Standard EIA/TIA-422-B for exact conditions.
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
tPLH
tPHL
Propagation delay time, low-to-high-level output
tPZH
tPZL
Output enable time to high level
tPHZ
tPLZ
Output disable time from high level
6
Propagation delay time, high-to-low-level output
Output enable time to low level
Output disable time from low level
VID = – 1.5
1 5 V to 1.5
1 5 V,
V
See Figure 7
See Figure 7
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See Figure 6
MIN
TYP
MAX
21
35
UNIT
ns
23
35
ns
10
30
ns
12
30
ns
20
35
ns
17
25
ns
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
RL
VID
2
VOD2
RL
2
VOH
VOC
+IOL
VOL
0V
– IOH
Figure 2. Receiver VOH and VOL
Figure 1. Driver VOD and VOC
3V
Input
Generator
(see Note A)
RL = 60 Ω
CL = 50 pF
(see Note B)
50 Ω
0V
td(OD)
td(OD)
Output
Output
3V
1.5 V
1.5 V
CL
50%
10%
90%
tt(OD)
TEST CIRCUIT
≈ 2.5 V
50%
10%
≈ – 2.5 V
tt(OD)
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Voltage Waveforms
Output
3V
S1
Input
1.5 V
1.5 V
0 or 3 V
Generator
(see Note A)
50 Ω
CL = 50 pF
(see Note B)
0V
0.5 V
tPZH
RL = 110 Ω
VOH
Output
TEST CIRCUIT
2.3 V
tPHZ
Voff ≈ 0 V
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
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7
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
5V
3V
RL = 110 Ω
S1
1.5 V
1.5 V
0V
Output
3 V or 0
Generator
(see Note A)
Input
tPZL
tPLZ
CL = 50 pF
(see Note B)
50 Ω
Output
5V
0.5 V
2.3 V
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 5. Driver Test Circuit and Voltage Waveforms
3V
Generator
(see Note A)
Output
51 Ω
Input
1.5 V
1.5 V
0V
1.5 V
CL = 15 pF
(see Note B)
0V
tPLH
tPHL
VOH
Output
1.3 V
1.3 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 6. Receiver Test Circuit and Voltage Waveforms
8
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SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
S1
1.5 V
2 kΩ
–1.5 V
S2
5V
CL = 15 pF
(see Note B)
Generator
(see Note A)
5 kΩ
1N916 or Equivalent
50 Ω
S3
TEST CIRCUIT
3V
Input
3V
1.5 V
S1 to 1.5 V
0 V S2 Open
S3 Closed
tPZH
Input
tPZL
1.5 V
S1 to –1.5 V
0 V S2 Closed
S3 Open
VOH
≈ 4.5 V
1.5 V
Output
0V
Output
1.5 V
VOL
3V
Input
3V
S1 to 1.5 V
S2 Closed
S3 Closed
1.5 V
Input
S1 to – 1.5 V
S2 Closed
S3 Closed
1.5 V
0V
0V
tPHZ
0.5 V
tPLZ
≈ 1.3 V
VOH
Output
Output
0.5 V
≈ 1.3 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 7. Receiver Test Circuit and Voltage Waveforms
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9
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
TYPICAL CHARACTERISTICS
DRIVER
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
VCC = 5 V
TA = 25°C
4.5
4
3.5
3
2.5
2
1.5
1
4
3.5
3
2.5
2
1.5
1
0.5
0.5
0
VCC = 5 V
TA = 25°C
4.5
VOL – Low-Level Output Voltage – V
VOH – High-Level Output Voltage – V
VOH
5
0
– 20
– 40
– 60
– 80
– 100
IOH – High-Level Output Current – mA
0
– 120
0
20
40
60
80
100
IOL – Low-Level Output Current – mA
Figure 9
Figure 8
DRIVER
RECEIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
VCC = 5 V
TA = 25°C
3.5
VOL
VOL – Low-Level Output Voltage – V
VOD – Differential Output Voltage – V
VOD
4
3
2.5
2
1.5
ÁÁ
ÁÁ
ÁÁ
1
0.5
0
0
10
20
30 40 50 60 70 80
IO – Output Current – mA
90 100
VCC = 5 V
TA = 25°C
0.5
0.4
0.3
0.2
0.1
0
0
Figure 10
10
120
5
10
15
20
25
IOL – Low Level Output Current – mA
Figure 11
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30
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
TYPICAL CHARACTERISTICS
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
VCC = 5 V
VID = – 0.2 V
IOL = 8 mA
VO
V
O – Output Voltage – V
0.3
ÁÁ
ÁÁ
0.2
ÁÁ
ÁÁ
ÁÁ
VID = 0.2 V
Load = 8 kΩ to GND
TA = 25°C
4
0.4
0.1
VCC = 5 V
3
VCC = 5.25 V
VCC = 4.75 V
2
1
0
0
0
10
70
20
30
50
40
60
TA – Free-Air Temperature – °C
0
80
0.5
2
1
1.5
VI – Enable Voltage – V
Figure 12
2.5
3
Figure 13
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
6
VID = 0.2 V
Load = 1 kΩ to VCC
TA = 25°C
VCC = 5.25 V
5
V
VO
O – Output Voltage – V
VOL – Low-Levcel Output Voltage – V
VOL
0.5
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
ÁÁ
ÁÁ
VCC = 4.75 V
VCC = 5 V
4
3
2
1
0
0
0.5
1
1.5
2
VI – Enable Voltage – V
2.5
3
Figure 14
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11
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
APPLICATION INFORMATION
SN65176A
SN65176A
RT
RT
Up to 32
Transceivers
NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.
Figure 15. Typical Application Circuit
12
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright  1998, Texas Instruments Incorporated