Integrated Circuit Systems, Inc. ICS9169-01 Frequency Generator and Integrated Buffers for Intel Pentium and Pentium ProTM µP's General Description Features The ICS9169-01 generates all clocks required for high speed RISC or CISC microprocessor systems such as 486, Pentium/ Pentium Pro™, PowerPC™, etc. Four different reference frequency multiplying factors are externally selectable with smooth frequency transitions. These multiplying factors can be customized for specific applications. A test mode is provided to drive all clocks directly. • High drive BCLK outputs typically provide greater than 1V/ ns slew rate into 30pF loads. PCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. • • • • • • • • Generates four processor, six bus, three 14.318 MHz and one 48 MHz clock for ISA bus, audio, super I/O and bus bridge devices Supports the Intel MARS chip set Synchronous clocks skew matched to 250ps window on PCLKs and 500ps window on BCLKs Test clock mode eases system design Selectable multiplying ratios Custom configurations available Output frequency ranges to 100 MHz (depending on option) 3.0V - 5.5 V supply range 28-pin SOIC and 28-pin SSOP (209-mil) packages Applications • Ideal for high-speed RISC or CISC systems such as 486, Pentium, Pentium Pro, PowerPC, etc. Block Diagram PLL CLOCK GEN X2 X1 48 MHz XTAL OSC REF(0:2) OEN FS0 FS1 PLL CLOCK GEN SYNC PCLK(0:3) REG BCLK(0:5) Pentium is a trademark of Intel Corporation PowerPC is a trademark of Motorola Corporation 9169-01RevE 08/28/98 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9169-01 Pin Configuration Functionality FS1 FS0 *VCO 0 0 1 1 0 1 0 1 230/33x X1 212/23x X1 176/21x X1 Test mode X1, REF (MHz) 14.31818 14.31818 14.31818 TCLK PCLK(0:3) (MHz) 50 (49.7) 66 (66.5) 60 (59.9) TCLK/2 *VCO range is limited from 60 - 200 MHz PCLK(0:3) VCO/2 TCLK/2 BCLK(0:5) PCLK/2 TCLK/4 48 MHz 48 MHz TCLK/2 28 Pin SOIC 28 Pin SSOP Pin Descriptions PIN NUMBER PIN NAME TYPE 2 X1 IN 3 4, 11, 23 X2 GND OUT PWR DESCRIPTION XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12.16 MHz crystal, nominally 14.31818 XTAL output which includes XTAL load capacitance. Ground for logic, PCLK and fixed frequency output buffers. GND PWR Ground for BCLK output buffers. 1, 8, 26 VDD PWR Power for logic, PCLK and fixed frequency output buffers. 14, 20 VDD PWR Power for BCLK output buffers. 6, 7, 9, 10 PCLK(0:3) OUT 13, 12 FS(0:1) IN 15, 16, 18 19, 21, 22 BCLK(0:5) OUT 5 OEN IN 24 48MHz OUT Fixed 48 MHz clock (with 14.318 MHz input). 28, 27, 25 REF(0:2) OUT REF is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 MHz. 17 Processor clock outputs which are a multiple of the input reference frequency as shown in the table above. Frequency multiplier select pins. See table above. These inputs have internal pull-up devices. Bus clock outputs are fixed at 1/2 the PCLK frequency. OEN tristates all outputs when low. This input has an internal pull-up device. Note 1: BCLK buffers cannot be supplied with 5 volts (pins 14 and 20) if CPU and fixed frequencies (pins 1, 8, and 26) are being supplied with 3.3 volts 2 ICS9169-01 Absolute Maximum Ratings Supply Voltage.................................................................................................................................................................. 7.0 V Logic Inputs ............................................................................................................................ GND - 0.5 V to VDD + 0.5 V . Ambient Operating Temperature ........................................................................................................................... 0 to +70 C Storage Temperature ......................................................................................................................................... -65 to +150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stess specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3 V VDD = 3.0 - 3.7 V, TA = 0 - 70oC unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL - - 0.2VDD V Input High Voltage VIH 0.7VDD - - V Input Low Current IIL VIN = 0 V -28.0 -10.5 - µA Input High Current IIH VIN = VDD -5.0 - 5.0 µA Output Low Current1 IOL VOL = 0.8 V; for PCLKs & BCLKs 30.0 47.0 - mA Output High Current1 IOH VOL = 2.0 V; for PCLKs & BCLKs - -66.0 -42.0 mA Output Low Current1 IOL VOL=0.8V; for fixed CLKs 25.0 38.0 - mA Output High Current1 IOH VOL=2.0V; for fixed CLKs - -47.0 -30.0 mA Output Low Voltage1 VOL IOL = 15 mA; for PCLKs & BCLKs - 0.3 0.4 V Output High Voltage1 VOH IOH = -30 mA; for PCLKs & BCLKs 2.4 2.8 - V Output Low Voltage1 VOL IOL=12.5mA; for fixed CLKs - 0.3 0.4 V Output High Voltage1 VOH IOH = -20mA; for fixed CLKs 2.4 2.8 - V Supply Current IDD @ 66.5 MHz; all outputs unloaded - 55 110 mA Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 3 Stresses a stess spec operation periods m ICS9169-01 Electrical Characteristics at 3.3 V VDD = 3.0 - 3.7 V, TA = 0 - 70oC unless otherwise stated AC Characteristics PARAMETER SYMBOL TEST CONDITIONS Jitter, One Sigma1 Tj1s1 Jitter, Absolute1 Tjab1 Jitter, One Sigma1 Tj1s2 20pF load, 0.8 to 2.0V PCLK & BCLK 20pF load, 2.0 to 0.8V PCLK & BCLK 20pF load, 20% to 80% PCLK & BCLK 20pF load, 80% to 20% PCLK & BCLK 20pF load @ VOUT = 1.4 V PCLK & BCLK Clocks; Load=20pF, FOUT >25 MHz PCLK & BCLK Clocks; Load=20pF, FOUT >25 MHz Fixed CLK; Load=20pF Tjab2 Fixed CLK; Load=20pF Rise Time1 Tr1 Fall Time1 Tf1 Rise Time1 Tr2 Fall Time1 Tf2 Duty Cycle1 Dt 1 Jitter, Absolute 1 Input Frequency Logic Input Capacitance1 Crystal Oscillator Capacitance1 Fj MIN TYP MAX UNITS - 0.9 1.5 ns - 0.8 1.4 ns - 1.5 2.5 ns - 1.4 2.4 ns 45 50 55 % - 50 150 ps -250 - 250 ps - 1 3 % -5 2 5 % 12.0 14.318 16.0 MHz CIN Logic input pins - 5 - pF CINX X1, X2 pins - 18 - pF Power-on Time1 ton From VDD=1.6V to 1st crossing of 66.5 MHz VDD supply ramp < 40 ms - 2.5 4.5 ms Frequency Settling Time1 ts From 1st crossing of acquisition to < 1% settling - 2.0 4.0 ms Clock Skew Window1 Tsk1 PCLK to PCLK; Load=20pF; @1.4V - 150 250 ps Clock Skew Window1 Tsk2 BCLK to BCLK; Load=20pF; @1.4V - 300 500 ps Clock Skew Window1 Tsk3 PCLK to BCLK; Load=20pF; @1.4V 1 2.6 5 ns Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 4 ICS9169-01 Electrical Characteristics at 5.0 V VDD = 4.5 - 5.5 V, TA = 0 - 70 oC unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL - - 0.8 V Input High Voltage VIH 2.4 - - V Input Low Current IIL VIN = 0 V -45 -15 - µA Input High Current IIH VIN = VDD -5.0 - 5.0 µA Output Low Current1 IOL 36.0 62.0 - mA Output High Current1 IOH - -152 -90.0 mA Output Low Current1 IOL VOL = 0.8V; for fixed CLKs 30.0 50.0 - mA Output High Current1 IOH VOL=2.0V; for fixed CLKs - -110.0 -65.0 mA Output Low Voltage1 VOL - 0.25 0.4 V Output High Voltage1 VOH 2.4 4.0 - V Output Low Voltage1 VOL IOL = 20 mA; for PCLKs & BCLKs IOH = -70 mA; for PCLKs & BCLKs IOL = 15mA; for fixed CLKs - 0.2 0.4 V 1 Output High Voltage VOH IOH=-50mA; for fixed CLKs 2.4 4.7 - V Supply Current1 IDD @ 66.5 MHz; all outputs unloaded - 80.0 160.0 mA VOL = 0.8 V; for PCLKs & BCLKs VOL = 2.0 V; for PCLKs & BCLKs Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 5 ICS9169-01 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1) All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram. 2) 47 ohm / 56pf RC termination should be used at 50MHz and higher clock loads. 3) Optional crystal load capacitors are recommended. Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01µF ceramic Connections to VDD: 6 ICS9169-01 Electrical Characteristics at 5.0 V VDD = 4.5 - 5.5 V, TA = 0 - 70 oC unless otherwise stated AC Characteristics PARAMETER SYMBOL TEST CONDITIONS 20pF load, 0.8 to 2.0V PCLK & BCLK 20pF load, 2.0 to 0.8V PCLK & BCLK 20pF load, 20% to 80% PCLK & BCLK 20pF load, 80% to 20% PCLK & BCLK MIN TYP MAX UNITS - 0.55 0.95 ns - 0.52 0.90 ns - 1.2 2.1 ns - 1.1 2.0 ns Rise Time1 Tr1 Fall Time1 Tf1 Rise Time1 Tr2 Fall Time1 Tf2 Duty Cycle1 Dt1 20pF load @ VOUT = 50% of VDD 45 50 55 % Duty Cycle1 Dt2 20pF load @ VOUT = 1.4 V 50 55 60 % Jitter, One Sigma1 Tj1s1 PCLK & BCLK Clocks; Load=20pF; R=33 Ω FOUT > 25 MHz - 50 150 ps Jitter, Absolute1 Tjab1 PCLK & BCLK Clocks; Load=20pF; R=33 Ω FOUT > 25 MHz -250 - 250 ps Jitter, One Sigma1 Tjis2 - 1 3 % Jitter, Absolute1 Tjab2 -5 2 5 % Input Frequency1 Fi 12.0 14.318 16.0 MHz Fixed CLK; Load=20pF R=33 Ω Fixed CLK; Load=20pF R=33 Ω Logic Input Capacitance1 CIN Logic input pins - 5 - pF Crystal Oscillator Capacitance1 CINX X1, X2 pins - 18 - pF Power-on Time1 ton From V=1.6V to 1st crossing of 66.5 MHz VDD supply ramp < 40 ms - 2.5 4.5 ms Frequency Settling Time1 ts From 1st crossing of acquisition to < 1% settling - 2.0 4.0 ms - 150 250 ps - 300 500 ps 1 2.6 5 ns Clock Skew Window1 Tsk1 Clock Skew Window1 Tsk2 Clock Skew Window1 Tsk3 PCLK to PCLK; Load=20pF; @1.4V BCLK to BCLK; Load=20pF; @1.4V PCLK to BCLK; Load=20pF; @1.4V Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 7 ICS9169-01 L ± 0.008 0.018 0.029 Typ. 5˚ Typ. ± 5 5˚ Typ. 0.047R 0.296 ± 0.005 0.406 ± 0.010 .0.328 ± 0.010 0.015 x 45˚ Pin 1 0.092 ± 0.005 0.020 0.041 ± 0.003 0.101 ± 0.010 0.010 0.050 Pitch typ. LEAD COUNT 28L DIMENSION L 0.704 0.008 ± 0.006 SOIC Package Ordering Information ICS9169M-01 Example: ICS XXXX M-PPP Pattern Number (2 or 3-digit number for parts with ROM code pattern) Package Type M = SOIC Device Type (consists of 3 or 4-digit numbers) Prefix ICS, AV=Standard Device 8 ICS9169-01 D/2 1.14 2.36 DIA. PIN E/2 1.14 H TOP VIEW BOTTOM VIEW D C SEATING PLANE A e B A2 SEE DETAIL A A1 C E SIDE VIEW END VIEW PARTING LINE α L DETAIL A SSOP Package 9 ICS9169-01 Package dimensions - SSOP package SYMBOL COMMON DIMENSIONS NOTE NOTE 4 VARIATIONS D 6 MIN. NOM. MAX. MIN. NOM. MAX. A A 0.68 0.002 0.73 0.005 0.78 0.008 AA AB 0.239 0.239 0.244 0.244 0.249 0.249 14 16 A B 0.066 0.010 0.068 0.012 0.070 0.015 AC AD 0.278 0.318 0.284 0.323 0.289 0.328 20 24 C 0.005 0.006 0.008 AE 0.397 0.402 0.407 28 AF 0.397 0.402 0.407 30 D E See Variations 0.205 e 0.209 4 0.212 4 0.0256 BSC H 0.301 0.307 0.311 L 0.022 0.030 0.037 N See Variations 4 8 0 5 6 Table dimensions in inches Ordering Information ICS9169F-01 Example: ICS XXXX M-PPP Pattern Number (2 or 3-digit number for parts with ROM code pattern) Package Type F=SSOP Device Type (consists of 3 or 4-digit numbers) Prefix ICS, AV=Standard Device 10 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.