V104 PRELIMINARY 10 BIT LVDS RECEIVER FOR VIDEO General Description Features The V104 10 Bit LVDS Receiver for Video is designed to support video data transmission between display engines and video processing engines for television and projector applications. The V104 supports up to WXGA resolutions for Plasma, Rear Projection, Front Projection, CRT and LCD applications. • • • • • • • • • The V104 converts the 6 LVDS (Low Voltage Differential Signaling) video data stream pairs to 35 CMOS/TTL data bits with a rising or falling edge clock. The clock edge selection is performed using a dedicated pin. Pin & function compatible with the THC63LVD104A Wide pixel clock range: 8 - 90 MHz Supports resolutions from 480p to WXGA Internal PLL does not require external loop filter Clock edge selection for TTL alignment selectable Power down mode Single 3.3V supply Low power consumption CMOS design 64-pin TQFP lead free package In conjunction with the V103 transmitter, the V104 can transmit 10 bits per color (R, G, B) along with 5 bits of control and timing data (HSYNC, VSYNC, DE, CNTL1, CNTL2) over a low EMI, low bus width connection including connectors and standard LVDS cabling. Block Diagram CMOS/TTL Output LVDS Input 7 RA6-RA0 7 RB6-RB0 7 RC6-RC0 RA+/RB+/Serial to Parallel RC+/- 7 RD+/- 7 RE+/PLL RCLK+/- RD6-RD0 RE6-RE0 CLKOUT (8 to 90 MHz) CMOS/TTL Input TEST PD OE R/F V104 Datasheet 1 1/12/05 Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m PRELIMINARY V104 10 BIT LVDS RECEIVER FOR VIDEO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PVCC PGND RE+ RERD+ RDLGND RCLK+ RCLKRC+ RCLVCC RB+ RBRA+ RA- Pin Assignment 64-pin TQFP 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC RA0 RA1 RA2 GND RA3 RA4 RA5 RA6 RB0 RB1 VCC RB2 RB3 RB4 RB5 RD4 RD3 RD2 RD1 RD0 RC6 VCC RC5 RC4 RC3 RC2 RC1 RC0 GND CLKOUT RB6 GND TEST PD OE R/F RE6 RE5 RE4 VCC RE3 RE2 RE1 RE0 RD6 RD5 GND Pin Descriptions Pin Number Pin Name Pin Type 50, 49 RA+, RA- LVDS IN LVDS Data In 52, 51 RB+, RB- LVDS IN LVDS Data In 55, 54 RC+, RC- LVDS IN LVDS Data In 60, 59 RD+, RD- LVDS IN LVDS Data In 62, 61 RE+, RE- LVDS IN LVDS Data In 57, 56 RCLK+, RCLK- LVDS IN LVDS Clock In 40, 41, 42, 43, 45, 46, 47 RA6 ~ RA0 OUT CMOS/TTL Data Outputs 32, 33, 34, 35, 36, 38, 39 RB6 ~ RB0 OUT CMOS/TTL Data Outputs 22, 24, 25, 26, 27, 28, 29 RC6 ~ RC0 OUT CMOS/TTL Data Outputs 14, 15, 17, 18, 19, 20, 21 RD6 ~ RD0 OUT CMOS/TTL Data Outputs V104 Datasheet Pin Description 2 1/12/05 Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m PRELIMINARY V104 10 BIT LVDS RECEIVER FOR VIDEO Pin Number Pin Name Pin Type Pin Description 6, 7, 8, 10, 11, 12, 13 RE6 ~ RE0 OUT 2 TEST IN Not used. Tie LOW. 3 PD IN HIGH: normal operation; LOW: Power down (all outputs are “L”). 4 OE IN HIGH: Output enable (normal operation); LOW: Output disable (all outputs are high impedance). 5 R/F IN Output Clock triggering edge select. High: Rising edge; Low: Falling edge. 9, 23, 37, 48 VCC Power 31 CLKOUT OUT 1, 16, 30, 44 GND Ground Ground pins for TTL outputs and digital circuitry. 53 LVCC Power Power supply pins for LVDS inputs. 58 LGND Ground Ground pins for LVDS inputs. 64 PVCC Power Power supply pin for PLL circuitry. 63 PGND Ground Ground pin for PLL circuitry. CMOS/TTL Data Outputs. Power supply pins for TTL outputs and digital circuitry. Clock out. PD R/F OE Data Outputs (Rxn) CLKOUT 0 0 0 High impedance High impedance 0 0 1 All 0 Fixed Low 0 1 0 High impedance High impedance 0 1 1 All 0 Fixed Low 1 0 0 High impedance High impedance 1 0 1 Data Out Latches output data on falling edge 1 1 0 High impedance High impedance 1 1 1 Data Out Latches output data on rising edge **Rxn x = A, B, C, D, E n = 0, 1, 2, 3, 4, 5, 6 V104 Datasheet 3 1/12/05 Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m PRELIMINARY V104 10 BIT LVDS RECEIVER FOR VIDEO External Components The V104 requires no external components. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the V104. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VCC -0.3 V to +4.0 V CMOS/TTL Input Voltage -0.3 V to VCC+0.3 V CMOS/TTL Output Voltage -0.3 V to VCC+0.3 V LVDS Receiver Input Voltage -0.3 V to VCC+0.3 V Output Current -30 mA to 30 mA Storage Temperature -55 to +125°C Junction Temperature 125°C Soldering Temperature (10 seconds) 260°C Maximum Power Dissipation @ +25°C 1.0 W Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) V104 Datasheet 4 Typ. Max. Units 0 +70 °C +3.0 +3.6 V 1/12/05 Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m PRELIMINARY V104 10 BIT LVDS RECEIVER FOR VIDEO Electrical Characteristics VDD=3.3 V ±10%, Ambient temperature 0 to +70°C Parameter Symbol Conditions Min. Typ. Max. Units CMOS/TTL DC Specifications Input High Voltage VIH 2.00 VCC V Input Low Voltage VIL GND 0.80 V Output High Voltage VOH IOH = -4 mA (data) IOH = -8 mA (clock) Output Low Voltage VOL IOH = -4 mA (data) IOH = -8 mA (clock) 0.4 V Input Current IINC 0V<VIN<VCC ±10 µA 100 mV 2.4 V LVDS Receiver DC Specifications Differential Input High Threshold VTH VOC = 1.2 V Differential Input Low Threshold VTL VOC = 1.2 V Input Current IINL VIN = 2.4 V / 0V VIN = 3.6 V Parameter Symbol -100 Conditions mV Typ. ±20 µA Max. Units Supply Current Receiver Supply Current (Gray Scale Pattern) IRCCG fCLKOUT = 90 MHz CL=8 pF, VCC = 3.3 V 70 mA Receiver Supply Current (Checker Pattern) IRCCW fCLKOUT = 90 MHz CL=8 pF, VCC = 3.3 V 112 mA Receiver Power Down Supply Current IRCCS V104 Datasheet PD = L 5 10 1/12/05 µA Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m PRELIMINARY V104 10 BIT LVDS RECEIVER FOR VIDEO Incremental Pattern (Gray Scale) CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 X = A, B, C, D, E Toggle Pattern (Checker) CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 X = A, B, C, D, E V104 Datasheet 6 1/12/05 Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m PRELIMINARY V104 10 BIT LVDS RECEIVER FOR VIDEO Parameter Symbol Min. Typ. Max. Units CLKOUT Period tRCP 11.1 T 125.0 ns CLK IN High Time tRCH CLK IN Low Time tRCL TTL Data Setup to CLKOUT tRS 4.5 ns TTL Data Hold from CLKOUT tRH 2.5 ns TTL Low to High Transition Time tTLH Switching Characteristics (T-1)/2 ns (T-1)/2 ns 1.0 2.0 ns 1.0 2.0 ns 0.0 +0.25 ns tRCIP 7 tRCIP +0.25 7 ns t 2 RCIP -0.25 7 t 2 RCIP 7 t 2 RCIP +0.25 7 ns tRIP5 t 3 RCIP -0.25 7 t 3 RCIP 7 t 3 RCIP +0.25 7 ns Input Data Position4 tRIP4 t 4 RCIP -0.25 7 t 4 RCIP 7 t 4 RCIP +0.25 7 ns Input Data Position5 tRIP3 t 5 RCIP -0.25 7 t 5 RCIP 7 t 5 RCIP +0.25 7 ns Input Data Position6 tRIP2 t 6 RCIP -0.25 7 t 6 RCIP 7 t 6 RCIP +0.25 7 ns Phase Lock Loop Set tRPLL CLKIN Period tRCIP TTL High to Low Transition Time tTHL Input Data Position0 tRIP1 Input Data Position1 tRIP0 tRCIP -0.25 7 Input Data Position2 tRIP6 Input Data Position3 -0.25 Device-device data output skew 10.0 ms 11.1 125.0 ns 0 1.6 ns Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case V104 Datasheet Symbol Conditions Min. Typ. Max. Units θJA Still air 53 °C/W θJA 1 m/s air flow 40 °C/W θJA 3 m/s air flow 33 °C/W 8 °C/W θJC 7 1/12/05 Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m PRELIMINARY V104 10 BIT LVDS RECEIVER FOR VIDEO AC Timing Diagrams TTL Outputs 80% 80% 20% 20% tTLH tTHL TTL Output CL = 8 pF TTL Output Load TTL Outputs tRCH tRCL R/F = L CLK OUT 2.0 V 2.0 V 2.0 V 0.8 V 0.8 V R/F = H tRCP tRS Rxn tRH 2.0 V 2.0 V 0.8 V 0.8 V x = A, B, C, D, E n = 0, 1, 2, 3, 4, 5, 6 Phase Lock Loop Set Time 3.0 V VCC RCLK+/2.0 V tRPLL PD 2.0 V CLKOUT V104 Datasheet 8 1/12/05 Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m PRELIMINARY V104 10 BIT LVDS RECEIVER FOR VIDEO Power Up Sequence Sequence 1 VCC PVCC LVCC VCC/2 Min 100 µsec VCC/2 PD Recommended PD Pin Circuit VCC 100 kohm PD Pin 0.1 µF Sequence 2 3.0 V VCC PVCC GND LVCC PD V104 Datasheet VCC VCC GND GND 9 1/12/05 Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m PRELIMINARY V104 10 BIT LVDS RECEIVER FOR VIDEO tRIP2 LVDS Inputs tRIP3 tRIP4 tRIP5 tRIP6 tRIP0 tRIP1 Rx6 Rx+/- Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 RCLK+ VDIFF = 0V VDIFF = 0V tRCIP x = A, B, C, D, E LVDS Inputs VDIFF = 0V VDIFF = 0V RCLK+ (Differential RA+/- RA3' RA2' RA1' RA0' RA6 RA5 RA4 RA3 RA2 RA1 RA0 RA6" RB+/- RB3' RB2' RB1' RB0' RB6 RB5 RB4 RB3 RB2 RB1 RB0 RB6" RC+/- RC3' RC2' RC1' RC0' RC6 RC5 RC4 RC3 RC2 RC1 RC0 RC6" RD+/- RD3' RD2' RD1' RD0' RD6 RD5 RD4 RD3 RD2 RD1 RD0 RD6" RE+/- RE3' RE1' RE0' RE6 RE5 RE4 RE3 RE2 RE1 RE0 RE2' Previous Cycle Current Cycle RE6" Next Cycle tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2 V104 Datasheet 10 1/12/05 Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m PRELIMINARY V104 10 BIT LVDS RECEIVER FOR VIDEO Package Outline and Package Dimensions (64-pin TQFP) Package dimensions are kept current with JEDEC Publication No. 95, variation ACD. ALL DIMENSIONS ARE IN MILLIMETERS. SYMBOL MIN/MAX N 64 A -- / 1.20 A1 0.05 / 0.15 A2 0.95 / 1.05 b 0.17 / 0.27 c 0.09 / 0.20 D 12.00 BASIC D1 10.00 BASIC D2 7.50 Ref. E 12.00 BASIC E1 10.00 BASIC E2 7.50 Ref. e 0.50 BASIC L 0.45 / 0.75 θ 0° / 7° ccc -- / 0.08 D3&E3 - Ordering Information Part / Order Number V104YLF V104YLFT Marking V104YLF V104YLF Shipping Packaging Package Temperature Tubes 64-pin TQFP 0 to +70° C Tape and Reel 64-pin TQFP 0 to +70° C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. V104 Datasheet 11 1/12/05 Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m