TI TPS56302PWP

TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
D
D
D
D
D
D
D
D
D
D
PWP PowerPAD PACKAGE
2.8 V – 5.5 V Input Voltage Range
(TOP VIEW)
Programmable Dual Output Controller
Supports Popular DSP, FPGA and
1
28
DROOP
VID0
Microcontroller Core and I/O Voltages
2
27
VID1
OCP
– Switching Regulator Controls I/O Voltage SLOWST
3
26
IOUT
– Low Dropout Controller Regulates Core
4
25
PWRGD
VHYST
Voltage
5
24
VSEN–LDO
VREFB
6
23
VSEN–RR
NGATE–LDO
Thermal
Adjustable Slow-Start for Simultaneous
7
22
Pad
ANAGND
INHIBIT
Powerup of Both Outputs
8
21
IOUTLO
BIAS
Power Good Output Monitors Both Outputs
9
20
VLDODRV
HISENSE
Fast Ripple Regulator Reduces Bulk
10
19
CPC1
LOSENSE/LOHIB
Capacitance for Lower System Costs
11
18
VCC
HIGHDR
12
17
BOOT
CPC2
±1.5% Reference Voltage Tolerance
13
16
BOOTLO
VDRV
Efficiencies Greater Than 90%
14
15
LDWDR
DRVGND
Overvoltage, Undervoltage, and Adjustable
Overcurrent Protection
AVAILABLE VID CODE RANGES
Drives Logic Level N-Channel MOSFETs
Through Entire Input Voltage Range
TPS56300
TPS56302
OUTPUTS
1.3 V TO 3.3 V
1.3 V TO 2.5 V
VOUT–LDO
Evaluation Module TPS56302EVM–163
1.3 V TO 2.5 V
1.3 V TO 3.3 V
VOUT–Switcher
Available
NOTE: See Table 1 for actual VID codes.
description
The high-performance TPS56302 synchronous-buck regulator provides two supply voltages to power the core
and I/O of digital signal processors. The TPS56302 is identical to the TPS56300 except that the reference
voltages of the LDO and switching regulator have been reversed. The switching regulator, using hysteretic
control with droop compensation, supports high current and efficiency for the I/O and other peripheral
components. The LDO controller, suitable for powering the core voltage, drives an external N-channel power
MOSFET and functions as an LDO regulator and as a power distribution switch.
typical design
VI
U1
TPS56302PWP
+
VCC
PWRGD
CPC1
NGATE–LDO
CPC2
VREFB
VSEN–LDO
VHYST
INHIBIT
DROOP
IOUTLO
OCP
HISENSE
IOUT
HIGHDR
SLOWST
VSEN–RR
VID0
VID1
LOSENSE/LOHIB
BOOT
BIAS
BOOTLO
VLDODRV
LOWDR
VDRV
ANAGND
DRVGND
PwrPad
+
VCORE
+
See Table 1
See Table 1
+
(2.8 V – 5.5 V)
VI/O
DSP
Data
+
Data Bus
PERIPHERAL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
description (continued)
To promote better system reliability during power up, voltage sequencing and protection are controlled such that
the core and I/O power up together with the same slow-start voltage. At power down, the LDO and ripple
regulator are discharged towards ground for added protection. The TPS56302 also includes inhibit, slow-start,
and under-voltage lockout features to aide in controlling power sequencing. A tri-level voltage identification
definition (VID) sets both regulated voltages to any of 9 preset voltage pairs from 1.3 V to 3.3 V. Other voltages
are possible by implementing an external voltage divider. Strong MOSFET drivers, with a typical peak current
rating of 2-A sink and source are included on chip, which allows paralleling MOSFETs to be driven and allowing
higher current to be controlled. The high-side driver features a floating bootstrap driver with an internal bootstrap
synchronous rectifier. Many protection features are incorporated within the device to ensure better system
integrity. An open-drain output power good status circuit monitors both output voltages, and is pulled low if either
output falls below the threshold. An over current shutdown circuit protects the high-side power MOSFET against
short-to-ground faults, while over voltage protection turns off the output drivers and LDO controller if either
output exceeds its threshold. Under voltage protection turns off the high-side and low-side MOSFET drivers and
the LDO controller if either output is 25% below VREF. Lossless current-sensing is implemented by detecting
the drain-source voltage drop across the high-side power MOSFET while it is conducting. The TPS56302 is fully
compliant with TI DSP power requirements.
AVAILABLE OPTIONS
PACKAGES
TSSOP†
(PWP)
TJ
EVALUATION MODULE
–40°C to 125°C
TPS56302PWP
TPS56302EVM–163 (SLVP163)
† The PWP package is also available taped and reel. To order, add an R to the end of
the part number (e.g., TPS56302PWPR).
Table 1. Voltage Identification Code¶#
VID TERMINALS‡
56302
56300
VID1
VID0
VREF–LDO#
(VDC)
VREF–RR#
(VDC)
VREF–RR#
(VDC)
VREF–LDO#
(VDC)
0
0
1.30
1.50
1.30
1.50
0
1
1.50
1.80
1.50
1.80
0
2
1.30
1.80
1.30
1.80
1
0
1.80
3.30
1.80
3.30
1
1
1.30
1.30
1.30
1.30
1
2
2.50
3.30
2.50
3.30
2
0
1.30
2.50
1.30
2.50
2
1
1.50
3.30
1.50
3.30
2
2
1.80
2.50
1.80
2.50
‡ 0 = ground (GND), 1 = floating(VBIAS/2), 2 = (VBIAS)
§ RR = Ripple Regulator, LDO = Low Drop-Out Regulator
¶ VBIAS/2 is internal, leave the VID pin floating. Adding an external 0.1-µF capacitor to ANAGND may be used
to avoid erroneous level.
# External resistors may be used as a voltage divider (from VOUT to VSEN–xx to ground) to program output
voltages to other values.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
functional block diagram
LOSENSE/
LOHIB
PWRGD
25
Bias
IOUTLO
19
HISENSE
IOUT
20
26
21
+
8
–
>0.93xVSEN–RR
Reg.
VDRV
VLDODRV
>0.93xVSEN–LDO
9
SHUTDOWN
Delay
INHIBIT
VCC
11
22
INHIBIT
27
OCP
24
VSEN–LDO
23
NGATE–LDO
17
BOOT
18
HIGHDR
16
BOOTLO
15
LOWDR
VDRV UVLO
V CC UVLO
HIGHDR
RR_OVP
Fault
Latch
CPC1 10
LDO_OVP
Q
S
RR_UVP *
R
LDO_UVP *
BOOT
CPC2 12
SHUTDOWN
+
–
VDRV
125 mV
5V
VDRV 13
SHUTDOWN
VLDODRV
E/A
VID0
1
–
SLOWST
VREF_LDO
+
VID
VID1
(see Table 1)
2
Vbias
Ivrefb/5
SLOWST
SHUTDOWN
Hysteresis
Comparator
SLOWST
VREF_RR
3
+
Adaptive
Deadtime
–
SHUTDOWN
Hysteresis
Setting
VDRV
SHUTDOWN
7
ANAGND
RR–Ripple Regulator
5
VREFB
4
VHYST
28
DROOP
Synchronous FET
POST OFFICE BOX 655303
6
14
VSEN–RR
DRVGND
* UVP is disabled during slowstart
• DALLAS, TEXAS 75265
3
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
VID0
1
VID1
2
SLOWST
3
Slow-start (soft start). A capacitor from pin 3 to GND sets the slow-start time for VOUT-RR and VOUT-LDO. Both supplies
will ramp-up together while tracking the slow-start voltage.
VHYST
4
Hysteresis set pin. The hysteresis equals 2 × (VREFB – VHYST).
VREFB
5
Buffered ripple regulator reference voltage from VID network.
VSEN-RR
6
Ripple regulator voltage sense input. This pin is connected to the ripple regulator output. It is used to sense the ripple
regulator voltage for regulation, OVP, UVP, and power good functions.. It is recommended that an RC low pass filter be
connected at this pin to filter high frequency noise.
ANAGND
7
Analog ground
BIAS
8
Analog BIAS pin. Recommended that a 1-µF capacitor be connected to ANAGND.
VLDODRV
9
Output of charge pump generated through bootstrap diode. Approximately equal to VDRV + VIN – 300 mV. Used as
supply for LDO driver and bias regulator. Recommended that a 1-µF capacitor be connected to DRVGND.
CPC1
10
Connect one end of charge pump capacitor. Recommended that a 1-µF capacitor be connected from CPC1 to CPC2.
VCC
11
3.3 V or 5 V supply (2.8 V – 5.5 V). It is recommended that a low ESR capacitor be connected directly from VCC to
DRVGND (bulk capacitors supplied at power stage input).
CPC2
12
Other end of charge pump capacitor from CPC1.
VDRV
13
Regulated output of internal charge pump. Supplies DRIVE charge for the low-side MOSFET driver (5 V).
Recommended that a 10-µF capacitor be connected to DRVGND.
DRVGND
14
Drive ground. Ground for FET drivers. Connect to source of low-side FET.
LOWDR
15
Low drive. Output drive to synchronous rectifier low-side FET.
BOOTLO
16
Bootstrap low. This pin connects to the junction of the high-side and low-side FETs.
BOOT
17
Bootstrap pin. Connect a 1-µF low ESR capacitor to BOOTLO to generate floating drive for the high-side FET driver.
HIGHDR
18
High drive. Output drive to high-side power switching FETs
LOSENSE/
LOHIB
19
Low sense/low-side inhibit. This pin is connected to the junction of the high and low-side FETs and is used in current
sensing and the anti-cross-conduction to eliminate shoot-through current.
HISENSE
20
High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs.
IOUTLO
21
Current sense low output. Voltage on this pin is the voltage on the LOSENSE pin when the high-side FETs are on.
INHIBIT
22
This pin inhibits the drive signals to the MOSFET drivers. The IC is in a low-current state if INHIBIT is grounded. It is
recommended that an external pullup resistor be connected to 5 V.
NGATE-LDO
23
Drives external N-channel power MOSFET to regulate LDO voltage to VREF-LDO.
VSEN–LDO
24
LDO voltage sense. This pin is connected to the LDO output. It is used to sense the LDO voltage for regulation, OVP,
UVP, and power good functions.
PWRGD
25
Power good. Power good signal goes high when output voltage is above 93% of VREF for both ripple regulator and
LDO. This is an open-drain output.
IOUT
26
Current signal output. Output voltage on this pin is proportional to the load current as measured across the high-side
FETs on-resistance. The voltage on this pin equals 2 × RON × IOUT, where RON is the equivalent on-resistance of the
high-side FETs
OCP
27
Over current protection. Current limit trip point for ripple regulator is set with a resistor divider between the IOUT pin and
ANAGND. The trip point is typically 125 mV.
DROOP
28
Droop voltage. Voltage input used to set the amount of output voltage droop as a function of load current. The amount of
droop compensation is set with a resistor divider between the IOUT pin and ANAGND.
4
Voltage Identification input 0. The VID pins are tri-level programming pins that set the output voltages for both
converters. The code pattern for setting the output voltage is located in table 1. The VID pins are internally pulled to
VBIAS/2, allowing floating voltage set to logic 1 (see Table 1).
Voltage Identification input 1 (see VID0 pin description and Table 1).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Input voltage range: VDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
BOOT to DRVGND (High-side Driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
BOOT to HIGHDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
BOOTLO to DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 15 V
DRV to DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
BIAS to ANAGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
DROOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
VID0, VID1 (tri-level terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VBIAS + 0.3 V
PWRGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
LOSENSE, LOHIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 14 V
IOUTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V
HISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
VSEN–LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
VSEN–RR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Voltage difference between ANAGND and DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±300 mV
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.
DISSIPATION RATING TABLE
DERATING FACTOR‡
PWP
PowerPAD mounted
TA < 25°C
3.58 W
0.0358 W/°C
TA = 70°C
1.96 W
PowerPAD unmounted
1.78 W
0.0178 W/°C
0.98 W
‡ Test Board Conditions:
1.. Thickness: 0.062”
2. 3”× 3”
3. 2 oz. Copper traces located on the top of the board (0.071 mm thick )
4. Copper areas located on the top and bottom of the PCB for soldering
5. Power and ground planes, 1 oz. Copper (0.036 mm thick)
6. Thermal vias, 0.33 mm diameter, 1.5 mm pitch
7. Thermal isolation of power plane
TA = 85°C
1.43 W
0.71 W
For more information, refer to TI technical brief SLMA002.
JUNCTION-CASE THERMAL RESISTANCE TABLE
Junction-case thermal resistance
POST OFFICE BOX 655303
0.72 °C/W
• DALLAS, TEXAS 75265
5
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)
input
PARAMETER
VCC
ICC
TEST CONDITIONS
MIN
Supply voltage range
TYP
MAX
2.8
Quiescent current
INHIBIT = 0 V,
5.5
VCC = 5 V
15
UNITS
V
mA
NOTE 2: Ensured by design, not production tested.
reference/voltage identification
PARAMETER
VID0–VID1
TEST CONDITIONS
High-level input voltage (2)
VID0–VID1
Mid-level floating voltage (1)
VID0–VID1
Low-level input voltage (0)
MIN
TYP
MAX
UNITS
VBIAS – 0.3 V
V
Input pull-to-mid resistance
BIAS
2
V
*1
V
36.5
)1
BIAS
2
0.3
V
95
kΩ
73
V
cumulative reference
PARAMETER
Cumulative accuracy ripple regulator
Cumulative accuracy
y LDO
TEST CONDITIONS
VREF = 1.3 V,
TJ = 25°C
VREF = 1.3 V,
TJ = –40°C,
VREF = full range,
Droop = 0,
Hysteresis window = 30 mV,
VREF = 1.3 V,
Closed Loop,
TJ = 25°C,
IO = 0.1 A,
Pass device = IRFZ24N,
See Note 2
MIN
TYP
MAX
–1.3%
0.25%
1.3%
Hysteresis window = 30 mV,
See Note 2
–0.2%
Hysteresis window = 30 mV,
See Note 2
VREF = full range,
IO = 0.1 A,
Pass device = IRFZ24N,
NOTE 2. Ensured by design, not production tested.
UNITS
Closed Loop,
See Note 2
–1.5%
1.5%
–2%
2%
–2.5%
2.5%
buffered reference
PARAMETER
VREFB output voltage
CONDITIONS
IREFB=50 µA,
Accuracy from VREF nominal
IREFB=50 µA,
TJ = –40°C,
Accuracy from VREF nominal
See Note 2
MIN
TYP
MAX
VREF
–1.5%
VREF
VREF
+1.5%
VREFB load regulation
10 µA < IREFB < 500 µA
NOTE 2. Ensured by design, not production tested.
UNITS
V
VREF–0.6%
2
mV
hysteretic comparator(ripreg)
PARAMETER
TEST CONDITIONS
MIN
Input bias current
See Note 2
Hysteresis accuracy
VVREFB – VVHYST = 15 mV,
Hysteresis window = 30 mV
–3.5
Maximum hysteresis setting
VVREFB – VVHYST = 30 mV,
See Note 2
60
Propagation delay time from VSENSE to HIGHDR or
LOWDR (excluding deadtime)
10 mV overdrive,
See Note 2
Prefilter pole frequency
NOTE 2. Ensured by design, not production tested.
6
1.3 V <= VREF <= 3.3 V,
See Note 2
POST OFFICE BOX 655303
TYP
UNITS
500
nA
3.5
mV
mV
150
5
• DALLAS, TEXAS 75265
MAX
250
ns
MHz
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued)
overvoltage protection
PARAMETER
TEST CONDITIONS
OVP ripple regulator trip point (RR)
Upper threshold
Hysteresis (RR)
Upper threshold – lower threshold,
(see Note 2)
Comparator propagation delay time (RR)
Deglitch time (includes comparator propagation delay time) (RR)
Voverdrive = 30 mV,
Voverdrive = 30 mV,
OVP LDO trip point (LDO)
Upper threshold
Hysteresis (LDO)
Upper threshold – lower threshold,
(see Note 2)
Comparator propagation delay time (LDO)
Voverdrive = 50 mV,
See Note 2
Voverdrive = 50 mV,
See Note 2
Deglitch time (includes comparator propagation delay time)
(LDO)
NOTE 2. Ensured by design, not production tested.
MIN
TYP
MAX
UNITS
112
115
120
%VREF
See Note 2
See Note 2
10
mV
1
µs
2.25
112
11
115
120
µs
% VREF
10
mV
1
µs
2.25
11
µs
MAX
UNITS
undervoltage protection
PARAMETER
CONDITIONS
UVP ripple regulator trip point (RR)
Lower threshold
Hysteresis (RR)
Upper threshold – lower threshold,
(see Note 2)
Comparator propagation delay time (RR)
Voverdrive = 50 mV,
See Note 2
Deglitch time (includes comparator
propagation delay time) (RR)
Voverdrive = 50 mV,
See Note 2
UVP LDO trip point (LDO)
Lower threshold
Hysteresis (LDO)
Upper threshold – lower threshold,
(see Note 2)
MIN
TYP
70
75
Voverdrive = 50 mV, See Note 2
Deglitch time (includes comparator
Voverdrive = 50 mV, See Note 2
propagation delay time) (LDO)
NOTE 2. Ensured by design, not production tested.
10
mV
1
µs
0.1
70
Comparator propagation delay time (LDO)
80 %VREF
1
75
ms
80 %VREF
10
mV
1
µs
0.1
1
ms
inhibit comparator
PARAMETER
Start threshold
CONDITIONS
TJ = –40°C,
MIN
See Note 2
Stop threshold
NOTE 2. Ensured by design, not production tested.
TYP
MAX
2.1
2.35
2.1
1.79
UNITS
V
V
VDRV UVLO
PARAMETER
CONDITIONS
MIN
TYP
0.35
Start threshold
See Note 2
Hysteresis
See Note 2
0.3
Stop threshold
See Note 2
NOTE 2. Ensured by design, not production tested.
4.4
POST OFFICE BOX 655303
MAX
4.9
• DALLAS, TEXAS 75265
UNITS
V
V
V
7
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued)
slow-start
PARAMETER
CONDITIONS
Charge current
V(S/S) = 0.5 V,
Resistance from VREFB pin to ANAGND = 20 kΩ
VREFB = 1.3 V,
Ichg = (IVREFB/5)
Discharge current
V(S/S) = 1.3 V
MIN
TYP
MAX
UNITS
10.4
13
15.6
µA
3
mA
Comparator input offset voltage
Comparator input bias current
10
See Note 2
10
Hysteresis accuracy
nA
7.5
mV
560
1000
ns
TYP
MAX
UNITS
2.72
2.80
–7.5
Comparator propagation delay
Overdrive = 10 mV,
NOTE 2. Ensured by design, not production tested.
See Note 2
mV
100
VCC UVLO
PARAMETER
Start threshold
CONDITIONS
MIN
(see Note 2)
TJ = –40°C,
Stop threshold
(see Note 2)
NOTE 2. Ensured by design, not production tested.
See Note 2
2.71
2.48
V
V
power good
PARAMETER
CONDITIONS
MIN
TYP
MAX
93
95
UNITS
Undervoltage
g trip point ripple regulator
g
(VSENSE–RR)
VIN and VDRV above UVLO thresholds
TJ = –40°C,
See Note 2
90
Undervoltage
g trip point LDO
(VSENSE–LDO)
VIN and VDRV above UVLO thresholds
TJ = –40°C,
See Note 2
90
Output saturation voltage
IO=5 mA
VPGD = 4.5 V
0.5
Hysteresis
VREF = 1.3 V, 1.5 V, or 1.8 V
VREF = 2.5 V, or 3.3 V
50
75
mV
100
125
mV
Comparator high–low transition time
(propagation delay only)
See Note 2
Leakage current
93
93
95
93
0.75
%V
%
VREF
V
µA
1
µs
1
Comparator low–high transition time
See Note 2
(propagation delay + deglitch)
NOTE 2. Ensured by design, not production tested.
%V
%
VREF
0.2
1
2
MIN
TYP
MAX
ms
droop compensation
PARAMETER
Initial accuracy
CONDITIONS
VDROOP = 50 mV
46
54
UNITS
mV
overcurrent protection (RR)
PARAMETER
CONDITIONS
OCP trip point
MIN
TYP
MAX
UNITS
118
130
142
mV
300
nA
Input bias current
Comparator propagation delay time
Voverdrive = 30 mV,
Deglitch time (includes comparator
Voverdrive = 30 mV,
propagation delay time)
NOTE 2. Ensured by design, not production tested.
8
POST OFFICE BOX 655303
See Note 2
See Note 2
• DALLAS, TEXAS 75265
µs
1
2.25
11
µs
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued)
high-side VDS sensing
PARAMETER
CONDITIONS
MIN
Gain
Initial accuracy
Common-mode rejection ratio
Sink current (IOUTLO)
TYP
MAX
2
VHISENSE = 3.3 V,
VIOUTLO = 3.2 V,
Differential input to Vds sensing amp = 100 mV
VHISENSE=2.8 V to 5.5 V,
VHISENSE– VIOUTLO=100 mV
2.8 V < VIOUTLO < 5.5 V
194
69
UNITS
V/V
208
75
mV
dB
250
nA
VIOUT = 0.5 V,
VIOUTLO=2.8 V
VIOUT = 0.05 V,
VIOUTLO=3.3 V
VHISENSE=5.5 V,
VHISENSE=3.3 V,
500
µA
VHISENSE=3.35 V,
50
µA
RIOUT = 10 kΩ
0
1.75
Output voltage swing
VHISENSE=4.5 V,
VHISENSE=3 V,
RIOUT = 10 kΩ
0
1.5
0
0.75
LOSENSE high-level input voltage
VHISENSE=2.8 V,
VHISENSE=2.8 V,
See Note 2
VHISENSE=4.5 V,
VHISENSE=4.5 V,
See Note 2
VHISENSE=5.5 V,
VHISENSE=5.5 V,
See Note 2
VHISENSE = 6 V,
VHISENSE = 4.5 V,
See Note 2
70
90
See Note 2
80
100
See Note 2
90
120
See Note 2
120
180
Source current (IOUT)
Sink current (IOUT)
LOSENSE low-level input voltage
LOSENSE high-level input voltage
LOSENSE low-level input voltage
LOSENSE high-level input voltage
LOSENSE low-level input voltage
Sample/hold resistance
Response time ((measured from 90% of
VIOUTLO to 90% of VIOUT)
Short circuit protection rising edge delay
RIOUT = 10 kΩ
1.77
See Note 2
2.85
3.80
4
VHISENSE = 2.8 V,
VIOUTLO pulsed from 2.8 V to 2.7 V,
100 ns rise and fall times,
See Note 2
3.5
VHISENSE = 4.5 V,
VIOUTLO pulsed from 4.5 V to 4.4 V,
100 ns rise and fall times,
See Note 2
3
VHISENSE = 5.5 V,
VIOUTLO pulsed from 5.5 V to 5.9 V,
100 ns rise and fall times,
See Note 2
3
See Note 2
2.8 V < VHISENSE < 5.5 V,
VLOSENSE = VHISENSE,
NOTE 2. Ensured by design, not production tested.
Sample/hold switch turnon/turnoff delay
POST OFFICE BOX 655303
See Note 2
• DALLAS, TEXAS 75265
V
V
3.2
VHISENSE = 2.55 V,
VIOUTLO pulsed from 2.55 V to 2.45 V,
100 ns rise and fall times,
See Note 2
LOSENSE grounded,
V
V
2.4
See Note 2
VHISENSE = 3.6 V,
VHISENSE = 2.8 V,
V
1.49
See Note 2
V
V
Ω
µs
300
500
ns
30
100
ns
9
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued)
thermal shutdown
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
See Note 2
145
°C
Hysteresis
See Note 2
NOTE 2. Ensured by design, not production tested.
10
°C
Over temperature trip point
synch charge pump regulator
PARAMETER
Internal oscillator frequency
CONDITIONS
2.8 V < VIN < 5.5 V,
VDRV=5 V ,
Internal oscillator turnon threshold
VCC above UVLO threshold,
Internal oscillator turnon hysteresis
VCC above UVLO threshold,
NOTE 2. Ensured by design, not production tested.
MIN
TYP
MAX
UNITS
IDRV = 50 mA,
See Note 2
200
300
400
kHz
See Note 2
5.05
5.2
20
mV
See Note 2
V
hysteretic comparator (charge pump)
PARAMETER
CONDITIONS
Threshold
VIN above UVLO threshold,
Hysteresis
VIN above UVLO threshold,
NOTE 2. Ensured by design, not production tested.
See Note 2
MIN
TYP
5.05
5.2
See Note 2
MAX
UNITS
V
20
mV
deadtime circuit
PARAMETER
LOSENSE/LOHIB high level input voltage
LOSENSE/LOHIB low level input voltage
LOWDR high level input voltage
LOWDR low level input voltage
CONDITIONS
VHISENSE=2.55 V – 5.5 V,
VHISENSE=2.55 V – 5.5 V,
See Note 2
VHISENSE=2.55 V–5.5 V,
VHISENSE=2.55 V–5.5 V,
See Note 2
CLOWDR = 9 nF,
VDRV=5 V
NOTE 2. Ensured by design, not production tested.
Driver nonoverlap time
10
POST OFFICE BOX 655303
MIN
See Note 2
• DALLAS, TEXAS 75265
MAX
3
40
UNITS
V
1.33
See Note 2
10% threshold on LOWDR,
TYP
2.4
V
V
1.7
V
170
ns
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued)
output drivers (see Note 5)
PARAMETER
Peak output current
MIN
TYP
Duty cycle < 2%,
tpw < 100 us,
VBOOT – VBOOTLO = 4.5 V,
VHIGHDR = 4 V (sink),
See Note 2 and Figure 15
CONDITIONS
0.7
2
Duty cycle < 2%,
tpw < 100 us,
VBOOT – VBOOTLO = 4.5 V,
VHIGHDR = 0.5 V (source), See Note 2 and Figure 15
1.2
2
tpw < 100 µs,
VLOWDR = 4 V (sink),
1.3
2
Duty cycle < 2%,
VDRV = 4.5 V,
See Note 2 and Figure 15
tpw < 100 us,
VLOWDR = 0.5 V (source),
1.4
2
HIGHDR rise/fall time
LOWDR rise/fall time
5
VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 4 V,
See Note 2
VDRV = 4.5 V,
VDRV = 4.5 V,
45
VLOWDR = 0.5 V, See Note 2
VLOWDR = 4 V,
See Note 2
CL = 3.3 nF,
VBOOT= 4.5 V,
VBOOTLO=grounded,
CL = 3.3 nF,
VDRV= 4.5 V,
INHIBIT grounded,
BOOTLO grounded
UNITS
A
Duty cycle < 2%,
VDRV = 4.5 V,
See Note 2 and Figure 15
VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 0.5 V,
See Note 2
Output resistance
MAX
Ω
9
45
See Note 2
See Note 2
VIN < UVLO, VBOOT=6 V,
60
ns
40
ns
10
µA
INHIBIT connected to +5 V, VIN > UVLO
f(swx) = 200 kHz,
VBOOT = 5.5 V,
2
mA
BOOTLO = 0,
CHIGHDR = 50 pF,
See Note 2
NOTES: 2. Ensured by design, not production tested.
5. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
High-side driver quiescent current
LDO N-channel output driver
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VLDODRV = 7.5 V,
VIOSENSE = 0.9 × VLDOREF,
VLDODRV = 7.5 V,
VIOSENSE = 1.1 × VLDOREF,
VN–DRV = 3 V (source),
See Note 2
100
µA
VN–DRV=0 V (sink),
See Note 2
1.5
mA
Open loop voltage gain
( VNGATE–LDO / VSENSE–LDO )
7.5 V ≥ VNGATE–LDO ≥ 0.5 V,
See Note 2
VIN = 5.5 V,
3000
(70)
V/V
(dB)
Power supply ripple rejection
f = 1 kHz,
5.5 V ≥ VIN ≥ 2.55 V,
See Note 2
CO=10 µF,
TJ=125 °C,
Peak output current
60
dB
NOTE 2. Ensured by design, not production tested.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted) (continued)
VSENSE–RR and VSENSE–LDO discharge
PARAMETER
CONDITIONS
VSENSE–RR discharge FET current saturation
VSENSE–RR discharge series resistance (limits current)
VSENSE–RR = 1.5 V,
INHIBIT = 0 V,
VSENSE–RR discharge FET propagation delay time
VSENSE–LDO discharge FET current saturation
See Note 2
VSENSE–LDO discharge series resistance (limits current)
VSENSE–LDO discharge FET propagation delay time
VSENSE–LDO = 3.3 V,
INHIBIT = 0 V,
See Note 2
MIN
TYP
See Note 2
5
VIN = 5.5 V
1
MAX
mA
kΩ
100
See Note 2
5
VIN = 5.5 V,
1
UNITS
ns
mA
kΩ
100
ns
NOTE 2. Ensured by design, not production tested.
detailed description
reference/voltage identification
The reference/voltage identification definition (VID) section consists of a temperature compensated bandgap
reference and a 2-pin voltage selection network. Both ripple regulator and LDO reference voltages are
programmed with each VID setting. The 2 VID pins are inputs to the VID selection network and are tri-level inputs
that may be set to GND, floating (VBIAS/2), or VBIAS. The VID codes allow the controller to power both current
and future DSP products. The output voltages may also be programmed by external resistor voltage dividers
for any values not included in the VID code settings. Refer to Table 1 for the VID code settings. The output
voltages of the VID network, VREF–RR, is within 1.5% and VREF–LDO is within 2.5% of the nominal setting over
the VID range of 1.3 V to 3.3 V. The reference tolerance conditions include a junction temperature range of
–40_C to +125_C and a VCC supply voltage range of 2.8 V to 5.5 V. The VREF–RR output of the reference/VID
network is indirectly brought out through a buffer to the VREFB pin. The voltage on this pin will be within 1.5%
of VREF–RR. It is not recommended to drive loads with VREFB, other than setting the hysteresis of the hysteretic
comparator, because the current drawn from VREFB sets the charging current for the slow-start capacitor. Refer
to the Slow-start section of this document for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered around VREF. The two external resistors form a resistor divider from
VREFB to ANAGND, and the divided down voltage connects to the VHYST pin. The hysteresis of the
comparator will be equal to twice the voltage difference that is across the VREFB and VHYST pins. The
propagation delay from the comparator inputs to the driver outputs is 250 ns maximum. The maximum
hysteresis setting is 60 mV.
low-side driver
The low-side driver is designed to drive low rDS(on) logic-level N-channel MOSFETs. The current rating of the
driver is 2-A typical, source and sink. The bias to the low-side driver is internally connected to the regulated
synchronous charge pump output.
high-side driver
The high-side driver is designed to drive low rDS(on) logic-level N-channel MOSFETs. The current rating of the
driver is 2 amps typical, source and sink. The high-side driver can be configured either as a floating bootstrap
driver or as a ground-reference driver. When configured as a floating driver, the bias voltage to the driver is
developed from the charge pump VDRV voltage. The internal synchronous bootstrap rectifier, connected
between the VDRV and BOOT pins, is a synchronously-rectified MOSFET for improved drive efficiency. The
maximum voltage that can be applied between the BOOT pin and ground is 14 V.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
detailed description (continued)
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon time of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate drive voltage to the low-side FET is below 1 V, and the low-side driver is not allowed
to turn on until the voltage at the junction of the 2 FETs (Vphase) is below 2 V.
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FET while the
high-side FET is on. The sampling network consists of an internal 60-Ω switch and an external hold capacitor.
Internal logic controls the turnon and turnoff of the sample/hold switch such that the switch does not turn on until
the Vphase voltage transitions high, and the switch turns off when the input to the high-side driver goes low.
Thus sampling will occur only when the high-side FET is conducting current. The voltage on the IOUT pin equals
2 times the sensed high-side voltage.
droop compensation
The droop compensation network reduces the load transient overshoot / undershoot on VOUT, relative to VREF
(see the application information section of this document for more details). VOUT is programmed to a voltage
greater than VREF by an external resistor divider from VOUT to the VSENSE pin to reduce the undershoot on
VOUT during a low to high load transient. The overshoot during a high to low load transient is reduced by
subtracting the voltage that is on the DROOP pin from VREF. The voltage on the IOUT pin is divided down with
an external resistor divider, and connected to the DROOP pin.
inhibit
INHIBIT is a TTL-compatible comparator pin that is used to enable the controller. When INHIBIT is lower than
the threshold, the output drivers are low and the slow-start capacitor is discharged. When INHIBIT goes high
(above 2.1 V), the short across the slow-start capacitor is released and normal converter operation begins.
When another system logic supply is connected to the INHIBIT pin, this pin controls power sequencing by
locking out controller operation until the system logic supply exceeds the input threshold voltage of the inhibit
circuit; thus the +3.3-V supply and another system logic supply (either +5 V or +12 V) must be above UVLO
thresholds before the controller is allowed to start up. Toggling the INHIBIT pin from low to high or recycling VCC
clears the fault latch.
slow-start
The slow-start circuit controls the rate at which both VOUT–RR and VOUT–LDO power up (at the same time). A
capacitor is connected between the SLOWST and ANAGND pins and is charged by an internal current source.
The value of the current source is proportional to the reference voltage, so that the charging rate of CSLOWST
is proportional to the ripple regulator reference voltage. The slow-start charging current is determined by the
following equation:
I
I
VREFB
+
SLOWSTART
5
Where IVREFB is the current flowing out of the VREFB pin. It is recommended that no additional loads be
connected to VREFB, other than the resistor divider for setting the hysteresis voltage. Thus these resistor values
will determine the slow-start charging current. The maximum current that can be sourced by the VREFB circuit
is 500 µA. The equation for the slow-start time is:
T
SLOWSTART
+5
C
SLOWSTART
R
VREFB
Where RVREFB is the total external resistance from VREFB to ANAGND.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
detailed description (continued)
VCC and VDRV undervoltage lockout
The VCC undervoltage lockout circuit disables the controller while the VCC supply is below the 2.8-V start
threshold. The VDRV undervoltage lockout circuit disables the controller while the VDRV supply is below the
4.9 V start threshold during powerup. While the controller is disabled, the output drivers will be low, the LDO
drive is off, and the slow-start capacitor will be shorted. When VCC and VDRV exceed the start threshold, the
short across the slow-start capacitor is released and normal converter operation begins. Recycling VCC or
toggling the INHIBIT pin from low to high clears the fault latch.
power good
The power good circuit monitors for an undervoltage condition on VOUT–RR and VOUT–LDO. The power good
(PWRGD) pin is pulled low if either VOUT–RR is 7% below VREF–RR, or VOUT–LDO is 7% below VREF–LDO.
PWRGD is an open drain output. The PWRGD pin is also pulled down, if either VCC or VDRV are below their
UVLO thresholds.
overvoltage protection
The overvoltage protection circuit monitors VOUT–RR and VOUT–LDO for an overvoltage condition. If VOUT–RR
or VOUT–LDO are 15% above their reference voltage, then a fault latch is set and both output drivers and LDO
are turned off. The latch remains set until the VCC or inhibit voltages go below their undervoltage lockout turnoff
values. A 1-µs to 5 µs deglitch timer is included for noise immunity.
overcurrent protection
The overcurrent protection circuit monitors the current through the high-side FET. The overcurrent threshold
is adjustable with an external resistor divider between IOUT and ANAGND pins, with the divider voltage
connected to the OCP pin. If the voltage on the OCP pin exceeds 125 mV, a fault latch is then set and the output
drivers are turned off. The latch remains set until the VCC or inhibit voltages go below their undervoltage lockout
values. A 1-µs to 5-µs deglitch timer is included for noise immunity. The OCP circuit is also designed to protect
the high-side power FET against a short-to-ground fault on the terminal common to both power FETs.
undervoltage protection
The undervoltage protection circuit monitors VOUT–RR and VOUT–LDO for an undervoltage condition. If VOUT–RR
or VOUT–LDO is 15% below their reference voltage, then a fault latch is set and both output drivers and LDO are
turned off. The latch remains set until the VCC or inhibit voltages go below their undervoltage lockout values.
A 100-µs to 1-ms deglitch timer is included for noise immunity.
synchronous charge pump
The regulated synchronous charge pump provides drive voltage to the low-side driver at VDRV (5 V), and to
the high-side driver configured as a floating driver. The minimum drive voltage is 4.5 V, (typical is 5 V). The
minimum short-circuit current is 80 mA. The bootstrap capacitor is used to provide voltage for the high-side FET,
the power for VLDODRV, and the bias regulator. Instead of diodes, synchronous rectified MOSFETs are used
to reduce voltage drop losses and allow a lower input voltage threshold. The charge pump oscillator operates
at 300 kHz until the UVLO VDRV is set; after which it is synchronized to the converter switching frequency and
is turned on and off to regulate VDRV at 5 V.
The charge pump is designed to operate at a switching frequency of 200 kHz to 400 kHz. Operation at low
frequency may require larger capacitors on the CPCx and VDRV pins. Higher frequencies (> 400 kHz) may not
be possible.
power sequence
The VOUT–LDO voltage is powered up with respect to the same slow-start reference voltage as the VOUT–RR
Also, at power down, the VOUT–RR and VOUT–LDO are discharged to ground through P-channel MOSFETs in
series with 1-kΩ resistors.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
VCC UVLO HYSTERESIS
vs
JUNCTION TEMPERATURE
13
180
VCC = 3.3 V
INHIBIT = 0 V
V CCUVLO Hysteresis – mV
Quiescent Current – mA
175
12
11
170
165
160
155
10
150
0
25
50
75
100
TJ – Junction Temperature – °C
125
0
25
50
75
100
TJ – Junction Temperature – °C
Figure 1
Figure 2
VCC UVLO START THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
SLOW-START CHARGE CURRENT
vs
JUNCTION TEMPERATURE
2.750
15
Slowstart Charge Current – µ A
V CCUVLO Start Threshold Voltage – V
125
2.725
2.700
2.675
14
13
12
11
10
2.65
0
25
50
75
100
TJ – Junction Temperature – °C
125
0
25
50
75
100
125
TJ – Junction Temperature – °C
Figure 3
Figure 4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
TYPICAL CHARACTERISTICS
SLOW-START TIME
vs
SUPPLY CURRENT (VREFB)
SLOW-START TIME†
vs
SLOW-START CAPACITANCE
1000
100
VCC = 3.3 V
V(VREFB) = 1.3 V
I(VREFB) = 65 µA
TJ = 25°C
Slowstart Time – ms
Slowstart Time – ms
VCC = 3.3 V
V(VREFB) = 1.3 V
CS = 0.1 µF
TJ = 27°C
100
10
1
1
10
100
10
1
0.1
0.0001
1000
0.0010
ICC – Supply Current (VREFB) – µA
Figure 5
DRIVER
DRIVER
RISE TIME
vs
GATE CAPACITANCE
FALL TIME
vs
GATE CAPACITANCE
TJ = 27°C
100
t f – Fall Time – ns
t r – Rise Time – ns
1
1000
TJ = 27°C
High Side
Low Side
10
1
10
100
100
High Side
Low Side
10
1
0.1
Gate Capacitance – nF
1
Figure 8
POST OFFICE BOX 655303
10
Gate Capacitance – nF
Figure 7
16
0.1000
Figure 6
1000
1
0.1
0.0100
Slow-start Capacitance – µF
• DALLAS, TEXAS 75265
100
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
DRIVER
DRIVER
HIGH-SIDE OUTPUT RESISTANCE
vs
JUNCTION TEMPERATURE
LOW-SIDE OUTPUT RESISTANCE
vs
JUNCTION TEMPERATURE
5.0
8
4.5
7
R O – Low-Side Output Resistance – Ω
R O – High-Side Output Resistance – Ω
TYPICAL CHARACTERISTICS
4.0
3.5
3.0
2.5
2.0
1.5
1.0
6
5
4
3
2
1
0
0
25
50
75
100
TJ – Junction Temperature – °C
125
0
25
50
75
100
TJ – Junction Temperature – °C
Figure 9
Figure 10
DRIVER
VDRV UVLO START THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
CURRENT
vs
OUTPUT VOLTAGE
5
4.70
VDRV UVLO Start Threshold Voltage – V
4.5
4
3.5
Input Current – A
125
3
2 A Typical
2.5
2
1.5
1
4.5 V
0.5
0
4.69
4.68
4.67
4.66
4.65
0
1
2
3
4
5
6
7
8
9
0
VO – Output Voltage – V
Figure 11
25
50
75
100
TJ – Junction Temperature – °C
125
Figure 12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
TYPICAL CHARACTERISTICS
RIPPLE REGULATOR
POWER GOOD THRESHOLD
vs
JUNCTION TEMPERATURE
VDRV UVLO HYSTERESIS
vs
JUNCTION TEMPERATURE
96
Ripple Regulator Powergood Threshold – %
300
VDRV UVLO Hysteresis – mV
280
260
240
220
200
180
160
140
120
95
94
93
92
91
90
89
88
100
0
25
50
75
100
TJ – Junction Temperature – °C
0
125
Figure 13
INHIBIT HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
2.100
140
INHIBIT Hysteresis Voltage – mV
INHIBIT Start Threshold Voltage – V
125
Figure 14
INHIBIT START THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.075
2.050
2.025
2.000
130
120
110
100
90
0
25
50
75
100
TJ – Junction Temperature – °C
125
0
Figure 15
18
25
50
75
100
TJ – Junction Temperature – °C
25
50
75
100
TJ – Junction Temperature – °C
Figure 16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
TYPICAL CHARACTERISTICS
RIPPLE REGULATOR OVP THRESHOLD
vs
JUNCTION TEMPERATURE
RIPPLE REGULATOR UVP THRESHOLD
vs
JUNCTION TEMPERATURE
Ripple Regulator UVP Threshold – %
77
117
116
115
114
113
112
0
25
50
75
100
76
75
74
73
72
71
125
0
25
TJ – Junction Temperature – °C
50
75
100
125
TJ – Junction Temperature – °C
Figure 17
Figure 18
OCP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
135
OCP Treshhold Voltage – mV
Ripple Regulator OVP Threshold – %
118
133
131
129
0
25
50
75
100
125
TJ – Junction Temperature – °C
Figure 19
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• DALLAS, TEXAS 75265
19
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
TYPICAL CHARACTERISTICS
LDO OVP THRESHOLD
vs
JUNCTION TEMPERATURE
118
LDO OVP Threshold – %
117
116
115
114
113
112
0
25
50
75
100
TJ – Junction Temperature – °C
125
Figure 20
LDO UVP THRESHOLD
vs
JUNCTION TEMPERATURE
77
LDO UVP Threshold – %
76
75
74
73
72
71
0
25
50
75
100
TJ – Junction Temperature – °C
Figure 21
20
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125
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
APPLICATION INFORMATION
evaluation module
In many DSP applications, the voltage bus powering DSP I/O also has to power peripheral circuitry. The total
current is much higher than the requirement for the I/O only. This is the reason to use the high-efficiency ripple
regulator to power I/O. In turn, the core power is delivered by LDO output. Since the I/O voltage is lower than
the input voltage in cases such as 5-V input, but higher than the core voltage, the ripple regulator output should
be used as the input voltage for LDO to achieve higher efficiency. In EVM testing, J1–4 (RR–OUT) is connected
to J2–1(VI–LDO). The test results displayed in this section are all based on this configuration.
TP6
FB2
+
J2
TP5
+
JP3
L1
3.3 uH
+
TP8
Q1:A
J1
Q4
TP7
TP1
+
TP11
+
E1
TP3
U1
TP4
TPS563xxPWP
PwrPad
TP2
Q1:B
+
+
+
Q5
+
TP10
FB1
JP1
JP2
Figure 22. EVM Schematic
Table 2. EVM Input and Outputs
VIN
5V
IIN
4A
VRR
3.3 V
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4A
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VLDO
1.8 V
ILDO
0.5 A
21
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
APPLICATION INFORMATION
Table 3. Ripple Regulator Power Stage Components
Ref Des
Function
4A (EVM Design)
Ripple Regulator Section
8A†
12A†
20A†
C3, C6
Input bulk
capacitor
C3: open
C6: 150 µF
(Sanyo,
6TPB150M)
C3: 150 µF
C6: 150 µF
(Sanyo,
6TPB150M)
C3: 150 µF
C6: 150 µF
(Sanyo,
6TPB150M)
C3: 150 µF
C6: 2x150 µF
(Sanyo,
6TPB150M)
C11, C2
Input high-freq
capacitor
C2: 0.1 µF
C11: 0.1 µF
(muRata
GRM39X7R104K016A,
0.1 µF, 16–V, X7R)
C2: 0.1 µF
C11: 0.1 µF
(muRata
GRM39X7R104K016A,
0.1 µF, 16–V, X7R)
C2: 0.1 µF
C11: 0.1 µF
(muRata
GRM39X7R104K016A, 0.1
µF, 16–V, X7R)
C2: 0.33 µF
C11: 0.33 µF
(muRata
GRM39X7R334K016A,
0.33 µF, 16–V, X7R)
C13, C14
Output bulk
capacitor
C13: 150 µF
(Sanyo, 6TPB150M)
C14: open
C13: 150 µF
(Sanyo, 6TPB150M)
C14: open
C13: 150 µF
C14: 150 µF
(Sanyo, 6TPB150M)
C13: 150 µF
C14: 150 µF
(Sanyo, 6TPB150M)
C15,C30,
C31
Output mid-freq
capacitor
C15: open
C30: 10 µF
C31: 10 µF
(muRata
GRM39X7R106K016A,
10 µF, 16–V, X7R)
C15: open
C30: 10 µF
C31: 10 µF
(muRata
GRM39X7R106K016A,
10 µF, 16–V, X7R)
C15: 10 µF
C30: 10 µF
C31: 10 µF
(muRata
GRM39X7R106K016A, 10
µF, 16–V, X7R)
C15: 10 µF
C30: 10 µF
C31: 10 µF
(muRata
GRM39X7R106K016A,
10 µF, 16–V, X7R)
C16
Output high-freq
capacitor
open
0.1 µF
(muRata
GRM39X7R104K016A,
0.1 µF, 16–V, X7R)
0.1 µF
0.1 µF
(muRata
(muRata
GRM39X7R104K016A, 0.1 GRM39X7R104K016A,
µF, 16–V, X7R)
0.1 µF, 16–V, X7R)
L1
Input filter
3.3 µH
Coilcraft
DO3316P–332, 5.4 A
3.3 µH
Coilcraft
DO3316P–332,5.4 A
1.5 µH
Coilcraft
DO3316P–152,6.4 A
1 µH
Coiltronics
UP3B–1R0, 12.5–A
L2
Output filter
3.3 µH
Coilcraft
DO3316P–332, 5.4 A
3.3 µH
Coilcraft
DO5022P–332HC, 10 A
1.5 µH
Coilcraft
DO5022P–152HC,
15 A
3.3 µH
Micrometals,
T68–8/90 Core w/7T,
#16, 25 A
R8
Low side gate
resistor
10 Ω
10 Ω
5.1 Ω
5.1 Ω
Q1A,Q4
Power switch
Q1A: Dual FET
IRF7311
Q4: IRF7811
Q4: 2xIRF7811
Q4: 2xIRF7811
Synchronous
Q1B: Dual FET
switch
IRF7311
† Position available on the EVM board
Q5: IRF7811
Q5: 2xIRF7811
Q5:
2xIRF7811
Q1B,Q5
The values listed in Table 3 are recommendations based on actual test circuits. Many variations of the above
are possible based upon the desires and/or requirements of the user. Performance of the circuit is equally, if
not more, dependent upon the layout than on the specific components, as long as the device parameters are
not exceeded. Fast-response, low-noise circuits require circuits require critical attention to the layout details.
22
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
APPLICATION INFORMATION
Table 4. LDO Power Stage Components
LDO Section
Ref. Des
Part
Q2:A
VIN
Q2:A
IRF7811(EVM)
or
Si4410, IRF7413‡
FDS6680
IRF9410, Si9410‡
Q2:A
IRF7811‡
Q2: B
IRLZ24N‡
VOUT
Description
VIN– VDROPOUT†
VIN
Used as a power distribution switch for
LDO output control
Low cost solution for low LDO output current (VIN–VOUT)*IOUT < 1 W
Higher current and still surface mount
1 W < (VIN–VOUT)*IOUT) < 2 W
High output current requiring heat sink.
Low cost but through–hole package.
(VIN–VOUT)*IOUT > 2 W
† VDROPOUT = IOUT × RDSON. It should be as small as possible.
‡ Position available on the EVM board
frequency calculation
With hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the
hysteresis window, the delay of the hysteresis comparator and the driver, the output inductance, the resistance
in the output inductor, the output capacitance, the ESR and ESL in the output capacitor, the output current, and
the turnon resistance of high-side and low-side MOSFET. It is a very complex equation if everything is included.
To make it more useful to designers, a simplified equation is developed that considers only the most influential
factors. The tolerance of the result for this equation is about 30%:
fs
+
V
IN
ǒ
V
V
OUT
IN
ǒ
V
* VOUT
IN
ESR
ǒ
250
Ǔ ȡȧȢ
10 –9
ESR
Ǔ
*
ǒ
250 10 –9
) Td ) Vhys
C
out
L
Ǔȣȧ
)Td
OUT
Ȥ
* ESL
V
Ǔ
IN
Where fs is the switching frequency (Hz); VOUT is the output voltage (V); VIN is the input voltage (V); COUT is
the output capacitance; ESR is the equivalent series resistance in the output capacitor (Ω); ESL is the equivalent
series inductance in the output capacitor (H); LOUT is the output inductance (H); Td is output feedback RC filter
time constant (S); Vhys is the hysteresis window (V).
output voltage setpoint calculation
In some applications, the required output voltage is different from the VID reference voltage. In this case,
external voltage divider can be used for the setpoint adjustment. The voltage divider is composed of two
resistors. The equation for the setpoint is:
R
+
bottom
R top
V
V
R
* VR
O
Where VR is the reference voltage; VO is the required output voltage setpoint. VR should be lower than VO. In
EVM design, the top resistor is R14 for the LDO output, or R10 for ripple regular output; the bottom resistor is
R15 for LDO output, or R12 for ripple regulator output.
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
APPLICATION INFORMATION
hysteresis window
The changeable hysteresis window in TPS56302 is used for switching frequency and output voltage ripple
adjustment. The hysteresis window setup is decided by a two-resistor voltage divider on VREFB and VHYST
pin. Two times the voltage drop on the top resistor is the hysteresis window. The formula is shown in the
following:
Vhyswindow = 2 × VREFB × ( 1 –
R 13
)
R 11 + R 13
Where Vhyswindow is the hysteresis window (V); VREFB is the regulated voltage from VREVB (pin 5); R11 is the
top resistor in the voltage divider; R13 is the bottom resistor in the voltage divider. The maximum hysteresis
window is 60 mV.
slow-start
Slow-start reduces the start-up stresses on the power-stage components and reduces the input current surge.
The minimum slow-start time is limited to 1 ms due to the power good function deglitch time. Slow-start timing
is dependent on the timing capacitor value on the slow-start pin and the total resistance on VREFB. The
following formula can be used for setting the slow-start timing:
T
SLOW-START
+5
C
SLOW-START
R
VREFB
TSLOW-START is the slow-start time; CSLOW-START is the capacitor value on SLOWST (pin 3). RVREFB is the total
resistance on VREFB (pin 5).
current limit
Current limit is implemented using the on-resistance of the upper FETs as the sensing elements. The IOUT
signal is used for the current limit and the droop function. The voltage at IOUT at the output current trip point
will be:
V
IOUT
+ RON
ǒǒ
I
2
O
Ǔ
RON is the high-side on-time resistance; IO is the output current. The current limit is calculated by using the
equation:
R5
+
R4
I
Ǔ
O MAX
2
R
0.125
ON
* 0.125
Where R4 is the bottom resistor in the voltage divider on OCP pin, and R5 is the top resistor; IO(MAX) is the
maximum current allowed; RON is the high-side FET on-time resistance.
Since the FET on-time resistance varies according to temperature, the current limit is basically for catastrophic
failure.
24
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
APPLICATION INFORMATION
droop compensation
Droop compensation with the offset resistor divider from VOUT to the VSENSE is used to keep the output voltage
in range during load transients by increasing the output voltage setpoint toward the upper tolerance limit during
light loads and decreasing the voltage setpoint toward the lower tolerance limit during heavy loads. This allows
the output voltage to swing a greater amount and still remain within the tolerance window. The maximum droop
voltage is set with R6 and R7:
V
DROOPǒmaxǓ
+ VIOUTǒmaxǓ
) R7
R6
R6
Where VDROOP(max) is the maximum droop voltage; VIOUT(max) is the maximum VIOUT that reflects the
maximum output current (full load); R6 is the bottom resistor of the divider connected to the DROOP pin, R7
is the top resistor.
The offset voltage is set to be half of the maximum droop voltage higher than the nominal output voltage, so
the whole droop voltage range is symmetrical to the nominal output voltage. The formula for setting the offset
voltage is:
V
OFFSET
+ 12
V
DROOPǒmaxǓ
+ VO
ǒ
Ǔ
)
R12
R10 R12
Where VOFFSET is the desired offset voltage; VDROOP(max) is the droop voltage at full load; VO is the nominal
output voltage; R10 is the top resistor of the offset resistor divider, and R12 is the bottom one.
Therefore, with the setup above, at light load, the output voltage is:
V
Ǔ + VOǒnomǓ ) VOFFSET + VOǒnomǓ ) 12
ǒ
V
O NO LOAD
DROOP
And, at full load, the output voltage is:
V
Ǔ + VOǒnomǓ * VOFFSET + VOǒnomǓ * 12
ǒ
O FULL LOAD
V
DROOP
output inductor ripple current
The output inductor current ripple can affect not only the efficiency, but also the output voltage ripple. The
equation for calculating the inductor current ripple is exhibited in the following:
I
ripple
+
V
IN
* VOUT * IOUT
L
ǒ
r
DS(on)
Ǔ
) RL
D
Ts
OUT
Where Iripple is the peak-to-peak ripple current (A) through the inductor; VIN is the input voltage (V); VOUT is the
output voltage (V); IOUT is the output current; rDS(on) is the on-time resistance of MOSFET (Ω); RL is the output
inductor equivalent series resistance; D is the duty cycle; and Ts is the switch cycle (S). From the equation, it
can be seen that the current ripple can be adjusted by changing the output inductor value.
Example:
VIN = 5 V; VOUT = 1.8 V; IOUT = 5 A; rDS(on) = 10 mΩ; RL = 5 mΩ; D = 0.36; Ts = 5 µs; LOUT = 6 µH
Then, the ripple Iripple = 1 A.
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
APPLICATION INFORMATION
output capacitor RMS current
Assuming the inductor ripple current totally goes through the output capacitor to ground, the RMS current in the
output capacitor can be calculated as:
IO(rms) =
∆I
12
Where IO(rms) is the maximum RMS current in the output capacitor (A); ∆I is the peak-to-peak inductor ripple
current (A).
Example:
∆I = 1 A, so IO(rms) = 0.29 A
input capacitor RMS current
The input capacitor RMS current is important for input capacitor design. Assuming the input ripple current totally
goes into the input capacitor to the power ground, the RMS current in the input capacitor can be calculated as:
I
I(rms)
+
Ǹ
I
2
O
D
(1
* D) ) 121
D
I
2
ripple
Where II(rms) is the input RMS current in the input capacitor (A); IO is the output current (A); Iripple is the
peak-to-peak output inductor ripple current; D is the duty cycle. From the equation, it can be seen that the
highest input RMS current usually occurs at the lowest input voltage, so it is the worst case design for input
capacitor ripple current.
Example:
IO = 5 A; D = 0.36; Iripple = 1 A,
Then, II(rms) = 2.46 A
layout and component value consideration
Good power supply results will only occur when care is given to proper design and layout. Layout and
component value will affect noise pickup and generation and can cause a good design to perform with less than
expected results. With a range of current from milliamps to tens or even hundreds of amps, good power supply
layout and component selection, especially for a fast ripple controller, is much more difficult than most general
PCB design. The general design should proceed from the switching node to the output, then back to the driver
section, and, finally, to placing the low-level components. In the following list are several specific points to
consider before layout and component selection for TPS56302:
1. All sensitive analog components should be referenced to ANAGND. These include components connected
to SLOWST, DROOP, IOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and LOSENSE/LOHIB.
2. The input voltage range for TPS56302 is low from 2.8-V to 5.5-V, so it has a voltage tripler (charge pump)
inside to deliver proper voltage for internal circuitry. To avoid any possible noise coupling, a low ESR
capacitor on VCC is recommended.
3. For the same reason in Item 2, the ANAGND and DRVGND should be connected as close as possible to
the IC.
4. The bypass capacitor should be placed close to the TPS56302.
26
POST OFFICE BOX 655303
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
APPLICATION INFORMATION
layout and component value consideration (continued)
5. When configuring the high-side driver as a boot-strap driver, the connection from BOOTLO to the power
FETs should be as short and as wide as possible. LOSENSE/LOHIB should have a separate connection
to the FETs since BOOTLO will have large peak current flowing through it.
6. The bulk storage capacitors across VIN should be placed close to the power FETs. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
7. HISENSE and LOSENSE/LOHIB should be connected very close to the drain and source, respectively, of
the high-side FET. HISENSE and LOSENSE/LOHIB should be routed very close to each other to minimize
differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to
where HISENSE connects to VIN, to reduce high-frequency noise coupling on HISENSE.
The EVM board (SLVP-139) is used in the test. The test results are shown in the following.
EFFICIENCY OF
RIPPLE REGULATOR (3.3 V)
RIPPLE REGULATOR
LOAD REGULATION (3.3 V)
100
2
VIN = 5 V
VIN = 5 V
90
Load Regulation – %
Efficiency – %
1
80
70
60
0
–1
50
40
0
1
2
3
4
5
–2
0
IO – Output Current – A
1
2
3
4
5
IO – Output Current – A
Figure 23
Figure 24
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• DALLAS, TEXAS 75265
27
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
APPLICATION INFORMATION
RIPPLE REGULATOR
LINE REGULATION (3.3 V)
LDO LOAD REGULATION (1.8 V)
2
2
VIN = 5 V
1
1
Line Regulation – %
Line Regulation – %
IO = 2 A
0
–1
0
–1
–2
3.5
3
4.5
4
5.5
5
–2
6
0.2
0
VIN – Input Voltage – V
0.4
Figure 25
5
5
VO – Output Voltage – V
I L – Load Current – A
VO – Output Voltage – mV
6
0
No Droop
Output Voltage
200
100
1.2
4
3.3 V
3
2
1
1.8 V
0
220 mV
–1
0
With Droop
–2
–100
0
0.5
1
1.5
2 2.5 3
t – Time – ms
3.5
4
4.5
5
0
4
8
12
16 20 24
t – Time – ms
Figure 28
Figure 27
28
1
SLOW-START
10
280 mV
0.8
Figure 26
DROOP COMPENSATION EFFECT
–5
0.6
IO – Output Current – A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
28
32
36
40
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
APPLICATION INFORMATION
layouts
3 in
2.7 in
Figure 29. Top Layer
Figure 30. Bottom Layer (Top View)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
APPLICATION INFORMATION
bill of materials
REF
PN
Description
MFG
Size
C1
10TPA33M
Capacitor, POSCAP, 33 µF, 10 V
Sanyo
C
C2, C20, C21, C30, C31
Std
Capacitor, Ceramic, 10 µF, 16 V
Sanyo
1210
C3. C6, C8, C13, C25
6TPB150M
Capacitor, POSCAP, 150 µF, 6 V
Sanyo
D
C4, C5, C11, C12, C23, C26, C27,
Std
Capacitor, Ceramic, 0.1 µF, 16 V
Sanyo
603
C7, C22
Std
Capacitor, Ceramic, 1 µF, 16 V
Sanyo
805
C9
Std
Open
1210
C10, C16
Std
Open
603
C14, C15
Std
Open
C17, C24
Std
Capacitor, Ceramic, 1000 pF, 16 V
Sanyo
603
C18, C19
Std
Capacitor, Ceramic, 1 µF, 16 V
Sanyo
805
D1
SML-LX2832G
Diode, LED, Green, 2.1 V SM
Lumwx
1210
L1, L2
DO3316P-332
Inductor, 3.3 µH, 5.4 A
Coilcraft
0.5 × 0.37 in
J1
ED2227
Terminal Block, 4-pin, 15 A, 5.08 mm
OST
5.08 mm
J2
ED1515
Terminal Block, 3-pin, 6 A, 3.5 mm
OST
n, 6 A,
JP1, JP2
S1132-3-ND
Header, Right straight, 3-pin, 0.1 ctrs,
0.3” pins
Sullins
#S1132-3-ND
JP1shunt
929950-00-ND
Shunt jumper, 0.1” (for JP1)
3M
0.1”
J3
S1132-2-ND
Header, Right straight, 2-pin, 0.1 ctrs,
0.3” pins
Sullins
#S1132-2-ND
Q1
Q2:A, Q4, Q5
IRF7811
Q2:B
D
Open
SO-8
MOSFET, N-ch, 30 V, 10 mΩ
SO-8
Open
TO–220
Q3
2N7002DICT-N
MOSFET, N-ch, 115 mA, 1.2 Ω
R3
std
Resistor, 10 kohms, 5 %
603
R4
std
Resistor, 1 kohms, 1%
603
R5
std
Resistor, 0 ohms, 1%
603
R6
std
Resistor, 1 kohms, 1%
603
R7
std
Resistor, 3.32 kohms, 1%
603
R8
std
Resistor, 10 ohms, 5 %
603
R9
std
Resistor, 2.7 ohms, 5 %
1206
R10
std
Resistor, 150 ohms, 5 %
603
R11
std
Resistor, 100 ohms, 1 %
603
R12
std
Resistor, 10 kohms, 5 %
603
R13
std
Resistor, 20.0 kohms, 1 %
603
R14
std
Resistor, 0 ohms, 5%
603
R15
std
Resistor, open
603
R16
std
Resistor, 15 kohms, 5 %
TP1–TP10
240–345
Test Point, Red
Farnell
TP11
131–4244–00
Adaptor, 3.5-mm probe clip
(or 131–5031–00)
Tektronix
U1
TPS56302PWP
Dual controller
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Diodes, Inc.
TO-236
805
TSSOP–28pin
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
APPLICATION INFORMATION
Power Supply
5–V, 5–A Supply
–
+
Load
+
0–4A
–
6.8 Ohms
2W
Jumper Pins 2–3
NOTE A: All wire pairs should be twisted.
Figure 31. Test Setup
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
APPLICATION INFORMATION
DSP power application
In DSP power applications, TPS56302 is used in the applications that require more current for peripheral and
DSP I/O. The power good (PG) output can be used for monitoring or controlling as an optional function. In the
EVM schematic, Q3, D1, R1, and R2 are the circuit to show this function.
Ripple
Regulator
VIN
RR
Output
LDO
Output
Core
LDO
DSP
I/O
Peripheral
PG output (optional)
Figure 32. TPS56302 For High Peripheral Current DSP Application
TPS56300 is used in the applications that require high current for core, but low current for I/O. Another important
feature is that, if the input voltage is the same as the LDO output, the LDO switch acts as a distribution switch
to control the on/off of the LDO output.
VIN
Ripple
Regulator
RR Output
Core
DSP
LDO Output
I/O
LDO
PG output (optional)
Figure 33. TPS56300 For On/Off Control DSP Application
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
20-PIN SHOWN
0,30
0,19
0,65
20
0,10 M
11
Thermal Pad
(See Note D)
4,50
4,30
0,15 NOM
6,60
6,20
Gage Plane
1
10
0,25
A
0°– 8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
5,10
5,10
6,60
7,90
9,80
A MIN
4,90
4,90
6,40
7,70
9,60
DIM
4073225/E 03/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
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Copyright  2000, Texas Instruments Incorporated