Page 1 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter FEATURES • • • • • • • • Form, Fit, and Function Compatible with the National NS16450 Packaging options available: 40 Pin Plastic or 44 Pin Plastic Leaded Chip Carrier Programmable Word Length, Stop Bits, and Parity Full Duplex Operation Programmable Baud Rate Generator - Division of any input clock by 1 to (216 –1) - Generates Internal 16 x clock Programmable Serial-Interface - 5-, 6-, 7- or 8-bit characters - Even, Odd, or No-Parity Bit Generation and Detection - 1-, 1 ½-, or 2-Stop Bit Generation - Baud Generation of DC to 56k Prioritized Interrupt Control Internal Diagnostic/Loopback Capabilities The IA16450 uses innovASIC’s innovative new f 3 Program to provide industry with parts that other vendors have declared obsolete. By specifying parts through this program a customer is assured of never having a component become obsolete again. This advanced information sheet assumes the original part has been designed in, and so provides a summary of capabilities only. For new designs contact innovASIC for more detailed information. National is a copyright trademark of National Semiconductor Corporation D3 D2 D1 D0 N. C. VCC RI_n DCD_n DSR_n CTS_n (3) (2) (1) (44) (43) (42) (41) (40) D2 VCC (4) (2) D4 (1) D1 (5) D0 (6) Package Pinout IA16450 (40) 40 Pin DIP (39) RI_n (3) (38) DCD_n D3 (4) (37) DSR_n D4 (5) (36) CTS_n D5 (7) (39) D5 (6) (35) MR D6 (8) (38) OUT1_n D6 (7) (34) OUT1_n D7 (9) (37) DTR_n D7 (8) (33) DTR_n (36) RTS_n (35) OUT2_n N. C. RCLK RCLK (9) (32) RTS_n SIN (10) (31) OUT2_n SOUT (11) (30) CS0 (12) IA16450 (10) 44 Pin LCC MR SIN (11) N. C. (12) (34) INTR SOUT (13) (33) INTR (29) N. C. CS0 (14) (32) N. C. CSOUT (23) DDIS WR (19) (22) RD VSS (20) (21) RD_n Copyright 1999, InnovASIC Inc. Customer Specific IC Solutions (28) (24) (18) ADS_n (17) XIN XOUT WR_n (27) ADS_n DDIS (25) CSOUT (16) (26) A2 XIN (25) (29) RD (17) (24) BAUDOUT_n RD_n A2 (23) (26) N. C. (15) (22) A1 BAUDOUT_n VSS A0 (30) (21) (31) (16) (20) (15) CS2_n WR CS1 A1 (19) A0 (27) XOUT (28) (14) WR_n (13) (18) CS1 CS2_n Page 2 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter The IA16450 is a form, fit and function compatible part to the National NS16450 Univeral Asynchronous Receiver/Transmitter. The IA16450 function receives and transmits data in a variety of configurations including 5, 6, 7 or 8 bit data words, odd, even or no parity, and 1, 1.5, and 2 stop bits. This megafunction includes an internal Baud Rate Generator and Interrupt Control. A block diagram is shown in Figure 1. Functional Block Diagram Figure 1 INTERNAL DATA BUS D7:D0 DATA BUS BUFFER RECEIVER BUFFER REGISTER RECEIVER SHIFT REGISTER LINE CONTROL REGISTER RECEIVER TIMING & CONTROL SIN RCLK DIVISOR LATCH (LSB) A0 BAUDOUT_n A1 BAUD GENERATOR A2 DIVISOR LATCH (MSB) CS0 CS1 CS2_n ADS_n MR RD DECODE AND CONTROL LOGIC LINE STATUS REGISTER TRANSMITTER TIMING & CONTROL TRANSMITTER HOLDING REGISTER TRANSMITTER SHIFT REGISTER RD_n WR WR_n SOUT DDIS CSOUT RTS_n XIN XOUT MODEM CONTROL REGISTER CTS_n DTR_n MODEM CONTROL LOGIC MODEM STATUS REGISTER DSR_n DCD_n RI OUT1_n OUT2_n INTERRUPT ENABLE REGISTER INTERRUPT CONTROL LOGIC INTERRUPT ID REGISTER Copyright 1999, InnovASIC Inc. Customer Specific IC Solutions INTR Page 3 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter I/O Signal Description Table 1 below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provided. Table 2 refers to the address register map. Table 3 refers to the Preliminary A. C. Characteristics. Figure 2 illustrates the Preliminary Timing Waveforms for this device. Environmental/Qualification Levels are listed in Table 4. Table 1 Name Type Description MR I Master Reset - Active high - Clears all registers (except the receiver buffer, transmitter holding and divisor latches) to their initial state. Resets internal control logic to its initial state A(2:0) I Register Address - Active high - This bus selects one of the internal UART registers (refer to table 1). Note the state of the divisor latch access bit (DLAB - the msb of the line control register) must be set high to access the divisor latches and low to access the receiver buffer or the interrupt enable register. DIN(7:0) I Data Input Bus - Active high - Serves as input data when writing to internal UART registers. CS0 I Chip Select 0 - Active high - When CS0, CS1 and CS2 are active the megafunction is selected. Read and write transactions to internal UART registers are then possible. CS1 I Chip Select 1 - Active high - When CS0, CS1 and CS2 are active the megafunction is selected. Read and write transactions to internal UART registers are then possible. CS2_n I Chip Select 2 - Active low - When CS0, CS1 and CS2 are active the megafunction is selected. Read and write transactions to internal UART registers are then possible. ADS_n I Address Strobe - Active low - Gating signal to the Address input latch. The positive edge of ADS_n latches the state of the register address bus into the Address input latch. If address signals are guaranteed to be stable for the duration of a read or write cycle, ADS_n may be tied low thus forcing the Address input latch to be transparent. RD I Read Control - Active High - when RD is high or RD_n is low and the UART is selected, read transactions from internal UART registers are possible. Copyright 1999, InnovASIC Inc. Customer Specific IC Solutions Page 4 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter Name Type Description RD_n I Read Control - Active low - when RD is high or RD_n is low and the UART is selected, read transactions from internal UART registers are possible. WR I Write Control - Active High - when WR is high or WR_n is low and the UART is selected, write transactions to internal UART registers are possible. WR_n I Write Control - Active low - when WR is high or WR_n is low and the UART is selected, write transactions to internal UART registers are possible. SIN I Serial Data Input - Active High - Receive data to the UART RCLK I Receive Clock - The 16x baud rate clock used by the receiver section of the UART. CTS_n I Clear To Send - Active Low - Active state indicates that the MODEM or data set is ready to exchange data. A change in state of this input is recorded in the DCTS bit (bit 0) of the MODEM Status register. Whenever CTS_n changes state, an interrupt is generated if the MODEM Status interrupt is enabled. The complement of this input is recorded in the CTS (bit 4) bit of the MODEM Status register DSR_n I Data Set Ready - Active Low - Active state indicates that the MODEM or data set is ready to establish the communications link with the UART. A change in state of this input is recorded in the DDSR bit (bit 1) of the MODEM Status register. Whenever DSR_n changes state, an interrupt is generated if the MODEM Status interrupt is enabled. The complement of this input is recorded in the DSR (bit 5) bit of the MODEM Status register DCD_n I Data Carrier Detect - Active Low - Active state indicates that the data carrier has been detected by the MODEM or data set. A change in state of this input is recorded in the DDCD bit (bit 3) of the MODEM Status register. Whenever DCD_n changes state, an interrupt is generated if the MODEM Status interrupt is enabled. The complement of this input is recorded in the DCD (bit 7) bit of the MODEM Status register Copyright 1999, InnovASIC Inc. Customer Specific IC Solutions Page 5 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter Name Type Description RI_n I Ring Indicator - Active Low - Active state indicates that the ring signal has been detected by the MODEM or data set. A change in state of this input is recorded in the TERI bit (bit 2) of the MODEM Status register. Whenever DSR_n changes state, an interrupt is generated if the MODEM Status interrupt is enabled. The complement of this input is recorded in the RI (bit 6) bit of the MODEM Status register DOUT(7:0) O Data Output Bus - Active high - Serves as output data when reading from internal UART registers. DDIS O Driver Disable - Active High - Active State indicates that the CPU is reading data from the UART. This output is intended as a disable or direction control between the UART and CPU. CSOUT O Chip Select Output - Active High - Active State indicates that the megafunction has been selected by use of the CS0, CS1 and CS2_n inputs. SOUT O Serial Data Out - Active High - Serial (transmit) data out. This signal is set to the marking (logic 1) state upon master reset. BAUDOUT_n O Baud Out - Active Low - The 16x baud rate clock used by the transmitter section of the UART. This output is controlled by the programmable baud rate generator. RTS_n O Request to Send - Active Low - This output indicates that the UART is ready to exchange data. This output is controlled by writing to the RTS (bit 1) bit of the control register. DTR_n O Data Terminal Ready - Active Low - This output indicates that the UART is ready to establish a communications link. This output is controlled by writing to the DTR (bit 0) bit of the control register. OUT1_n O Discrete Output - Active Low - One of two user-programmable discrete outputs. This output is controlled by writing to the OUT1 (bit 2) bit of the control register. OUT2_n O Discrete Output - Active Low - One of two user-programmable discrete outputs. This output is controlled by writing to the OUT2 (bit 3) bit of the control register. INTR O Interrupt - Active High - Indicates that an enabled interrupt has had its interrupt condition met. Copyright 1999, InnovASIC Inc. Customer Specific IC Solutions Page 6 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter Name Type I XIN XOUT O VSS VCC P P Description External Crystal Input. This signal iniput is used in conjuction with XOUT to form a feedback circuit for the baud rate generator’s oscillator. If a clock signal will be generated offchip, then it should drive the baud rate generator through this pin External Crystal Output. This signal output is used in conjuction with XIN to form a feedback circuit for the baud rate generator’s oscillator. If the clock signal will be generated off-chip, then this pin is unused. Ground. +5V power. IA16450 Register Address Map Table 2 DLAB A2 A1 A0 0 0 0 0 Receiver Buffer - Read Only Transmitter Holding Register - Write Only 1 0 0 0 Divisor Latch (LSB) 0 0 0 1 Interrupt Enable Register 1 0 0 1 Divisor Latch (MSB) X 0 1 0 Interrupt ID Register X 0 1 1 Line Control Register 1 0 0 MODEM Control Register X 1 0 1 Line Status Register X 1 1 0 MODEM Status Register X 1 1 1 Scratch X DATA REGISTER DESCRIPTION Copyright 1999, InnovASIC Inc. Customer Specific IC Solutions Page 7 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter AC Electrical Characteristics Table 3 Symbol Parameter Min tADS Address Strobe Width 25 tAH Address Hold Time 0 tAR RD, RD_n Delay from Address tAS Address Setup Time tAW WR, WR_n Delay from Address tCH Chip Select Hold Time 0 tCS Chip Select Setup Time 25 tCSC Chip Select Output Delay from Select tCSR RD, RD_n Delay fron Select tCSW WR, WR_n Delay fron Select tDH Data Hold Time 10 tDS Data Setup Time 20 tHZ RD, RD_n to Floating Data Delay 0 tRA Address Hold Time from RD, RD_n tRC Read Cycle Delay tRCS Chip Select Hold Time from RD, RD_n tRD RD, RD_n Strobe Width tRDD RD, RD_n to Driver Disable Delay 20 tRVD Delay from RD, RD_n to Data 31 tWA Address Hold Time from WR, WR_n 0 tWC Write Cycle Delay 36 tWCS Chip Select Hold Time from WR, WR_n tWR WR, WR_n Strobe Width 60 RC Read Cycle = tAR + t RD + t RC 115 WC Write Cycle = t AW + t WR +tWC 115 Note 1: (Note 1) Max 20 25 (Note 1) 20 (Note 1) (Note 1) 33 20 (Note 1) 20 (Note 1) 25 0 36 (Note 1) 0 60 (Note 1) Applicable only when ADS_n is tied low. Copyright 1999, InnovASIC Inc. Customer Specific IC Solutions 0 Page 8 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter Timing Waveforms Figure 2 Write Cycle tADS ADS_n tAS A2,A1,A0 tAH VALID tCS CS2_n,CS1,CS0 t CH tWA VALID tCSC tWCS CSOUT tCSW t WR tWC tAW WC ACTIVE WR_n,WR ACTIVE RD_n,RD ACTIVE tDS DATA,D0:D7 t DH VALID DATA Read Cycle t ADS ADS_N tAS A2,A1,A0 tRA tCH tRCS VALID tCS CS2_n,CS1,CS0 tAH VALID tCSC CSOUT t CSR RC tAR RD_n,RD tRD tRC ACTIVE ACTIVE WR_n,WR ACTIVE t RDD tRDD t RVD tHZ DDIS DATA,D0:D7 VALID DATA Copyright 1999, InnovASIC Inc. Customer Specific IC Solutions Page 9 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter Qualification Levels Table 4 Part Number IA16450-PDW40C IA16450-PLC44C IA16450-PDW40I IA16450-PLC44I Environmental/ Qual Level Commercial Commercial Industrial Industrial The following diagram depicts the innovASIC Product Identification Number. IAXXXXX-PPPPNNNT/SP Special Processing: S = Space Q = MIL-STD-883 Temperature: C = Commercial I = Industrial M = Military Number of Leads Package Type: Per Package Designator Table IC Base Number innovASIC Designator Copyright 1999, InnovASIC Inc. Customer Specific IC Solutions Page 10 of 10 IA16450 Preliminary Data Sheet Universal Asynchronous Receiver/Transmitter Package Designator Table Package Type innovASIC Designator Ceramic side brazed Dual In-line Cerdip with window Ceramic leaded chip carrier Cerdip without window Ceramic leadless chip carrier PLCC Plastic DIP standard (300 mil) Plastic DIP standard (600 mil) Plastic metric quad flat pack Plastic thin quad flat pack Skinny Cerdip Small outline plastic gull-wing(150 mil body) Small outline medium plastic gull-wing (207 mil body) Small outline narrow plastic gull wing (150 mil body) Small outline wide plastic gull wing (300 mil body) Skinny Plastic Dip Shrink small outline plastic (5.3mm .208 body) Thin shrink small outline plastic Small outline large plastic gull wing (330 mil body) Thin small outline plastic gull-wing (8 x 20mm) [TSOP] CDB CDW CLC CD CLL PLC PD PDW PQF PTQ CDS PSO PSM PSN PSW PDS PS PTS PSL PST PGA BGA CPGA CBGA Contact innovASIC for other package and processing options. Copyright 1999, InnovASIC Inc. Customer Specific IC Solutions