TECHNICAL DATA IN74ACT175 Quad D Flip-Flop with Common Clock and Reset High-Speed Silicon-Gate CMOS The IN74ACT175 is identical in pinout to the LS/ALS175, HC/HCT175. The IN74ACT175 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of four D flip-flops with common Reset and Clock inputs, and separate D inputs. Reset (active-low) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D input is transferred to the corresponding Q output on the next positive-going edge of the Clock input. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA; 0.1 µA @ 25°C • Outputs Source/Sink 24 mA ORDERING INFORMATION IN74ACT175N Plastic IN74ACT175D SOIC TA = -40° to 85° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 16=VCC PIN 8 = GND Outputs Reset Clock D Q Q L X X L H H H H L H L L H H L X no change X = Don’t care 269 IN74ACT175 MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA IOUT DC Output Sink/Source Current, per Pin ±50 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TJ Junction Temperature (PDIP) TA Operating Temperature, All Package Types IOH Output Current - High IOL Output Current - Low tr, tf * Parameter Input Rise and Fall Time (except Schmitt Inputs) * Min Max Unit 4.5 5.5 V 0 VCC V 140 °C +85 °C -24 mA 24 mA 10 8.0 ns/V -40 VCC =4.5 V VCC =5.5 V 0 0 VIN from 0.8 V to 2.0 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 270 IN74ACT175 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limits V 25 °C -40°C to 85°C Unit VOUT=0.1 V or VCC-0.1 V 4.5 5.5 2.0 2.0 2.0 2.0 V Maximum Low Level Input Voltage VOUT=0.1 V or VCC-0.1 V 4.5 5.5 0.8 0.8 0.8 0.8 V Minimum High-Level Output Voltage IOUT ≤ -50 µA 4.5 5.5 4.4 5.4 4.4 5.4 V 4.5 5.5 3.86 4.86 3.76 4.76 4.5 5.5 0.1 0.1 0.1 0.1 VIN=VIH or VIL IOL=24 mA IOL=24 mA 4.5 5.5 0.36 0.36 0.44 0.44 ±0.1 ±1.0 µA Symbol Parameter VIH Minimum High-Level Input Voltage VIL VOH Test Conditions * VIN=VIH or VIL IOH=-24 mA IOH=-24 mA VOL Maximum Low-Level Output Voltage IOUT ≤ 50 µA V * IIN Maximum Input Leakage Current VIN=VCC or GND 5.5 ∆ICCT Additional Max. ICC/Input VIN=VCC - 2.1 V 5.5 1.5 mA IOLD +Minimum Dynamic Output Current VOLD=1.65 V Max 5.5 75 mA IOHD +Minimum Dynamic Output Current VOHD=3.85 V Min 5.5 -75 mA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND 5.5 80 µA 8.0 * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. 271 IN74ACT175 AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns) Guaranteed Limits Symbol Parameter 25 °C Min -40°C to 85°C Max Min Unit Max fmax Maximum Clock Frequency (Figure 1) 175 tPLH Propagation Delay, Clock to Q or Q (Figure 1) 2.0 10.0 1.5 11.0 ns tPHL Propagation Delay, Clock to Q or Q (Figure 1) 2.0 11.0 1.5 12.0 ns tPHL, tPLH Propagation Delay, Reset to Q or Q (Figure 2) 2.0 9.5 1.5 10.5 ns CIN Maximum Input Capacitance 145 4.5 MHz 4.5 pF Typical @25°C,VCC=5.0 V CPD Power Dissipation Capacitance 45 pF TIMING REQUIREMENTS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns) Guaranteed Limits Symbol Parameter 25 °C -40°C to 85°C Unit tsu (H) (L) Minimum Setup Time, Data to Clock (Figure 3) 2.0 2.5 2.0 2.5 ns th Minimum Hold Time, Clock to Data (Figure 3) 1.0 1.0 ns tw Minimum Pulse Width, Reset (Figure 2) 3.0 4.0 ns tw Minimum Pulse Width, Clock (Figure 1) 3.0 3.5 ns trec Minimum Recovery Time, Reset to Clock (Figure 2) 0 0 ns 272 IN74ACT175 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms EXPANDED LOGIC DIAGRAM 273