INTEGRAL IN74ACT240DW

IN74ACT240
OCTAL 3-STATE INVERTING BUFFER/LINE
DRIVER/LINE RECEIVER
High-Speed Silicon-Gate CMOS
•
•
•
•
The IN74ACT240 is identical in pinout to the LS/ALS240,
HC/HCT240. The IN74ACT240 may be used as a level converter
for interfacing TTL or NMOS outputs to High Speed CMOS
inputs.
This octal inverting buffer/line driver/line receiver is designed
to be used with 3-state memory address drivers, clock drivers,
and other bus-oriented systems. The device has inverting
outputs and two active-low output enables.
• TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
Outputs Source/Sink 24 mA
LOGIC DIAGRAM
ORDERING INFORMATION
IN74ACT240N Plastic
IN74ACT240DW SOIC
TA = -40° to 85° C for all
packages
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Enable A,
A,B
Enable B
L
L
L
H
H
X
X = don’t care
Z = high impedance
PIN 20=VCC
PIN 10 = GND
1
Outputs
YA,YB
H
L
Z
IN74ACT240
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
VOUT
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
mA
±20
IOUT
DC Output Sink/Source Current, per Pin
mA
±50
ICC
DC Supply Current, VCC and GND Pins
mA
±50
PD
Power Dissipation in Still Air, Plastic DIP+
750
mW
SOIC Package+
500
Tstg
Storage Temperature
-65 to +150
°C
260
TL
Lead Temperature, 1 mm from Case for 10
°C
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage (Referenced to GND)
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to
GND)
TJ
Junction Temperature (PDIP)
TA
Operating Temperature, All Package Types
IOH
Output Current - High
IOL
Output Current - Low
t r, tf
Input Rise and Fall Time * VCC =4.5 V
VCC =5.5 V
(except Schmitt Inputs)
*
VIN from 0.8 V to 2.0 V
Min
4.5
0
-40
0
0
Max
5.5
VCC
Unit
V
V
140
+85
-24
24
10
8.0
°C
°C
mA
mA
ns/V
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and
VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
VCC). Unused outputs must be left open.
2
IN74ACT240
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
Guaranteed
VCC
Limits
Symbol
Parameter
Test Conditions
V
25 °C -40°C to
85°C
VIH
Minimum
High- VOUT=0.1 V
4.5
2.0
2.0
Level
Input
5.5
2.0
2.0
Voltage
VIL
Maximum Low - VOUT= VCC-0.1 V
4.5
0.8
0.8
Level
Input
5.5
0.8
0.8
Voltage
VOH
Minimum
High- IOUT ≤ -50 µA
4.5
4.4
4.4
Level
Output
5.5
5.4
5.4
Voltage
*
VIN= VIL
3.76
3.86
4.5
IOH=-24 mA
4.76
4.86
5.5
IOH=-24 mA
VOL
Maximum
Low- IOUT ≤ 50 µA
4.5
0.1
0.1
Level
Output
5.5
0.1
0.1
Voltage
*
VIN=VIH
0.44
0.36
4.5
IOL=24 mA
0.44
0.36
5.5
IOL=24 mA
IIN
Maximum Input VIN=VCC or GND
5.5
±0.1
±1.0
Leakage Current
5.5
IOZ
Maximum Three- VIN (OE)=VIL, VIH
±0.5
±5.0
State
Leakage VIN=VCC, GND
Current
VOUT=VCC, GND
5.5
1.5
Additional
Max
VIN=VCC - 2.1 V
∆ICCT
ICC/Input
VOLD=1.65 V Max
IOLD
+Minimum
5.5
75
Dynamic Output
Current
VOHD=3.85 V Min
IOHD
+Minimum
5.5
-75
Dynamic Output
Current
VIN=VCC or GND
ICC
Maximum
5.5
8.0
80
Quiescent Supply
Current
(per Package)
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
3
Unit
V
V
V
V
µA
µA
mA
mA
mA
µA
IN74ACT240
AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
Unit
Symbol
Parameter
25 °C
-40°C to
85°C
Min Max Min Max
tPLH
Propagation Delay, A to YA or B to YB 1.5
8.5
1.5
9.5
ns
(Figure 1)
tPHL
Propagation Delay, A to YA or B to YB 1.5
7.5
1.5
8.5
ns
(Figure 1)
tPZH
Propagation Delay, Output Enable to YA 1.5
8.5
1.0
9.5
ns
or YB (Figure 2)
tPZL
Propagation Delay, Output Enable to YA 2.0
9.5
1.5 10.5
ns
or YB (Figure 2)
tPHZ
Propagation Delay, Output Enable to YA 2.0
9.5
2.0 10.5
ns
or YB (Figure 2)
tPLZ
Propagation Delay, Output Enable to YA 2.5 10.0 2.0 10.5
ns
or YB (Figure 2)
CIN
Maximum Input Capacitance
4.5
4.5
pF
CPD
Typical @25°C,VCC=5.0
V
45
Power Dissipation Capacitance
Figure 1. Switching Waveforms
pF
Figure 2. Switching Waveforms
4