IN74HCT109 DUAL J-K FLIP-FLOP WITH SET AND RESET High-Performance Silicon-Gate CMOS The IN74HCT109 is identical in pinout to the LS/ALS109. The IN74HCT109 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two J- K flip-flops with individual set, reset, and clock inputs. Changes at the inputs are reflected at the outputs with the next low-to-high transition of the clock. Both Q to Q outputs are available from each flip-flop. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION IN74HCT109N Plastic IN74HCT109D SOIC TA = -55° to 125° C for all packages. PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE PIN 16=VCC PIN 8 = GND Set Reset L H L H H H H L L H H H H H H H Inputs Clock X X X L J K X X X L H L X X X L L H H X H X Output Q Q H L L H H* H* L H Toggle No Change H L No Change X = Don’t care * Both outputs will remain high as long as Set and Reset are low., but the output states are unpredictable if Set and Reset go high simultaneously. 1 IN74HCT109 MAXIMUM RATINGS* Symb Parameter Value Unit ol VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA ±20 IOUT DC Output Current, per Pin mA ±25 ICC DC Supply Current, VCC and GND Pins mA ±50 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 °C 260 TL Lead Temperature, 1 mm from Case for 10 °C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond witch damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types t r, tf Input Rise and Fall Time (Figure 1) 2 Min 4.5 0 Max 5.5 VCC Unit V V -55 0 +125 500 °C ns IN74HCT109 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Unit Symb Parameter Test Conditions V ≤85 ≤125 25 °C ol to °C °C -55°C VOUT=0.1 V or VCC-0.1 V VIH Minimum 4.5 2.0 2.0 2.0 V High-Level 5.5 2.0 2.0 2.0 IOUT≤ 20 µA Input Voltage VOUT=0.1 V or VCC-0.1 V VIL Maximum 4.5 0.8 0.8 0.8 V Low -Level 5.5 0.8 0.8 0.8 IOUT ≤ 20 µA Input Voltage VIN=VIH or VIL VOH Minimum 4.5 4.4 4.4 4.4 V High-Level 5.5 5.4 5.4 5.4 IOUT ≤ 20 µA Output Voltage VIN=VIH or VIL 4.5 3.98 3.84 3.7 IOUT ≤ 4.0 mA VIN= VIL or VIH VOL Maximum 4.5 0.1 0.1 0.1 V Low-Level 5.5 0.1 0.1 0.1 IOUT ≤ 20 µA Output Voltage VIN= VIL or VIH 4.5 0.26 0.33 0.4 IOUT ≤4.0 mA VIN=VCC or GND IIN Maximum 5.5 ±0.1 ±1.0 ±1.0 µA Input Leakage Current VIN=VCC or GND ICC Maximum 5.5 4.0 40 80 µA Quiescent IOUT=0µA Supply Current (per Package) Additional VIN = 2.4 V, Any One Input ≥-55°C 25°C to 125°C µA ∆ICC Quiescent VIN=VCC or GND, Other Inputs 5.5 2.9 2.4 Supply IOUT=0µA Current This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 3 IN74HCT109 AC ELECTRICAL CHARACTERISTICS(VCC=5.5 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Unit Symbol Parameter ≤85 ≤125 25 °C to °C °C -55°C fmax Maximum Clock Frequency (50% Duty 30 24 20 MHz Cycle) (Figures 1 and 4) 35 44 53 ns tPLH, Maximum Propagation Delay, Clock to Q tPHL or Q (Figures 1 and 4) 46 58 69 ns tPHL Maximum Propagation Delay , Set or Reset to Q or Q (Figures 2 and 4) tTLH, tTHL Maximum Output Transition Time, Any 15 19 22 ns Output (Figures 1 and 4) CIN Maximum Input Capacitance 10 10 10 pF CPD Power Dissipation Capacitance (Per FlipFlop) Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC+∆ICCVCC Typical @25°C,VCC=5.0 V 60 TIMING REQUIREMENTS (VCC=5.5 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Symbol Parameter 25 °C to ≤85°C ≤125°C -55°C tSU Minimum Setup Time, J 20 25 30 or K to Clock (Figure 3) th Minimum Hold Time, 5 5 5 Clock to J or K (Figure 3) 5 5 5 trec Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2) tw Minimum Pulse Width, 16 20 24 Set or Reset (Figure 2) tw Minimum Pulse 16 20 24 Width,Clock (Figure 1) tr, tf Maximum Input Rise and 500 500 500 Fall Times (Figure 1) 4 pF Unit ns ns ns ns ns ns IN74HCT109 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms EXPANDED LOGIC DIAGRAM 5