TECHNICAL DATA IN74HCT573A Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS The IN74HCT573A is identical in pinout to the LS/ALS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the highimpedance state. Thus, data may be latched even when the outputs are not enabled. • TTL/NMOS-Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION IN74HCT573AN Plastic IN74HCT573ADW SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 20=VCC PIN 10 = GND Output Enable Latch Enable D Q L H H H L H L L L L X no change H X X Z X = don’t care Z = high impedance 408 Output IN74HCT573A MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) Min Max Unit 4.5 5.5 V 0 VCC V -55 +125 °C 0 500 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 409 IN74HCT573A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC V 25 °C to -55°C ≤85 °C ≤125 °C Unit VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V Maximum Low Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V VIN=VIH or VIL IOUT ≤ 6.0 mA 4.5 3.98 3.84 3.7 VIN= VIL or VIH IOUT ≤ 20 µA 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 VIN= VIL or VIH IOUT ≤ 6.0 mA 4.5 0.26 0.33 0.4 Symbol Parameter VIH Minimum High-Level Input Voltage VIL VOH VOL Guaranteed Limit Maximum Low-Level Output Voltage Test Conditions V IIN Maximum Input Leakage Current VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA IOZ Maximum Three State Leakage Current Output in High-Impedance State VIN =VIH or VIL VOUT=VCC or GND 5.5 ±0.5 ±5.0 ±10 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 5.5 4.0 40 160 µA ∆ICC Additional Quiescent Supply Current VIN=2.4 V, Any One Input VIN=VCC or GND, Other Inputs ≥-55°C 25°C to 125°C mA 2.9 2.4 IOUT=0µA 410 5.5 IN74HCT573A AC ELECTRICAL CHARACTERISTICS(VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Symbol Parameter 25 °C to -55°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input D to Q (Figures 1 and 5) 30 38 45 ns tPLH, tPHL Maximum Propagation Delay,Latch Enable to Q (Figures 2 and 5) 30 38 45 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 28 35 42 ns tPZH, tPZL Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 28 35 42 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 5) 12 15 18 ns Maximum Input Capacitance 10 10 10 pF Maximum Three-State Output Capacitance (Output in High-Impedance State) 15 15 15 pF CIN COUT CPD Power Dissipation Capacitance (Per Enabled Output) Typical @25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 48 pF TIMING REQUIREMENTS (VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Symbol Parameter 25 °C to -55°C ≤85°C ≤125°C Unit tSU Minimum Setup Time, Input D to Latch Enable (Figure 4) 10 13 15 ns th Minimum Hold Time, Latch Enable to Input D (Figure 4) 5 5 5 ns tw Minimum Pulse Width, Latch Enable (Figure 2) 15 19 22 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 500 500 500 ns 411 IN74HCT573A Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms EXPANDED LOGIC DIAGRAM Figure 5. Test Circuit Figure 6. Test Circuit 412