TECHNICAL DATA IW4015B Dual 4-Stage Static Shift Register High-Voltage Silicon-Gate CMOS The IW4015B consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one IW4015B package, or to more than 8 stages using additional IW4015B’s is possible. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION IW4015BN Plastic IW4015BD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Clock PIN 16=VCC PIN 8= GND X Outputs Data Reset Q1 Qn L L L Qn-1 H L H Qn-1 X L X H X = don’t care 24 No change L L IW4015B MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +20 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT IIN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW -65 to +150 °C 260 °C Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 25 IW4015B DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC V ≥-55°C 25°C ≤125 °C Unit VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V VIL Maximum Low -Level VOUT= 0.5 V or VCC - 0.5V Input Voltage VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V VOH Minimum High-Level Output Voltage VIN=GND or VCC 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage VIN=GND or VCC 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V IIN Maximum Input Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 µA IOL Minimum Output Low VIN= GND or VCC (Sink) Current UOL=0.4 V UOL=0.5 V UOL=1.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 Minimum Output VIN= GND or VCC High (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 5.0 10 15 -2 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 Symbol Parameter VIH Minimum High-Level Input Voltage IOH 26 Guaranteed Limit Test Conditions mA mA IW4015B AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200kΩ, Input tr=tf=20 ns) Guaranteed Limit VCC V ≥-55°C 25°C ≤125°C Unit Maximum Clock Frequency (Figure 1) 5.0 10 15 3 6 8.5 3 6 8.5 1.5 3 4.25 MHz tPHL, tPLH Maximum Propagation Delay, Clock to Q (Figure 1) 5.0 10 15 320 160 120 320 160 120 640 320 240 ns tPHL Maximum Propagation Delay, Reset to Q (Figure 2) 5.0 10 15 400 200 160 400 200 160 800 400 320 ns Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns Symbol tmax tTHL, tTLH CIN Parameter Maximum Input Capacitance - 7.5 pF TIMING REQUIREMENTS(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns) Guaranteed Limit VCC Symbol Parameter V ≥-55°C 25°C ≤125°C Unit tw Minimum Pulse Width, Clock (Figure 1) 5.0 10 15 180 80 50 180 80 50 360 160 100 ns tw Minimum Pulse Width, Reset (Figure 2) 5.0 10 15 200 80 60 200 80 60 400 160 120 ns tsu Minimum Setup Time, Data to Clock (Figure 3) 5.0 10 15 70 40 30 70 40 30 140 80 60 ns th Minimum Hold Time, Clock to Data (Figure 3) 5.0 10 15 0 0 0 0 0 0 0 0 0 ns Maximum Input Rise and Fall Time (Figure 1) 5.0 10 15 15 6 2 15 6 2 30 12 4 µs tr, tf 27 IW4015B Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms EXPANDED LOGIC DIAGRAM ( 1/2 of the Device) 28