INTEL 87C196KT

87C196KT/87C196KS
ADVANCED 16-BIT CHMOS MICROCONTROLLER
Automotive
( b 40§ Cto a 125§ C Ambient)
Y
High Performance CHMOS 16-Bit CPU
Y
Up to 32 Kbytes of On-Chip EPROM
Y
Up to 1 Kbyte of On-Chip Register RAM
Y
Up to 512 Bytes of Additional RAM
(Code RAM)
Y
Register-Register Architecture
Y
8 Channel/10-Bit A/D with Sample/Hold
Y
37 Prioritized Interrupt Sources
Y
Up to Seven 8-Bit (56) I/O Ports
Y
Full Duplex Serial I/O Port
Y
Dedicated Baud Rate Generator
Y
Interprocessor Communication Slave
Port
Y
Selectable Bus Timing Modes for
Flexible Interfacing
Y
Y
High Speed Peripheral Transaction
Server (PTS)
Y
Two Dedicated 16-Bit High-Speed
Compare Registers
Y
10 High Speed Capture/Compare (EPA)
Y
Full Duplex Synchronous Serial I/O
Port (SSIO)
Y
Two Flexible 16-Bit Timer/Counters
Y
Quadrature Counting Inputs
Y
Flexible 8-/16-Bit External Bus
(Programmable)
Y
Programmable Bus (HLD/HLDA)
Y
1.75 ms 16 x 16 Multiply
Y
3 ms 32/16 Divide
Y
68-Pin PLCC Package
Oscillator Fail Detection Circuitry
The 87C196Kx devices represents the 4th generation of MCSÉ 96 microcontroller products implemented on
Intel’s advanced 1 micron process technology. These products are based on the 80C196KB device with
enhancements ideal for automotive applications. The instruction set is a true super set of the 80C196KB with a
few new instructions.
The MCS 96 microcontroller family members are all high performance microcontrollers with a 16-bit CPU. The
87C196KT is composed of the high speed (16 MHz) KX macrocore as well as the following peripherals: Up to
32 Kbytes of Program EPROM, up to 1 Kbytes of Register RAM (00-3FFH including SFRs), up to 512 bytes of
code RAM (16-bit addressing modes) with the ability to execute from this RAM space, an eight channel-10 Bit
g 3LSB analog to digital converter with programmable S/H times with conversion times k 20 ms at 16 MHz, an
asynchronous/synchronous serial I/O port (8096 compatable) with a dedicated 16-bit baud rate generator, an
additional synchronous serial I/O port with full duplex master/slave transceivers, a flexible timer/counter
structure with prescaler, cascading, and quadrature capabilities, 10 modularized multiplexed high speed I/O
for capture and compare (called Event Processor Array) with 250 ns resolution and double buffered inputs,
and a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS). The
PTS has several channel modes, including single/burst block transfers from any memory location to any
memory location, a PWM and PWM toggle mode to be used in conjunction with the EPA, and an A/D scan
mode.
Additional SFR space is allocated for the EPA and can be ‘‘windowed’’ into the lower Register RAM area.
NOTICE:
This datasheet contains information on products in production. The specifications are subject to change
without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a
design.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
November 1995
COPYRIGHT © INTEL CORPORATION, 1995
Order Number: 270999-007
1
87C196KT/87C196KS
Device
Pins/Package
EPROM
Reg RAM
Code RAM
I/O
EPA
SIO
SSIO
A/D
87C196KT
68-Pin PLCC
32K
1K
512b
56
10
Y
Y
8
87C196KS
68-Pin PLCC
24K
1K
256b
56
10
Y
Y
8
NOTE:
This is a PRODUCT PREVIEW DATA SHEET. The AC and DC parameters contained within this data sheet may change
after full automotive temperature characterization of the device has been performed. Contact your local sales office before
finalizing the Timing and D.C. characteristics of a design to verify you have the latest information.
ARCHITECTURE
NEW INSTRUCTIONS
The KT/KS are new members of the MCS-96 family
having the same architecture and use the same instruction set as the 80C196KB. Many new features
have been added including:
XCH/XCHB Exchange the contents of two locations, either Word or Byte is supported.
CPU FEATURES
BMOVI
Interruptable Block Move Instruction,
allows the user to be interrupted during long executing Block Moves.
TIJMP
Table Indirect JUMP. This instruction
incorportes a way to do complex
CASE level branches through one instruction. An example of such code
savings: several interrupt sources and
only one interrupt vector. The TIJMP
instruction will sort through the sources and branch to the appropriate subcode level in one instruction. This instruction was added especially for the
EPA structure, but has other code saving advantages.
EPTS/DPTS Enable and Disable Interrupts (Works
like EI and DI).
Y
Powerdown and Idle Modes
Y
16 MHz Operating Frequency
Y
A High Performance Peripheral
Transaction Server (PTS)
Y
37 Interrupt Vectors
Y
Up to 512 Bytes of Additional Code
RAM
Y
Up to 1 Kbyte of Additional Register
RAM
Y
‘‘Windowing’’ Allows 8-Bit Addressing
to some 16-Bit Addresses
Y
1.75 ms 16 x 16 Multiply
SFR OPERATION
Y
3 ms 32/16 Divide
Y
Oscillator Fail Detect Circuitry
A total of 1 Kbyte of Register RAM is implemented
on the 87C196KT/KS devices. These locations support the on-chip peripherals that the 87C196KT/KS
has (SFR’s), as well as offering a data storage area.
These locations are all 8-bit directly addressable by
use of the windowing technique. Any 32-, 64- or 128byte section can be relocated into the upper 32-, 64or 128-byte area of the Register RAM area 080H –
0FFH.
PERIPHERAL FEATURES
Ð Programmable A/D Conversion and S/H Times
Ð 10 Capture/Compare I/O with 2 Flexible Timers
(250 ns Resolution and Double Buffered Inputs)
Ð Synchronous Serial I/O Port for Full Duplex Serial I/O
Ð Synchronous/Asynchronous Serial I/O Port
(with Dedicated 16-Bit Baud Rate Generator)
Ð Total Utilization of ALL Available Pins (I/O Mux’d
with Control)
Ð (2) 16-Bit Timers with Prescale, Cascading, and
Quadrature Counting Capabilities
Ð Up to 12 Externally Triggered Interrupts
2
2
87C196KT/87C196KS
87C196KT Block Diagram
270999 – 1
270999 – 2
3
3
87C196KT/87C196KS
PIN DESCRIPTIONS
Symbol
Name and Function
VCC
Main supply voltage ( a 5V).
VSS, VSSI, VSSI
Digital circuit ground (0V). There are three VSS pins, all of which MUST be connected.
VREF
Reference for the A/D converter ( a 5V). VREF is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for
A/D and Port 0 to function.
VPP
Programming voltage for the EPROM parts. It should be a 12.5V for programming. It
is also the timing pin for the return from powerdown circuit. Connect this pin with a
1 mF capacitor to VSS and a 1 MX resistor to VCC. If this function is not used, VPP
may be tied to VCC.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same
potential as VSS.
XTAL1
Input of the oscillator inverter and the internal clock generator.
XTAL2
Output of the oscillator inverter.
P2.7/CLKOUT
Output of the internal clock generator. The frequency is (/2 the oscillator frequency. It
has a 50% duty cycle. Also LSIO pin.
RESET
Reset input to the chip. Input low for at least 16 state times will reset the chip. The
subsequent low to high transition resynchronizes CLKOUT and commences a 10state time sequence in which the PSW is cleared, bytes are read from 2018H and
201AH loading the CCBs, and a jump to location 2080H is executed. Input high for
normal operation. RESET has an internal pullup.
P5.7/BUSWIDTH
Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin
dyamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low, an
8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is ‘‘0’’ and
CCR1 bit 2 is ‘‘1’’, all bus cycles are 8-bit, if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is ‘‘0’’, all
bus cycles are 16-bit. CCR bit 1 e ‘‘0’’ and CCR1 bit 2 e ‘‘0’’ is illegal. Also an LSIO
pin when not used as BUSWIDTH.
NMI
A positive transition causes a non maskable interrupt vector through memory location
203EH.
P5.1/INST
Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle. INST is active only during external memory
fetches, during internal EPROM fetches INST is held low. Also LSIO when not INST.
EA
Input for memory select (External Access). EA equal to a high causes memory
accesses to locations 2000H through 9FFFH to be directed to on-chip EPROM/ROM.
EA equal to a low causes accesses to these locations to be directed to off-chip
memory. EA e a 12.5V causes execution to begin in the Programming Mode. EA is
latched at reset.
P5.0/ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive (high) at the end of the bus cycle. ADV can be used as a chip
select for external memory. ALE/ADV is active only during external memory
accesses. Also LSIO when not used as ALE.
P5.3/RD
Read signal output to external memory. RD is active only during external memory
reads or LSIO when not used as RD.
P5.2/WR/WRL
Write and Write Low output to external memory, as selected by the CCR, WR will go
low for every external write, while WRL will go low only for external writes where an
even byte is being written. WR/WRL is active during external memory writes. Also an
LSIO pin when not used as WR/WRL.
4
4
87C196KT/87C196KS
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
P5.5/BHE/WRH
Byte High Enable or Write High output, as selected by the CCR. BHE e 0 selects the
bank of memory that is connected to the high byte of the data bus. A0 e 0 selects
that bank of memory that is connected to the low byte. Thus accesses to a 16-bit
wide memory can be to the low byte only (A0 e 0, BHE e 1), to the high byte only
(A0 e 1, BHE e 0) or both bytes (A0 e 0, BHE e 0). If the WRH function is selected,
the pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is
only valid during 16-bit external memory write cycles. Also an LSIO pin when not
BHE/WRH.
P5.6/READY
Ready input to lengthen external memory cycles, for interfacing with slow or
dynamic memory, or for bus sharing. If the pin is high, CPU operation continues in a
normal manner. If the pin is low prior to the falling edge of CLKOUT, the memory
controller goes into a wait state mode until the next positive transition in CLKOUT
occurs with READY high. When external memory is not used, READY has no effect.
The max number of wait states inserted into the bus cycle is controlled by the CCR/
CCR1. Also an LSIO pin when READY is not selected.
P5.4/SLPINT
Dual function I/O pin. As a bidirectional port pin or as a system function. The system
function is a Slave Port Interrupt Output Pin.
P6.2/T1CLK
Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it
may also be used as a TIMER1 Clock input. The TIMER1 will increment or
decrement on both positive and negative edges of this pin.
P6.3/T1DIR
Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it
may also be used as a TIMER1 Direction input. The TIMER1 will increment when
this pin is high and decrements when this pin is low.
PORT1/EPA0–7
P6.0–6.1/EPA8–9
Dual function I/O port pins. Primary function is that of bidirectional I/O. System
function is that of High Speed capture and compare. EPA0 and EPA2 have yet
another function of T2CLK and T2DIR of the TIMER2 timer/counter.
PORT 0/ACH0–7
8-bit high impedance input-only port. These pins can be used as digital inputs and/or
as analog inputs to the on-chip A/D converter. These pins are also used as inputs to
EPROM parts to select the Programming Mode.
P6.3–6.7/SSIO
Dual function I/O ports that have a system function as Synchronous Serial I/O. Two
pins are clocks and two pins are data, providing full duplex capability.
PORT 2
8-bit multi-functional port. All of its pins are shared with other functions.
PORT 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
5
5
87C196KT/87C196KS
(2018H : Byte)
CCB
CCB1 (201AH : Byte)
0
PD
e
‘‘1’’ Enables Powerdown
0
0
e
Reserved Must Be ‘‘0’’
1
BW0
e
See Table
1
IRC2
e
See Table
2
WR
e
‘‘1’’ e WR/BHE - ‘‘0’’ e WRL/WRH
2
BW1
e
See Table
3
ALE
e
‘‘1’’ e ALE - ‘‘0’’ e ADV
3
WDE
e
‘‘0’’ e Always Enabled
4
IRC0
e
1
e
5
IRC1
e
( See Table
4
5
0
e
( Reserved Must Be ‘‘01’’
6
LOC0
e
MSEL0
e
LOC1
e
( See Table
6
7
7
MSEL1
e
( See Table
LOC1
LOC0
Function
IRC2
IRC1
IRC0
Max Wait States
0
0
1
1
0
1
0
1
Read and Write Protected
Write Protected Only
Read Protected Only
No Protection
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
Zero Wait States
1 Wait State
2 Wait States
3 Wait States
INFINITE
MSEL1
MSEL0
Bus Timing Mode
BW1
BW0
Bus Width
0
0
1
1
0
1
0
1
Mode 0 (1-Wait KR)
Mode 1
Mode 2
Mode 3 (KR)
0
0
1
1
0
1
0
1
ILLEGAL
16-Bit Only
8-Bit Only
BW Pin Controlled
Mode 0
(1-Wait KR):
Designed to be similar to the 87C196KR bus
timing with 1 automatic wait state.
See AC Timings section for actual timings data.
Mode 1:
RD, WR, advanced 1 TOSC
ALE advanced 0.5 TOSC
ALE pulse width remains 1 TOSC
Mode 2:
RD, WR, advanced 1 TOSC
ALE advanced 0.5 TOSC
ALE pulse width remains 1 TOSC
Address advanced 0.5 TOSC
Mode 3 (KR): Designed to be similar to the 87C196KR bus
timing.
See AC Timings section for actual timings data.
6
6
87C196KT/87C196KS
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 60§ C to a 150§ C
Voltage from VPP or EA to
VSS or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 0.5V to a 13.0V
Voltage from Any Other Pin
to VSS or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 0.5 to a 7.0V
This includes VPP on ROM and CPU devices .
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.5W
OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Units
TA
Ambient Temperature Under Bias
b 40
a 125
§C
VCC
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V
FOSC
Oscillator Frequency
4
16
MHz (Note 4)
NOTE:
ANGND and VSS should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
(Under Listed Operating Conditions)
Parameter
Max
Units
XTAL1 e 16 MHz,
VCC e VPP e VREF e 5.5V
(While device in Reset)
82
mA
5
mA
Idle Mode Current
XTAL1 e 16 MHz,
VCC e VPP e VREF e 5.5V
40
mA
IPD
Powerdown Mode Current
VCC e VPP e VREF e 5.5V(6, 9)
TBD
mA
VIL
Input Low Voltage (all pins)
For PORT0(8)
b 0.5V
0.3 VCC
V
VIH
Input High Voltage
For PORT0(8)
0.7 VCC
VCC a 0.5
V
VIH1
Input High Voltage XTAL1
XTAL1 Input Pin Only(1)
0.7 VCC
VCC a 0.5
V
VIH2
Input High Voltage on RESET
RESET input pin only
0.7 VCC
VCC a 0.5
V
ICC
VCC Supply Current
( b 40§ C to a 125§ C Ambient)
IREF
A/D Reference Supply Current
IIDLE
Test Conditions
Min
Typ
50
7
7
87C196KT/87C196KS
DC CHARACTERISTICS
Symbol
VOL
(Under Listed Operating Conditions) (Continued)
Parameter
Test Conditions
Min
Typ
IOL e 200 mA(3,5)
Max
Units
0.3
0.45
1.5
V
V
V
Output Low Voltage
(Outputs Configured as
Complementary)
IOL e 3.2 mA
IOL e 7.0 mA
VOH
Output High Voltage
(Outputs Configured as
Complementary)
IOH e b 200 mA(3,5)
IOH e b 3.2 mA
IOH e b 7.0 mA
ILI
Input Leakage Current (Std. Inputs)
VSS k VIN k VCC
g 10
mA
ILI1
Input Leakage Current (Port 0)
VSS k VIN k VREF
g 1.5
mA
VOH1
SLPINT (P5.4) and HLDA (P2.6)
Output High Voltage in RESET
IOH e 0.8 mA(7)
VOH2
Output High Voltage in RESET
IOH e b 15 mA(1,8)
IOH2
Output High Current in RESET
VOH2 e VCC b 1.0V
VOH2 e VCC b 2.5V
VOH2 e VCC b 4.0V
CS
Pin Capacitance (Any pin to VSS)
VOL3
VCC b 0.3
VCC b 0.7
VCC b 1.5
V
V
V
2.0
V
VCC b 1V
V
b 30
b 75
b 90
b 120
b 240
b 280
mA
mA
mA
ftest e 1.0 MHz(6)
10
pF
Output Low Voltage in RESET
(RESET Pin Only)
IOL3 e 4 mA(10)
IOL3 e 6 mA
IOL3 e 8 mA
0.3
0.5
0.8
V
RWPU
Weak Pullup Resistance
(Note 6)
RRST
Reset Pullup Resistor
150K
65K
X
180K
X
NOTES:
1. All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to their not being weakly
pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5 and Port6 except SPLINT (P5.4) and HLDA (P2.6).
2. Standard input pins include XTAL1, EA, RESET, and Port 1/2/5/6 when setup as inputs.
3. All bidirectional I/O pins when configured as Outputs (Push/Pull).
4. Device is static and should operate below 1 Hz, but only tested down to 4 MHz.
5. Maximum IOL/IOH currents per pin will be characterized and published at a later date.
6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
VREF e VCC e 5.0V.
7. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6).
8. When P0 is used as analog inputs, refer to A/D specifications for this characteristic.
9. For temperatures k100§ C typical is 10 mA.
10. This specification is not tested in production and is based upon theoretical estimates and/or product characterization.
ICC vs Frequency
270999 – 24
NOTES:
ICC Max e 3.25 c Freq a 30
IIDLE Max e 1.25 c Freq a 20
8
8
87C196KT/87C196KS
AC CHARACTERISTICS
(Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns.
The 87C196KT will meet these specifications
Symbol
Parameter
Min
Max
Units
FXTAL
Frequency on XTAL1
4.0
16.0
MHz(1)
TOSC
XTAL1 Period (1/FXTAL)
62.5
250
ns
TXHCH
XTAL1 High to CLKOUT High or Low
a 20
110
ns
TOFD
Clock Failure to Reset Pulled Low(6)
4
40
ms
TCLCL
CLKOUT Period
TCHCL
CLKOUT High Period
TOSC b 10
TOSC a 30
ns
TCLLH
CLKOUT Low to ALE/ADV High
b 10
a 15
ns
TLLCH
ALE/ADV Low to CLKOUT High
b 25
a 15
ns
TLHLH
ALE/ADV Cycle Time
TLHLL
ALE/ADV High Time
TOSC b 10
TAVLL
Address Valid to ALE Low
TOSC b 15
ns
TLLAX
Address Hold After ALE/ADV Low
TOSC b 40
ns
TLLRL
ALE/ADV Low to RD Low
TOSC b 40
TRLCL
RD Low to CLKOUT Low
b5
TRLRH
RD Low Period
TRHLH
RD High to ALE/ADV High
2 TOSC
ns
ns(5)
4 TOSC
TOSC a 10
ns
a 35
ns
ns(5)
TOSC b 5
TOSC
ns
TOSC a 25
ns(3)
a5
ns
TRLAZ
RD Low to Address Float
TLLWL
ALE/ADV Low to WR Low
TOSC b 10
TCLWL
CLKOUT Low to WR Low
b 10
TQVWH
Data Valid before WR High
TOSC b 23
TCHWH
CLKOUT High to WR High
b 10
TWLWH
WR Low Period
TOSC b 30
TWHQX
Data Hold after WR High
TOSC b 30
TWHLH
WR High to ALE/ADV High
TOSC b 10
TWHBX
BHE, INST Hold after WR High
TOSC b 10
ns
TWHAX
AD8–15 Hold after WR High
TOSC b 30
ns(4)
TRHBX
BHE, INST Hold after RD High
TOSC b 10
ns
TRHAX
AD8–15 Hold after RD High
TOSC b 30
ns(4)
ns
a 25
ns
ns
a 15
ns
ns(5)
ns
TOSC a 15
ns(3)
NOTES:
1. Testing performed at 4.0 MHz, however, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
5. If wait states are used, add 2 Tosc c n, where n e number of wait states. If mode 0 (1 automatic wait state added)
operation is selected, add 2 TOSC to specification.
6. TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by
programming the UPROM location 0778H with the value 0004H. KT/KS customer QROM codes need to equate location
2016H to the value 0CDEH if the oscillator fail detect (OFD) function is desired. Intel manufacturing uses location 2016H
as a flag to determine whether or not to program the Clock Detect Enable (CDE) bit. Programming the CDE bit
enables oscillator fail detection.
9
9
87C196KT/87C196KS
AC CHARACTERISTICS
(Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins e 100 pF, Rise anf Fall Times e 10 ns.
The system must meet these specifications to work with the 87C196KT.
Symbol
Parameter
TAVYV
Address Valid to Ready Setup
TLLYV
ALE Low to READY Setup
TYLYH
Non READY Time
TCLYX
READY Hold after CLKOUT Low
TAVGV
Address Valid to BUSWIDTH Setup
TLLGV
ALE Low to BUSWIDTH Setup
TCLGX
BUSWIDTH Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
TRLDV
Min
Max
Units
2 TOSC b 75
ns(3)
TOSC b 70
ns(3)
No Upper Limit
ns
TOSC b 30
ns(1)
2 TOSC b 75
ns(2, 3)
TOSC b 60
ns(2, 3)
3 TOSC b 55
ns(2)
RD active to input Data Valid
TOSC b 30
ns(2)
TCLDV
CLKOUT Low to Input Data Valid
TOSC b 60
ns
TRHDZ
End of RD to Input Data Float
TOSC
ns
TRHDX
Data Hold after RD High
0
0
0
ns
ns
NOTES:
1. If Max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 Tosc c n, where n e number of wait states.
3. If mode 0 is selected, one wait state minimum is always added. If additional wait states are required, add 2 Tosc to the
specification.
10
10
87C196KT/87C196KS
87C196KT SYSTEM BUS TIMING
270999 – 4
* If mode 0 operation is selected, add 2 Tosc to this time.
11
11
87C196KT/87C196KS
87C196KT READY TIMINGS (ONE WAIT STATE)
270999 – 5
*If mode 0 selected, one wait state is always added. If additional wait states are required, add 2 Tosc to these specifications.
87C196KT BUSWIDTH TIMINGS
270999 – 6
*If mode 0 selected, add 2 Tosc to these specifications.
12
12
87C196KT/87C196KS
HOLD/HOLDA TIMINGS
(Over Specified Operation Conditions)
Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns.
Symbol
Parameter
Min
Max
Units
ns(1)
THVCH
HOLD Setup Time
a 65
TCLHAL
CLKOUT Low to HLDA Low
b 15
a 15
ns
TCLBRL
CLKOUT Low to BREQ Low
b 15
a 15
ns
TAZHAL
HLDA Low to Address Float
a 20
ns
TBZHAL
HLDA Low to BHE, INST, RD, WR Weakly Driven
a 25
ns
TCLHAH
CLKOUT Low to HLDA High
b 25
a 15
ns
TCLBRH
CLKOUT Low to BREQ High
b 25
a 25
ns
THAHAX
HLDA High to Address No Longer Float
b 15
THAHBV
HLDA High to BHE, INST, RD, WR Valid
b 10
ns
a 15
ns
NOTE:
1. To guarantee recognition at next clock.
8XC196KT HOLD/HOLDA TIMINGS
270999 – 7
13
13
87C196KT/87C196KS
BUS MODE 1ÐAC CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns.
The 87C196KT will meet these specifications
Symbol
Parameter
Min
Max
Units
FXTAL
Frequency on XTAL1
8.0
16.0
MHz(1)
TOSC
XTAL1 Period (1/FXTAL)
62.5
125
ns
TXHCH
XTAL1 High to CLKOUT High or Low
a 20
110
ns
TCLCL
CLKOUT Period
TCHCL
CLKOUT High Period
TOSC b 10
TOSC a 27
ns
TCHLH
CLKOUT HIGH to ALE/ADV High
0.5 TOSC b 15
0.5 TOSC a 20
ns
TCLLL
CLKOUT LOW to ALE/ADV Low
0.5 TOSC b 25
0.5 TOSC a 15
TLHLH
ALE/ADV Cycle Time
TLHLL
ALE/ADV High Time
TAVLL
Address Valid to ALE Low
0.5 TOSC b 15
ns
TLLAX
Address Hold After ALE/ADV Low
0.5 TOSC b 20
ns
TLLRL
ALE/ADV Low to RD Low
0.5 TOSC b 30
TRLCL
RD Low to CLKOUT Low
TOSC b 10
TRLRH
RD Low Period
TRHLH
RD High to ALE/ADV High
TRLAZ
RD Low to Address Float
2 TOSC
ns
TOSC b 10
TOSC a 10
TLLWL
ALE/ADV Low to WR Low
0.5 TOSC b 10
TCLWL
CLKOUT Low to WR Low
TOSC b 15
TQVWH
Data Valid before WR High
2 TOSC b 23
TCHWH
CLKOUT High to WR High
b 10
ns
ns
TOSC a 30
ns
ns(5)
2 TOSC b 20
0.5 TOSC
ns
ns(5)
4 TOSC
0.5 TOSC a 25
ns(3)
a5
ns
ns
TOSC a 25
ns
ns
a 15
ns
ns(5)
2 TOSC b 15
TWLWH
WR Low Period
TWHQX
Data Hold after WR High
0.5 TOSC b 25
TWHLH
WR High to ALE/ADV High
0.5 TOSC b 10
TWHBX
BHE Hold after WR High
TOSC b 15
TWHIX
INST Hold after WR High
0.5 TOSC b 15
TWHAX
AD8–15 Hold after WR High
0.5 TOSC b 30
ns(4)
TOSC b 32
ns
TRHBX
BHE Hold after RD High
TRHAX
AD8–15 Hold after RD High
0.5 TOSC b 32
TRHAX
AD8–15 Hold after RD High
0.5 TOSC b 30
ns
0.5 TOSC a 15
ns(3)
ns
ns(4)
NOTES:
1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
5. If wait states are used, add 2 TOSC c n, where n e number of wait states.
14
14
87C196KT/87C196KS
BUS MODE 1ÐAC CHARACTERISTICS (Over Specified Operating Conditions) (Continued)
Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns.
The system must meet these specifications to work with the 87C196KT.
Symbol
Parameter
TAVYV
Address Valid to Ready Setup
TLLYV
ALE Low to READY Setup
TYLYH
Non READY Time
TCLYX
READY Hold after CLKOUT Low
TAVGV
Address Valid to BUSWIDTH Setup
TLLGV
ALE Low to BUSWIDTH Setup
TCLGX
BUSWIDTH Hold after CLKOUT Low
TAVDV
Min
Max
Units
2 TOSC b 75
ns
1.5 TOSC b 70
ns
No Upper Limit
0
ns
TOSC b 30
ns(1)
2 TOSC b 75
ns
1.5 TOSC b 60
ns
Address Valid to Input Data Valid
3 TOSC b 65
ns(2)
TRLDV
RD active to input Data Valid
2 TOSC b 44
ns(2)
TCLDV
CLKOUT Low to Input Data Valid
TOSC b 60
ns
TRHDZ
End of RD to Input Data Float
TRHDX
Data Hold after RD High
0
ns
TOSC
0
ns
ns
NOTES:
1. If Max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 TOSC c n, where n e number of wait states. If mode 0 (1 automatic wait state added)
operation is selected, add 2 TOSC to specification.
15
15
87C196KT/87C196KS
MODE 1Ð87C196KT SYSTEM BUS TIMING
270999 – 23
16
16
87C196KT/87C196KS
BUS MODE 1ÐHOLD/HOLDA TIMINGS
(Over Specified Operation Conditions)
Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns.
Symbol
Parameter
Min
Max
Units
ns(1)
THVCH
HOLD Setup Time
a 65
TCLHAL
CLKOUT Low to HLDA Low
b 15
a 15
ns
TCLBRL
CLKOUT Low to BREQ Low
b 15
a 15
ns
TAZHAL
HLDA Low to Address Float
a 25
ns
TBZHAL
HLDA Low to BHE, INST, RD, WR Weakly Driven
a 25
ns
TCLHAH
CLKOUT Low to HLDA High
b 25
a 15
ns
TCLBRH
CLKOUT Low to BREQ High
b 25
a 15
ns
THAHAX
HLDA High to Address No Longer Float
b 15
ns
THAHBV
HLDA High to BHE, INST, RD, WR Valid
b 10
ns
NOTE:
1. To guarantee recognition at next clock.
MODE 1Ð8XC196KT HOLD/HOLDA TIMINGS
270999 – 11
17
17
87C196KT/87C196KS
BUS MODE 2ÐAC CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns.
The 87C196KT will meet these specifications
Symbol
Parameter
Min
Max
Units
FXTAL
Frequency on XTAL1
8.0
16.0
MHz(1)
TOSC
XTAL1 Period (1/FXTAL)
62.5
125
ns
TXHCH
XTAL1 High to CLKOUT High or Low
a 20
a 85
ns
TCLCL
CLKOUT Period
TCHCL
CLKOUT High Period
TOSC b 10
TOSC a 27
ns
TCHLH
CLKOUT HIGH to ALE/ADV High
0.5 TOSC b 15
0.5 TOSC a 20
ns
TCLLL
CLKOUT LOW to ALE/ADV Low
0.5 TOSC b 25
0.5 TOSC a 15
TLHLH
ALE/ADV Cycle Time
TLHLL
ALE/ADV High Time
TOSC b 10
TAVLL
Address Valid to ALE Low
TOSC b 15
ns
TLLAX
Address Hold After ALE/ADV Low
0.5 TOSC b 20
ns
TLLRL
ALE/ADV Low to RD Low
0.5 TOSC b 30
TRLCL
RD Low to CLKOUT Low
TOSC b 10
TRLRH
RD Low Period
2 TOSC b 20
TRHLH
RD High to ALE/ADV High
0.5 TOSC b 5
TRLAZ
RD Low to Address Float
2 TOSC
ns
TLLWL
ALE/ADV Low to WR Low
0.5 TOSC b 10
TCLWL
CLKOUT Low to WR Low
TOSC b 22
TQVWH
Data Valid before WR High
2 TOSC b 25
TCHWH
CLKOUT High to WR High
b 10
ns
ns(5)
4 TOSC
TOSC a 10
ns
ns
TOSC a 30
ns
ns(5)
0.5 TOSC a 25
ns(3)
a5
ns
ns
TOSC a 25
ns
ns
a 15
ns
ns(5)
2 TOSC b 20
TWLWH
WR Low Period
TWHQX
Data Hold after WR High
0.5 TOSC b 25
TWHLH
WR High to ALE/ADV High
0.5 TOSC b 10
TWHBX
BHE Hold after WR High
TOSC b 15
TWHIX
INST Hold after WR High
0.5 TOSC b 15
TWHAX
AD8–15 Hold after WR High
0.5 TOSC b 30
ns(4)
ns
TRHBX
BHE Hold after RD High
TOSC b 32
TRHIX
INST Hold after RD High
0.5 TOSC b 32
TRHAX
AD8–15 Hold after RD High
0.5 TOSC b 30
ns
0.5 TOSC a 10
ns(3)
ns
ns(4)
NOTES:
1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
5. If wait states are used, add 2 TOSC c n, where n e number of wait states.
18
18
87C196KT/87C196KS
BUS MODE 2ÐAC CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns.
The system must meet these specifications to work with the 87C196KT.
Symbol
Parameter
Min
Max
Units
TAVYV
Address Valid to Ready Setup
2.5 TOSC b 75
ns
TLLYV
ALE Low to READY Setup
1.5 TOSC b 70
ns
TYLYH
Non READY Time
TCLYX
READY Hold after CLKOUT Low
TAVGV
TLLGV
TCLGX
BUSWIDTH Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
TRLDV
RD active to Input Data Valid
TCLDV
CLKOUT Low to Input Data Valid
TRHDZ
End of RD to Input Data Float
TRHDX
Data Hold after RD High
No Upper Limit
ns
TOSC b 30
ns(1)
Address Valid to BUSWIDTH Setup
2.5 TOSC b 75
ns
ALE Low to BUSWIDTH Setup
1.5 TOSC b 60
ns
3.5 TOSC b 60
ns(2)
2 TOSC b 44
ns(2)
TOSC b 60
ns
0
0
ns
0.5 TOSC
0
ns
ns
NOTES:
1. If Max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 TOSC c n, where n e number of wait states. If mode 0 (1 automatic wait state added)
operation is selected, add 2 TOSC to specification.
19
19
87C196KT/87C196KS
MODE 2Ð87C196KT SYSTEM BUS TIMING
270999 – 12
20
20
87C196KT/87C196KS
MODE 2Ð87C196KT READY TIMINGS (ONE WAIT STATE)
270999 – 13
MODE 2Ð87C196KT BUSWIDTH TIMINGS
270999 – 14
21
21
87C196KT/87C196KS
BUS MODE 2ÐHOLD/HOLDA TIMINGS
(Over Specified Operation Conditions)
Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns.
Symbol
Parameter
Min
Max
Units
ns(1)
THVCH
HOLD Setup Time
a 65
TCLHAL
CLKOUT Low to HLDA Low
b 15
a 15
ns
TCLBRL
CLKOUT Low to BREQ Low
b 15
a 15
ns
TAZHAL
HLDA Low to Address Float
a 25
ns
TBZHAL
HLDA Low to BHE, INST, RD, WR Weakly Driven
a 25
ns
TCLHAH
CLKOUT Low to HLDA High
b 25
a 15
ns
TCLBRH
CLKOUT Low to BREQ High
b 25
a 15
ns
THAHAX
HLDA High to Address No Longer Float
b 15
ns
THAHBV
HLDA High to BHE, INST, RD, WR Valid
b 10
ns
NOTE:
1. To guarantee recognition at next clock.
MODE 2Ð8XC196KT HOLD/HOLDA TIMINGS
270999 – 15
22
22
87C196KT/87C196KS
AC CHARACTERISTICSÐSLAVE PORT
SLAVE PORT WAVEFORMÐ(SLPL e 0)
270999 – 8
SLAVE PORT TIMINGÐ(SLPL e 0, 1, 2, 3)
Symbol
Parameter
Min
Max
Units
TSAVWL
Address Valid to WR Low
50
ns
TSRHAV
RD High to Address Valid
60
ns
TSRLRH
RD Low Period
TOSC
ns
TSWLWH
WR Low Period
TOSC
ns
TSRLDV
RD Low to Output Data Valid
TSDVWH
Input Data Setup to WR High
TSWHQX
WR High to Data Invalid
30
ns
TSRHDZ
RD High to Data Float
15
ns
60
20
ns
ns
NOTES:
1. Test Conditions: FOSC e 16 MHz, TOSC e 60 ns. Rise/Fall Time e 10 ns. Capacitive Pin Load e 100 pF.
2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests.
3. Specifications above are advanced information and are subject to change.
23
23
87C196KT/87C196KS
AC CHARACTERISTICSÐSLAVE PORT (Continued)
SLAVE PORT WAVEFORMÐ(SLPL e 1)
270999 – 9
SLAVE PORT TIMINGÐ(SLPL e 1, 2, 3)
Parameter
Min
TSELLL
Symbol
CS Low to ALE Low
20
Max
Units
ns
TSRHEH
RD or WR High to CS High
60
ns
TSLLRL
ALE Low to RD Low
TOSC
ns
TSRLRH
RD Low Period
TOSC
ns
TSWLWH
WR Low Period
TOSC
ns
TSAVLL
Address Valid to ALE Low
20
ns
TSLLAX
ALE Low to Address Invalid
20
ns
TSRLDV
RD Low to Output Data Valid
TSDVWH
Input Data Setup to WRHigh
20
ns
TSWHQX
WR High to Data Invalid
30
ns
TSRHDZ
RD High to Data Float
15
ns
60
ns
NOTES:
1. Test Conditions: FOSC e 16 MHz, TOSC e 60 ns. Rise/Fall Time e 10 ns. Capacitive Pin Load e 100 pF.
2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests.
3. Specifications above are advanced information and are subject to change.
24
24
87C196KT/87C196KS
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
1/TXLXL
Oscillator Frequency
TXLXL
Oscillator Period (TOSC)
TXHXX
TXLXX
TXLXH
TXHXL
Max
Units
4
16
MHz
62.5
250
ns
High Time
0.35 c TOSC
0.65 TOSC
ns
Low Time
0.35 c TOSC
0.65 TOSC
ns
Rise Time
10
ns
Fall Time
10
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270999 – 16
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
270999 – 18
270999 – 17
AC Testing inputs are driven at 3.5V for a logic ‘‘1’’ and
0.45V for a logic ‘‘0’’. Timing measurements are made
at 2.0V for a logic ‘‘1’’ and 0.8V for logic ‘‘0’’.
THERMAL CHARACTERISTICS
Device and Package
AN87C196KT/KS
(68-Lead PLCC)
For timing purposes a Port Pin is no longer floating
when a 150 mV change from load voltage occurs and
begins to float when a 150 mV change from the loading
VOH/VOL level occurs IOL/IOH s 15 mA.
EXPLANATION OF AC SYMBOLS
iJA
iJC
36.5§ C/W
13§ C/W
NOTES:
1. iJA e Thermal resistance between junction and the surrounding environmental (ambient). Measurements are taken 1 ft. away from case in air flow environment. iJC e
Thermal resistance between junction and package surface
(case).
2. All values of iJA and iJC may fluctuate depending on
the environment (with or without airflow, and how much airflow) and device power dissipation at temperature of operation. Typical variations are g 2§ C/W.
3. Values listed are at a maximum power dissipation of
0.50W.
Each symbol is two pairs of letters prefixed by ‘‘T’’
for time. The characters in a pair indicate a signal
and its condition, respectively. Symbols represent
the time between the two signal/condition points.
Conditions:
HÐHigh
LÐLow
VÐValid
XÐNo Longer
Valid
ZÐFloating
Signals:
AÐAddress
BÐBHE
BRÐBREQ
CÐCLKOUT
DÐDATA
GÐBuswidth
HÐHOLD
HAÐHLDA
LÐALE/ADV
QÐData Out
RDÐRD
WÐWR/WRH/WRI
XÐXTAL1
YÐREADY
25
25
87C196KT/87C196KS
EPROM SPECIFICATIONS
AC EPROM PROGRAMMING CHARACTERISTICS
Operating Conditions: Load Capacitance e 150 pF; TC e 25§ C g 5§ C, VCC, VREF e 5.0V g 0.5V, VSS,
ANGND e 0V.
VPP e 12.5V g 0.25V; EA e 12.5V g 0.25V; Fosc e 5.0 MHz.
Symbol
Paramter
Min
Max
Units
TAVLL
Address Setup Time
0
TOSC
TLLAX
Address Hold Time
100
TOSC
TDVPL
Data Setup Time
0
TOSC
TPLDX
Data Hold Time
400
TOSC
TLLLH
PALE Pulse Width
50
TOSC
TPLPH
PROG Pulse Width(2)
50
TOSC
TLHPL
PALE High to PROG Low
220
TOSC
TPHLL
PROG High to next PALE Low
220
TPHDX
Word Dump Hold Time
TPHPL
PROG High to next PROG Low
220
TOSC
TLHPL
PALE High to PROG Low
220
TOSC
TPLDV
PROG Low to Word Dump Valid
TSHLL
RESET High to First PALE Low
TPHIL
PROG High to AINC Low
TILIH
AINC Pulse Width
TILVH
TILPL
TPHVL
PROG High to PVER Valid
TOSC
50
50
1100
TOSC
TOSC
TOSC
0
TOSC
240
TOSC
PVER Hold after AINC Low
50
TOSC
AINC Low to PROG Low
170
TOSC
220
TOSC
NOTES:
1. Run-time programming is done with Fosc e 6.0 MHz to 10.0 MHz, VCC, VPD, VREF e 5V g 0.5V, TC e 25§ C g 5§ C and
VPP e 12.5V g 0.25V. For run-time programming over a full operating range, contact factory.
2. Programming specifications are not tested, but guaranteed by design.
3. This specification is for the word dump mode. For programming pulses use 300 Tosc a 100 ms.
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Parameter
IPP
VPP Programming Supply Current
Min
Max
Units
200
mA
NOTE:
VPP must be within 1V of VCC while VCC k 4.5V. VPP must not have a low impedance path to ground or VSS while VCC l
4.5V.
26
26
87C196KT/87C196KS
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
270999 – 19
SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT
270999 – 20
27
27
87C196KT/87C196KS
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT
270999 – 21
AC CHARACTERISTICSÐSERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMINGÐSHIFTING REGISTER MODE
Test Conditions: TA e b 40§ C to a 125§ C; VCC e 5.0V g 10%; VSS e 0.0V; Load Capacitance e pF
Symbol
TXLXL
Parameter
Serial Port Clock Period
TXLXH
Serial Port Clock Falling Edge to Rising Edge
TQVXH
Output Data Setup to Clock Rising Edge
TXHQX
Output Data Hold after Clock Rising Edge
TXHQV
Next Output Data Valid after Clock Rising Edge
TDVXH
Input Data Setup to Clock Rising Edge
TXHDX(8)
Input Data Hold after Clock Rising Edge
TXHQZ(8)
Last Clock Rising to Output Float
Min
Max
8 TOSC
4 TOSC b 50
Units
ns
TOSC a 50
3 TOSC
ns
ns
2 TOSC b 50
ns
2 TOSC a 50
ns
2 TOSC a 200
ns
0
ns
5 TOSC
ns
NOTE:
8. Parameters not tested.
28
28
87C196KT/87C196KS
WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE
270999 – 22
A TO D CHARACTERISTICS
The sample and conversion time of the A/D converter in the 8-bit or 10-bit modes is programmed by
loading a byte into the ADÐTIME Special Function
Register. This allows optimizing the A/D operation
for specific applications. The ADÐTIME register is
functional for all possible values, but the accuracy of
the A/D converter is only guaranteed for the times
specified in the operating conditions table.
The value loaded into ADÐTIME bits 5, 6, 7 determines the sample time, SAMP. The value loaded
into ADÐTIME bits 0, 1, 2, 3 and 4 determines the
bit conversion time, CONV. These bits, as well as
the equation for calculating the total conversion
time, T, are shown in the following table:
7
6
ADÐTIME
5
4
The converter is ratiometric, so absolute accuracy is
dependent on the accuracy and stability of VREF.
VREF must be close to VCC since it supplies both the
resistor ladder and the analog portion of the converter and input port pins. There is also an ADÐTEST
SFR that allows for conversion on ANGND and
VREF as well as adjusting the zero offset. The absolute error listed is without doing any adjustments.
A/D CONVERTER SPECIFICATION
The specifications given assume adherence to the
operating conditions section of this data sheet. Testing is performed with VREF e 5.12V and 16 MHz
operating frequency. After a conversion is started,
the device is placed in IDLE mode until the conversion is complete.
1FAFH:Byte
3
2
1
Sample Time
Bit Conversion Time
(SAMP)
4n a 1 state times
n e 1 to 7
(CONV)
n a 1 state times
n e 2 to 31
0
Equation: T e (SAMP) a Bx (CONV) a 2.5
T e total conversion time (states)
B e number of bits conversion (8 or 10)
n e programmed register value
29
29
87C196KT/87C196KS
10-BIT MODE A/D OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
TA
Ambient Temperature
b 40
a 125
§C
VCC
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V(1)
TSAM
Sample Time
2.0
TCONV
Conversion Time
15
18
ms(2)
FOSC
Oscillator Frequency
4.0
16.0
MHz
ms(2)
NOTES:
1. VREF must be within 0.5V of VCC.
2. The value of ADÐTIME is selected to meet these specifications.
10-BIT MODE A/D CHARACTERISTICS
Parameter
(Using Above Operating Conditions)(6)
Typ*(1)
Resolution
Absolute Error
Full Scale Error
0.25 g 0.5
Zero Offset Error
0.25 g 0.5
Non-Linearity
1.0 g 2.0
Differential Non-Linearity
Min
Max
Units*
1024
10
1024
10
Level
Bits
0
g 3.0
LSBs
LSBs
LSBs
g 3.0
LSBs
b 0.75
a 0.75
LSBs
g 0.1
0
g 1.0
LSBs
Repeatability
g 0.25
0
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
Channel-to-Channel Matching
Off Isolation
Feedthrough
VCC Power Supply Rejection
b 60
Input Resistance
Sampling Capacitor
LSB/C(1)
LSB/C(1)
LSB/C(1)
dB(1,2,3)
b 60
b 60
DC Input Leakage
LSBs(1)
g 1.0
dB(1,2)
dB(1,2)
750
1.2K
X(4)
0
g 1.5
mA
3.0
pF
*An ‘‘LSB’’ as used here has a value of approximately 5 mV.
NOTES:
1. These values are expected for most parts at 25§ C, but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer break-before-make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. All conversions performed with processor in IDLE mode.
30
30
87C196KT/87C196KS
8-BIT MODE A/D OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
TA
Ambient Temperature
b 40
a 125
§C
VCC
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V(1)
TSAM
Sample Time
2.0
TCONV
Conversion Time
12
15
ms(2)
FOSC
Oscillator Frequency
4.0
16.0
MHz
ms(2)
NOTES:
1. VREF must be within 0.5V of VCC.
2. The value of ADÐTIME is selected to meet these specifications.
8-BIT MODE A/D CHARACTERISTICS
Parameter
(Using Above Operating Conditions)(6)
Typ*(1)
Resolution
Absolute Error
Full Scale Error
g 0.5
Zero Offset Error
g 0.5
Non-Linearity
Differential Non-Linearity
Channel-to-Channel Matching
Repeatability
g 0.25
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.003
0.003
0.003
Off Isolation
Feedthrough
VCC Power Supply Rejection
b 60
Input Resistance
Units*
256
8
256
8
Level
Bits
0
g 1.0
LSBs
LSBs
LSBs
0
g 1.0
LSBs
b 0.5
a 0.5
LSBs
0
g 1.0
LSBs
LSBs(1)
0
LSB/C(1)
LSB/C(1)
LSB/C(1)
dB(1,2,3)
dB(1,2)
dB(1,2)
750
g 1.0
Voltage on Analog Input Pin
Sampling Capacitor
Max
b 60
b 60
DC Input Leakage
Min
1.2K
X(4)
0
g 1.5
mA
ANGND b 0.5
VREF a 0.5
V(5)
3.0
pF
*An ‘‘LSB’’ as used here has a value of approximately 20 mV.
NOTES:
1. These values are expected for most parts at 25§ C, but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer break-before-make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted.
6. All conversions performed with processor in IDLE mode.
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87C196KT/87C196KS
87C196KT/KS ERRATA
The following is a list of all known functional deviations for 87C196KT/KS devices. B-step and later
devices can be identified by a special mark following
the eight digit FPO number on the top of the package. For C-step devices, this mark is a ‘‘C’’.
1. HOLD OR READY DURING DIVIDE; (A-step):
There is a bug in the DIV and DIVB (signed divide) instructions such that if the following 2 conditions are met, there may be an error of 1 in the
quotient:
a) HOLD or READY is asserted during the first
state of execution of the DIV and DIVB instruction.
b) HOLD or READY duration is 16 state times for
the DIVB or 24 state times for a DIV instruction.
2. P2.7 (CLKOUT); (A-step):
Port 2.7 (CLKOUT) does not operate in open
drain mode.
7. REGISTER RAM OVERWRITE; (A-step,
B-step):
If a write is performed to a byte/word location
within the SFR range of 1F60h to 1FFFh, the
data to be written is also written to a correspondding location located within the REGISTER RAM
space 360h to 3FFh. To determine the address
of the REGISTER RAM location that is overwritten, an offset of 1C00h can be subtracted from
the byte/word addressed in the SFR range.
8. BUS TIMING MODES 1 AND 2 (A-step, B-step):
Bus timing modes 1 and 2 are not featured or
specified on A-step and B-step parts. On C-step
parts Mode 1 is selected by setting bits MSEL1
e 0 and MSEL0 e 1 in the CCB1 register.
Mode 2 is similarly selected by setting MSEL1 e
1 and MSEL0 e 0. Timings are altered by
Mode 1 and Mode 2 as follows (for actual values
see the Bus Mode 1 and Bus Mode 2 AC Characteristics in this data sheet):
Mode 1: RD, WR advanced 1 TOSC
ALE advanced 0.5 TOSC
3. P2ÐREG.7 AND P6ÐREG.4 THROUGH P6Ð
REG.7 CLEARED: (A-step):
ALE pulse width remains 1 TOSC
Mode 2: RD, WR advanced 1 TOSC
P2ÐREG.7 is cleared when P2ÐSSEL.7 bit is
changed from a 1 to a 0 (special function to
LSIO). P6ÐReg.4–.7 is cleared when the corresponding P6ÐSSEL.4–.7 is changed from a 1 to
a 0.
ALE advanced 0.5 TOSC
ALE pulse width remains 1 TOSC
4. INDIRECT SHIFT INSTRUCTION; (A-step):
The upper three bits of the byte register holding
the shift count are not masked completely. If the
shift count register has the value 32 x n, where n
e 1, 3, 5 or 7, the operand wil be shifted 32
times. The above condition results in NO shift
taking place.
5. INTERNAL RAM POWERDOWN LEAKAGE;
(A-step):
If an invalid address is applied to the internal
RAM during power-down, the address lines float.
This can cause increased current consumption
during power-down. To insure a valid address on
the internal RAM, execute the idle/power-down
instruction from internal RAM.
6. INST PIN; (A-step):
On A-step devices, the INST pin is pulled medium
low for approx. 200 ns after RESET and then
pulled weakly HIGH until P5SSEL is written to.
This is corrected on B-step devices where the
INST pin is pulled medium low for approx. 200 ns
after RESET and is then pulled weakly LOW until
P5SSEL is written to.
Address advanced 0.5 TOSC
9. VOH2 (A-step, b-step):
A- and B-step parts are capable of VOH2 e VCC
b 1V with IOH e b 6 mA. C-step devices meet
the target values of VOH2 e VCC b 1V with IOH
e b 15 mA.
10. CLKOUT DURING RESET (A-step, B-step,
C-step):
For all steppings of the 87C196KT, the
CLKOUT function during RESET (P2.7) differs
from the 87C196KR C-step. During RESET on
the 87C196KT, CLKOUT does not toggle and
remains in the high state. During RESET on the
87C196KR C-step CLKOUT countinues to toggle.
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87C196KT/87C196KS
87C196KT/KS DESIGN CONSIDERATIONS
1. EPA TIMER RESET/WRITE CONFLICT
4. WRITE CYCLE DURING RESET
If the user writes to the EPA timer at the same
time that the timer is reset, it is indeterminate
which will take precedence. Users should not
write to a timer if using EPA signals to reset it.
If RESET occurs during a write cycle, the contents of the external memory device may be corrupted.
5. INDIRECT SHIFT INSTRUCTION
2. VALID TIME MATCHES
The timer must increment/decrement to the
compare value for a match to occur. A match
does not occur if the timer is loaded with a value
equal to an EPA compare value. Matches also do
not occur if a timer is reset and 0 is the EPA
compare value.
The upper 3 bits of the byte register holding the
shift count are not masked completely. If the shift
count register has the value 32 c n, where
n e 1, 3, 5, or 7, the operand will be shifted 32
times. This should have resulted in no shift taking
place.
3. P6ÐPIN.4-.7 NOT UPDATED IMMEDIATELY
Values written to P6ÐREG are temporarily held
in a buffer. If P6ÐMODE is cleared, the buffer is
loaded into P6ÐREG.x If P6ÐMODE is set, the
value stays in the buffer and is loaded into
P6ÐREG.x when P6ÐMODE.x is cleared. Since
reading P6ÐREG returns the current value in
P6ÐREG and not the buffer, changes to
P6ÐREG
cannot
be
read
until/unless
P6ÐMODE.x is cleared.
6. PORT 4 ADDRESS BEHAVIOR
For bus timing Modes 1 and 2, specified only on
the 87C196KT/KS C-step, Port 4 does not retain
the address during the data portion of the bus
cycle. Designs using an 8-bit external memory
system in bus Mode 1 or Mode 2 require an external latch on Port 4 to retain the address during
the data portion of the bus cycle. Designs using
an 8-bit external memory system in the KR or
KR a 1 Wait bus timing modes do not require an
external latch. Designs using 16-bit external
memory systems require an external latch on
both Port 3 and Port 4 in all bus timing modes.
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87C196KT/87C196KS
DATA SHEET REVISION HISTORY
This is the -007 revision of the 8XC196KT/KS Data Sheet. The following differences exist between the -006
revision and the -007 revision.
1. VOL3 estimate added.
2. ‘‘Voltage on Analog Input Pin’’ removed.
Parameter covered by Note 1: VREF must be within 0.5V of VCC.
3. The Data Sheet Revision History was updated to reflect changes made for this version of the datasheet
(-007).
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