INTEL TN87C196KB16

8XC196KB/8XC196KB16
Table 2. 8XC196KB Memory Map
PROCESS INFORMATION
This device is manufactured on P629.0 and 629.1, a
CHMOS III-E process. Additional process and reliability information is available in the Intel ®Quality
System Handbook:
http://developer.intel.com/design/quality/quality.htm
270909 – 2
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Figure 2. The 8XC196KB Nomenclature
Description
0FFFFH
04000H
Internal ROM/EPROM or External
Memory (Determined by EA)
3FFFH
2080H
Reserved. Must contain FFH.
(Note 5)
207FH
2040H
Upper Interrupt Vectors
203FH
2030H
ROM/EPROM Security Key
202FH
2020H
Reserved. Must contain FFH.
(Note 5)
201FH
201AH
Reserved. Must Contain 20H.
(Note 5)
2019H
CCB
2018H
Reserved. Must contain FFH.
(Note 5)
2017H
2014H
Lower Interrupt Vectors
2013H
2000H
Port 3 and Port 4
1FFFH
1FFEH
External Memory
1FFDH
0100H
232 Bytes Register RAM (Note 1)
00FFH
0018H
CPU SFR’s (Notes 1, 3)
0017H
0000H
Table 1. Thermal Characteristics
Package
Type
θ ja
θ jc
PLCC
35°C/W
13 °C/W
QFP
70°C/W
4 °C/W
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel Packaging Handbook (order number 240800) for a
description of Intel’s thermal impedance test methodology.
Address
External Memory or I/O
NOTES:
1. Code executed in locations 0000H to 00FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KB quick reference for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these locations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
3
8XC196KB/8XC196KB16
270909 – 3
Figure 3. 68-Pin Package (PLCC Top View)
NOTE:
The above pin out diagram applies to the OTP (87C196KB) device. The OTP device uses all of the programming pins shown
above. The ROM (83C196KB) device only uses programming pins: AINC, PALE, PMODE.n, and PROG. The ROMless
(80C196KB) doesn’t use any of the programming pins.
4
8XC196KB/8XC196KB16
270909 – 4
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 4. 80-Pin QFP Package
NOTE:
The above pin out diagram applies to the OTP (87C196KB) device. The OTP device uses all of the programming pins shown
above. The ROM (83C196KB) device only uses programming pins: AINC, PALE, PMODE.n, and PROG. The ROMless
(80C196KB) doesn’t use any of the programming pins.
5
8XC196KB/8XC196KB16
PIN DESCRIPTIONS
Symbol
Name and Function
VCC
Main supply voltage (5V).
VSS
Digital circuit ground (0V). There are multiple VSS pins, all of them must be connected.
VREF
Reference voltage for the A/D converter (5V). VREF is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential as
VSS. Connect VSS and ANGND at chip to avoid noise problems.
VPP
Programming voltage. Also timing pin for the return from power down circuit.
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
CLKOUT
Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator
frequency. It has a 50% duty cycle.
RESET
Reset input to and open-drain output from the chip. Input low for at least 4 state times to reset
the chip. The subsequent low-to-high transition re-synchronizes CLKOUT and commences a
10-state-time RESET sequence.
BUSWIDTH
Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit
cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch and
output low indicates a data fetch. INST is valid throughout the bus cycle. INST is activated
only during external memory accesses.
EA
Input for memory select (External Access). EA equal to a TTL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROM/OTPR OM. EA equal to a
TTL-low causes accesses to these locations to be directed to off-chip memory.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide
a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes
inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory
accesses.
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH
Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will
go low for external writes to the high byte of the data bus. WRH will go low for external writes
where an odd byte is being addressed. BHE/WRH is activated only during external memory
writes.
READY
Ready input to lengthen external memory cycles. If the pin is low prior to the falling edge of
CLKOUT, the memory controller goes into a wait mode until the next positive transition in
CLKOUT occurs with READY high. When the external memory is not being used, READY has
no effect. Internal control of the number of wait states inserted into a bus cycle (held not
ready) is available in the CCR.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,
HSO.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
6
8XC196KB/8XC196KB16
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
Port 0
8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
Port 1
8-bit quasi-bidirectional I/O port. These pins are shared with HOLD, HLDA and BREQ.
Port 2
8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KB.
Pins P2.6 and P2.7 are quasi-bidirectional.
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus, which has strong internal pullups.
HOLD
Bus Hold input requesting control of the bus. Enabled by setting WSR.7.
HLDA
Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.
BREQ
Bus Request output activated when the bus controller has a pending external memory
cycle. Enabled by setting WSR.7.
TxD
The TxD pin is used for serial port transmission in Modes 1, 2 and 3. In Mode 0 the pin is
used as the serial clock output.
RxD
Serial Port Receive pin used for serial port reception. In Mode 0 the pin functions as input or
output data.
EXTINT
A rising edge on the EXTINT pin will generate an external interrupt.
T2CLK
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
T2RST
A rising edge on the T2RST pin will reset Timer2.
PWM
The pulse width modulator output.
T2UP-DN
The T2UPDN pin controls the direction of Timer2 as an up or down counter.
T2CAPTURE
A rising edge on P2.7 will capture the value of Timer2 in the T2CAPTURE register.
PMODE
Programming Mode Select. Determines the EPROM programming algorithm that is
performed. PMODE is sampled after a chip reset and should be static while the part is
operating.
SID
Slave ID Number. Used to assign each slave a pin of Port 3 or 4 to use for passing
programming verification acknowledgement.
PALE
Programming ALE Input. Accepted by the 87C196KB when it is in Slave Programming
Mode. Used to indicate that Ports 3 and 4 contain a command/address.
PROG
Programming. Falling edge indicates valid data on PBUS and the beginning of
programming. Rising edge indicates end of programming.
PACT
Programming Active. Used in the Auto Programming Mode to indicate when programming
activity is complete.
PVAL
Program Valid. This signal indicates the success or failure of programming in the Auto
Programming Mode. A zero indicates successful programming.
PVER
Program Verification. Used in Slave Programming and Auto CLB Programming Modes.
Signal is low after rising edge of PROG if the programming was not successful.
AINC
Auto Increment. Active low signal indicates that the auto increment mode is enabled. Auto
Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
Ports 3
and 4
(Programming
Mode)
Address/Command/Data Bus. Used to pass commands, addresses, and data to and from
slave mode 87C196KBs. Used by chips in Auto Programming Mode to pass command,
addresses and data to slaves. Also used in the Auto Programming Mode as a regular
system bus to access external memory. Should have pullups to VCC when used in slave
programming mode.
7
8XC196KB/8XC196KB16
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
Ambient Temperature
Under Bias................................. b 55§ C to a 125§ C
Storage Temperature.................... b65§C to a 150§C
Voltage On Any Pin to VSS................ b0.5V to a 7.0V
*WARNING: Stressing the device beyond the ``Absolute
Maximum Ratings'' may cause permanent damage.
These are stress ratings only. Operation beyond the
``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions''
may affect device reliability.
Power Dissipation(1)..........................1.5W
NOTE:
1. Power dissipation is based on package heat transfer limitations, not device power consumption.
OPERATING CONDITIONS
(All characteristics in this data sheet apply to these operating conditions unless otherwise noted.)
Symbol
Description
Min
Max
Units
TA
Ambient Temperature Under Bias
0
a 70
VCC
Digital Supply Voltage
4.50
5.50
§C
VREF
Analog Supply Voltage
4.50
5.50
V
V
FOSC
Oscillator Frequency 12 MHz
3.5
12
MHz
FOSC
Oscillator Frequency 16 MHz
3.5
16
MHz
NOTE:
ANGND and VSS should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
Description
Min
0.8
Units
Test Conditions
Input Low Voltage
VIH
Input High Voltage (All Pins except
XTAL1 and RESET)
VIH1
Input High Voltage on XTAL 1
0.7 VCC
VCC a 0.5
V
VIH2
Input High Voltage on RESET
2.6
VCC a 0.5
V
VOL
Output Low Voltage
0.3
0.45
1.5
V
V
V
IOL e 200 mA
IOL e 3.2 mA
IOL e 7 mA
VOH
Output High Voltage
(Standard Outputs)(2)
VCC b 0.3
VCC b 0.7
VCC b 1.5
V
V
V
IOH e b 200 mA
IOH e b 3.2 mA
IOH e b 7 mA
VOH1
Output High Voltage
(Quasi-bidirectional Outputs)(1)
VCC b 0.3
VCC b 0.7
VCC b 1.5
V
V
V
IOH e b 10 mA
IOH e b 30 mA
IOH e b 60 mA
ILI
Input Leakage Current
(Std. Inputs)(3)
ILI1
Input Leakage Current (Port 0)
ITL
1 to 0 Transition Current
(QBD Pins)(1)
IIL
Logical 0 Input Current (QBD Pins)(1)
8
b 0.5
Max
VIL
0.2 VCC a 0.9 VCC a 0.5
g 10
V
V
mA
0 k VIN k VCC b 0.3V
a3
mA
b 800
mA
0 k VIN k VREF
VIN e 2.0V
b 50
mA
VIN e 0.45V
8XC196KB/8XC196KB16
DC CHARACTERISTICS (Continued)
Symbol
Description
Min
Typ(7)
Max
IIL1
Logical 0 Input Current in Reset
BHE, WR, P2.0
b 850
mA
VIN e 0.45V
IIL2
Logical 0 Input Current in Reset
ALE, RD, INST
b7
mA
VIN e 0.45V
IIH1
Logical 1 Input Current
on NMI Pin
100
mA
VIN e 2.0V
Hyst.
Hysteresis on RESET Pin
ICC
Active Mode Current in Reset
50
60
mA
IREF
A/D Converter Reference Current
2
5
mA
IIDLE
Idle Mode Current
10
25
mA
IPD
Powerdown Mode Current
5
30
mA
RRST
Reset Pullup Resistor
CS
Pin Capacitance (Any Pin to VSS)
300
6K
Units
Test Conditions
mV
50K
X
10
pF
XTAL1 e 16 MHz
VCC e VPP e VREF e 5.5V
VCC e VPP e VREF e 5.5V
FTEST e 1.0 MHz
NOTES: (Notes apply to all specifications)
1. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
2. Standard Outputs include AD0±15, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0 and RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
3. Standard Inputs include HSI pins, EA, READY, BUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/
P2.4.
4. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below VCC b 0.7V:
IOL on Output pins: 10 mA
IOH on quasi-bidirectional pins: self limiting
IOH on Standard Output pins: 10 mA
5. Maximum current per bus pin (data and control) during normal operation is g 3.2 mA.
6. During normal (non-transient) conditions the following total current limits apply:
IOH is self limiting
Port 1, P2.6
IOL: 29 mA
IOH: 26 mA
HSO, P2.0, RXD, RESET IOL: 29 mA
IOL: 13 mA
IOH: 11 mA
P2.5, P2.7, WR, BHE
IOH: 52 mA
AD0±AD15
IOL: 52 mA
IOH: 13 mA
RD, ALE, INST±CLKOUT IOL: 13 mA
7. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
e
e
VCC
5V.
and VREF
ICC Max e 3.88 c FREQ a 8.43
IIDLE Max e 1.65 c FREQ a 2.2
270909 ±5
Figure 6. I CC and I IDLE vs Frequency
9
8XC196KB/8XC196KB16
AC CHARACTERISTICS
Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 12/16 MHz
The system must meet these specifications
Symbol
Description
TAVYV
Address Valid to READY Setup
TYLYH
NonREADY Time
TCLYX
READY Hold after CLKOUT Low
TLLYX
READY Hold after ALE Low
TAVGV
Address Valid to Buswidth Setup
TCLGX
Buswidth Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
TRLDV
to work with the 87C196KB:
Min
Max
2 TOSC b 75
No upper limit
Units
Notes
ns
ns
0
TOSC b 30
ns
(Note 1)
TOSC b 15
2 TOSC b 40
ns
(Note 1)
2 TOSC b 75
0
ns
ns
3 TOSC b 55
ns
(Note 2)
RD Active to Input Data Valid
TOSC b 23
ns
(Note 2)
TCLDV
CLKOUT Low to Input Data Valid
TOSC b 50
ns
TRHDZ
End of RD to Input Data Float
TOSC b 20
ns
TRXDX
Data Hold after RD Inactive
0
NOTES:
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2 TOSC c n where n e number of wait states.
10
ns
8XC196KB/8XC196KB16
AC CHARACTERISTICS (Continued)
Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 12/16 MHz
The 87C196KB will meet these specifications:
Symbol
Description
Min
Max
Units
Notes
FXTAL
Frequency on XTAL1 12 MHz
3.5
FXTAL
Frequency on XTAL1 16 MHz
3.5
12.0
MHz
(Note 2)
16.0
MHz
(Note 2)
TOSC
1/F XTAL 12 MHz
TOSC
1/F XTAL 16 MHz
83.3
286
ns
62.5
286
ns
TXHCH
XTAL1 High to CLKOUT High or Low
a 20
TCLCL
CLKOUT Cycle Time
a 110
ns
2 TOSC
ns
TOSC b 10
TOSCa 10
TCHCL
CLKOUT High Period
TCLLH
CLKOUT Falling Edge to ALE Rising
b 10
a 10
ns
ns
TLLCH
ALE Falling Edge to CLKOUT Rising
b 15
a 15
TLHLH
ALE Cycle Time
4 TOSC
ns
ns
TLHLL
ALE High Period
TOSC b 10
TAVLL
Address Setup to ALE Falling Edge
TOSC b 20
ns
TLLAX
Address Hold after ALE Falling Edge
TOSC b 40
ns
TLLRL
ALE Falling Edge to RD Falling Edge
TOSC b 35
TRLCL
RD Low to CLKOUT Falling Edge
TRLRH
RD Low Period
TRHLH
RD Rising Edge to ALE Rising Edge
TRLAZ
RD Low to Address Float
TLLWL
ALE Falling Edge to WR Falling Edge
TCLWL
CLKOUT Low to WR Falling Edge
TQVWH
Data Stable to WR Rising Edge
TCHWH
CLKOUT High to WR Rising Edge
TWLWH
TOSCa 10
(Note 3)
ns
ns
a4
a 25
ns
TOSCb 5
TOSC a 25
ns
(Note 3)
TOSC
TOSC a 25
ns
(Note 1)
a5
ns
TOSC b 10
0
ns
a 25
TOSC b 23
ns
ns
b5
a 15
WR Low Period
TOSC b 15
TOSC a 5
TWHQX
Data Hold after WR Rising Edge
TOSC b 15
TWHLH
WR Rising Edge to ALE Rising Edge
TOSC b 15
TWHBX
BHE, INST HOLD after WR Rising Edge
TOSC b 15
ns
TRHBX
BHE, INST HOLD after RD Rising Edge
TOSC b 10
ns
TWHAX
AD8±15 hold after WR Rising Edge
TOSC b 30
ns
TRHAX
AD8±15 hold after RD Rising Edge
TOSC b 25
ns
(Note 3)
ns
ns
(Note 3)
ns
TOSC a 10
ns
(Note 1)
NOTES:
1. Assuming back-to-back bus cycles.
2. Testing performed at 3.5 MHz, however, the device is static by design and will typically operate below 1 Hz.
3. When using wait states, all 2 TOSCa n where n e number of wait states.
11
8XC196KB/8XC196KB16
System Bus Timings
270909 ±6
12
8XC196KB/8XC196KB16
READY Timings (One Wait State)
270909 ±7
Buswidth Bus Timings
270909 ±8
13
8XC196KB/8XC196KB16
HOLD/HLDA Timings
Symbol
Description
Min
THVCH
HOLD Setup
55
Max
Units
TCLHAL
CLKOUT Low to HLDA Low
15
TCLBRL
CLKOUT Low to BREQ Low
15
ns
THALAZ
HLDA Low to Address Float
10
ns
THALBZ
HLDA Low to BHE, INST, RD, WR Float
10
ns
TCLHAH
CLKOUT Low to HLDA High
b 15
15
ns
TCLBRH
CLKOUT Low to BREQ High
b 15
15
ns
THAHAX
HLDA High to Address No Longer Float
b 15
ns
THAHAV
HLDA High to Address Valid
0
ns
THAHBX
HLDA High to BHE, INST, RD, WR No Longer Float
THAHBV
HLDA High to BHE, INST, RD, WR Valid
TCLLH
CLKOUT Low to ALE High
ns
ns
b 20
ns
0
ns
b5
15
Notes
(Note 1)
ns
NOTE:
1. To guarantee recognition at next clock.
Maximum Hold Latency
Bus Cycle Type
Internal Access
16-Bit External Execution
8-Bit External
Latency
1.5 States
2.5 States
4.5 States
270909 ±9
14
8XC196KB/8XC196KB16
EXTERNAL CLOCK DRIVE
Symbol
Parameter
1/T XLXL
Oscillator Frequency 12 MHz
Min
Max
1/T XLXL
Oscillator Frequency 16 MHz
TXLXL
Oscillator Period 12 MHz
TXLXL
Oscillator Period 16 MHz
62.5
286
TXHXX
High Time
21.25
TXLXX
Low Time
21.25
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
3.5
Units
12.0
MHz
3.5
16
MHz
83.3
286
ns
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270909 ±10
An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications, the capacitance will not exceed 20 pF.
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
270909 ±11
NOTE:
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and VSS. When
using crystals, C1 e 20 pF, C2 e 20 pF. When using
ceramic resonators, consult manufacturer for recommended circuitry.
AC TESTING INPUT, OUTPUT WAVEFORMS
270909 ±13
AC Testing inputs are driven at 2.4V for a Logic ``1'' and 0.45V for
a Logic ``0'' Timing measurements are made at 2.0V for a Logic
``1'' and 0.8V for a Logic ``0''.
270909 ±12
* Required if open-collector TTL driver used
Not needed if CMOS driver is used.
FLOAT WAVEFORMS
270909 ±14
For Timing Purposes a Port Pin is no Longer Floating when a
200 mV change from Load Voltage Occurs and Begins to Float
when a 200 mV change from the Loaded VOH/V OL Level occurs;
IOL/I OH e g 15 mA.
15
8XC196KB/8XC196KB16
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ``T'' for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
H
- High
L
- Low
A
B
- Address
- BHE
G
- Buswidth
V
X
- Valid
- No Longer Valid
BR - BREQ
H
- HOLD
HA - HLDA
C
- CLKOUT
L
- ALE/ADV
Z
- Floating
D
- DATA IN
Q
- DATA OUT
AC CHARACTERISTICS-SERIAL
R
W
X
- RD
- WR/WRH /WRL
- XTAL1
Y
- READY
PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE (MODE 0)
Symbol Parameter
Min
TXLXL
Serial Port Clock Period (BRR t 8002H)
6 TOSC
Max
Units
TXLXH
Serial Port Clock Falling Edge to Rising Edge (BRR t 8002H)
TXLXL
Serial Port Clock Period (BRR e 8001H)
TXLXH
Serial Port Clock Falling Edge to Rising Edge (BRR e 8001H) 2 TOSC b 50 2 TOSC a 50
ns
TQVXH
Output Data Setup to Clock Rising Edge
2 TOSC b 50
ns
TXHQX
Output Data Hold after Clock Rising Edge
2 TOSC b 50
TXHQV
Next Output Data Valid after Clock Rising Edge
TDVXH
Input Data Setup to Clock Rising Edge
TXHDX
Input Data Hold after Clock Rising Edge
TXHQZ
Last Clock Rising to Output Float
ns
4 TOSC b 50 4 TOSC a 50
4 TOSC
ns
ns
ns
2 TOSC a 50
ns
TOSC a 50
ns
0
ns
2 TOSC
ns
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE (MODE 0)
270909 ±18
16
8XC196KB/8XC196KB16
State times are calculated as follows:
10-BIT A/D CHARACTERISTICS
At a clock speed of 6 MHz or less, the clock prescaler should be disabled. This is accomplished by setting IOC2.4 e 1.
At higher frequencies (greater than 6 MHz) the clock
prescaler should be enabled (IOC2.4 e 0) to allow
the comparator to settle.
state time e
2
XTAL1
The converter is ratiometric, so the absolute accuracy is directly dependent on the accuracy and stability
of VREF. VREF must be close to VCC since it supplies
both the resistor ladder and the digital section of the
converter.
The table below shows two different clock speeds
See the MCS-96 A/D Converter Quick Reference
and their corresponding A/D conversion and sample
for definition of A/D terms.
times.
Example Sample and Conversion Times
A/D Clock
Prescaler
IOC2.4 e 0
IOC2.4 e 1
Clock Speed
(MHz)
x ON
x OFF
Sample Time
(States)
Sample Time
at Clock
Speed
(ms)
Conversion
Time
(States)
Conversion
Time at
Clock Speed
(ms)
16
15
1.875
156.5
19.6
6
8
2.667
89.5
29.8
A/D CONVERTER SPECIFICATIONS
Parameter
Typical(1)
Resolution
Absolute Error
Full Scale Error
0.25 g 0.50
Zero Offset Error
0.25 g 0.50
Non-Linearity Error
1.5 g 2.5
Differential Non-Linearity Error
Channel-to-Channel Matching
g 0.1
Minimum
Maximum
Units *
1024
10
1024
10
Levels
Bits
0
g3
LSBs
LSBs
LSBs
0
g3
LSBs
l b1
a2
LSBs
0
g1
LSBs
Repeatability
g 0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
LSB/ § C
LSB/ § C
LSB/ § C
Off Isolation
Notes
dB
2, 3
Feedthrough
b 60
b 60
dB
2
VCC Power Supply Rejection
b 60
dB
2
4
Input Series Resistance
DC Input Leakage
Sampling Capacitor
750
1.2K
X
0
g 3.0
mA
3
pF
NOTES:
*An ``LSB'', as used here, has a value of approximately 5 mV.
1. Typical values are expected for most devices at 25§ C.
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make Guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
17
8XC196KB/8XC196KB16
OTPROM SPECIFICATIONS
OTPROM PROGRAMMING OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Units
TA
Ambient Temperature During Programming
20
30
C
VCC, VPD, VREF(1)
Supply Voltages During Programming
4.5
5.5
V
VEA
Programming Mode Supply Voltage
12.50
13.0
V(2)
VPP
EPROM Programming Supply Voltage
12.50
13.0
V(2)
VSS, ANGND(3)
Digital and Analog Ground
0
0
V
FOSC
Oscillator Frequency 12 MHz
6.0
12.0
MHz
FOSC
Oscillator Frequency 16 MHz
6.0
16.0
MHz
NOTES:
1. VCC, VPD and VREF should nominally be at the same voltage during programming.
2. VEA and VPP must never exceed the maximum voltage for any amount of time or the device may be damaged.
3. VSS and ANGND should nominally be at the same voltage (0V) during programming.
AC OTPROM PROGRAMMING CHARACTERISTICS
Symbol
18
Description
Min
Max
Units
TSHLL
Reset High to First PALE Low
TLLLH
PALE Pulse Width
1100
TOSC
40
TOSC
TAVLL
TLLAX
Address Setup Time
0
TOSC
Address Hold Time
50
TOSC
TLLVL
PALE Low to PVER Low
60
TOSC
TPLDV
PROG Low to Word Dump Valid
50
TOSC
TPHDX
Word Dump Data Hold
TDVPL
Data Setup Time
0
TOSC
TPLDX
Data Hold Time
50
TOSC
TPLPH
PROG Pulse Width
40
TOSC
TPHLL
PROG High to Next PALE Low
120
TOSC
TLHPL
PALE High to PROG Low
220
TOSC
TPHPL
PROG High to Next PROG Low
120
TOSC
TPHIL
PROG High to AINC Low
0
TOSC
TILIH
AINC Pulse Width
40
TOSC
TILVH
PVER Hold after AINC Low
50
TOSC
TILPL
AINC Low to PROG Low
170
TOSC
TPHVL
PROG High to PVER Low
50
90
TOSC
TOSC
8XC196KB/8XC196KB16
DC OTPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
IPP
VPP Supply Current (When Programming)
Min
Max
Units
100
mA
NOTE:
Do not apply VPP until VCC is stable and within specifications and the oscillator/clock has stabilized or the device may be
damaged.
OTPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
270909 ±15
SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT
270909 ±16
19
8XC196KB/8XC196KB16
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT
270909 ±17
20
8XC196KB/8XC196KB16
FUNCTIONAL DEVIATIONS
Devices marked with an ‘‘E’’, ‘‘F’’ or ‘‘G’’ have the
following errata.
1. Missed Interrupt on P0.7, EXTINT
The following differences exist between this data
sheet (270909-005) and (270909-004).
1. ITL MAX was – 650 μA (270909-004). Now ITL
MAX is – 800 μA (270909-005).
2. IIL2 was named IIL1 (270909-004). Now IIL2 is
correctly named (270909-005).
2. HSI_ MODE Divide-by-Eight
3. IIL1 was omitted (270909-004). IIL1 MAX was
added. IIL1 MAX is – 850 μA (270909-005).
4. TLLYV and TLLGV (270909-004) were removed.
These timings are not required in high-speed system designs.
REVISION HISTORY
5. An errata was added to the known errata section.
There is a possibility to miss an external interrupt
on P0.7 EXTINT.
Interrupts occurring on P0.7 could be missed since
the INT_PEND EXTINT bit may not be set. See
techbit MC0893.
This data sheet (270909-006) is valid for devices
with an ‘‘E’’, ‘‘F’’ or ‘‘G’’ at the end of the top side
tracking number. Data sheets are changed as new
device information becomes available. Verify with
your local Intel sales office that you have the latest
version before finalizing a design or ordering devices.
The following differences exist between this data
sheet (270909-007) and (270909-006).
1. Package prefix variables have changed.
These variables are now indicated by “x”.
The following differences exist between data
sheet 270909-006 and 270909-005.
1. Removed ‘‘Word Addressable Only’’ from Port 3
and 4 in Table 2.
2. Removed ICC1, active mode current at 3.5 MHz.
This specification is not longer required.
3. Removed TLLYV and TLLGV from waveform diagrams.
4. The HSI errata and CMPL with R0 were removed
as this is now considered normal operation.
The following differences exist between this data
sheet (270909-004) and (270909-003).
1. The
ROM
(80C196KB),
and
ROMless
(83C196KB) were combined with this data sheet
resulting in no specification differences.
2. The description of the prescalar bit for the A/D
has been enhanced.
3. THAHBVMIN was – 15 ns (270909-003). Now
THAHBVMIN is – 20 ns (270909-004).
4. TXHQZMAX was 1 TOSC (270909-003). Now
TXHQZMAX is 2 TOSC (270909-004). This should
have no impact on designs using synchronous
serial mode 0.
5. The change indicators for the 80C196KB are
‘‘E’’, ‘‘F’’ and ‘‘G’’. Previously there was only one
change indicator ‘‘E’’. The change indicator is
used for tracking purposes. The change indicator
is the last character in the FPO number. The FPO
number is the second line on the top side of the
device.
5. The HSI_ MODE divide-by-eight errata was added to the known errata section.
21
8XC196KB/8XC196KB16
The following differences exist between (-003) and
version (-002).
1. The 12 MHz and 16 MHz devices were combined in this data sheet. The 87C196KB 12 MHz
only data sheet (272035-001) is now obsolete.
2. Changes were made to the format of the data
sheet and the SFR descriptions were removed.
3. The -002 version of this data sheet was valid for
devices marked with a ``B'' or a ``D'' at the end
of the top side tracking number.
4. The OSCILLATOR errata was removed.
5. An errata was not documented in the -002 data
sheet for devices marked with a ``B'' or a ``D''.
This is the DIVIDE DURING HOLD/READY errata. When HOLD or READY is active and DIV/
DIVB is the last instruction in the queue, the divide result may be incorrect.
6. TXCH was changed from Min e 40 ns to Min e
20 ns.
7. TRLCL was changed from Min e 5 ns to Min e
4 ns.
9. IIL1 was changed from Max e b 6 mA to Max e
b 7 mA.
10. THAHBV was changed from Min e b 10 ns to
Min e b 15 ns.
Differences between the -002 and -001 data sheets.
1. The -001 version of this data sheet was valid for
devices marked with a ``C'' at the end of the top
side tracking number.
2. Added 64L SDIP and 80L QFP packages.
3. Added IIH1.
4. Changed TCHWH Min from b 10 ns to b 5 ns.
5. Changed TCHWH Max from a 10 ns to a 15 ns.
6. Changed TWLWH Min from TOSC b 20 ns to
TOSC b 15 ns.
7. Changed TWHQX Min from TOSC b 10 ns to
TOSC b 15 ns.
8. Changed TWHLH Min from TOSC b 10 ns to
TOSC b 15 ns.
9. Changed TWHLH Max from TOSC a 15 ns to
TOSC a 10 ns.
10. Changed TWHBX Min from TOSC b 10 ns to
TOSC b 15 ns.
11. Changed THVCH Min from 85 ns to 55 ns.
12. Remove THVCH Max.
13. Changed TCLHAL Min from b 10 ns to b 15 ns.
14. Changed TCLHAL Max from 20 ns to 15 ns.
15. Changed TCLBRL Min from b 10 ns to b 15 ns.
16. Changed TCLBRL Max from 20 ns to 15 ns.
17. Changed THAHAX Min from b 10 ns to b 15 ns.
18. Added HSI description to Functional Deviations.
19. Added Oscillator description to Functional Deviations.
22