8XC196KD/8XC196KD20 8XC196KD VERTICAL WINDOWING MAP Table 1. 128-Byte Windows Address to Remap Device Series WSR Contents Table 3. 32-Byte Windows Address to Remap Device Series WSR Contents 03E0H KD X101 1111B e 5FH 03C0H KD X101 1110B e 5EH 0380H KD X001 0111B e 17H 03A0H KD X101 1101B e 5DH 0300H KD X001 0110B e 16H 0380H KD X101 1100B e 5CH 0280H KD X001 0101B e 15H 0360H KD X101 1011B e 5BH 0200H KD X001 0100B e 14H 0340H KD X101 1010B e 5AH 0180H KC, KD X001 0011B e 13H 0320H KD X101 1001B e 59H 0100H KC, KD X001 0010B e 12H 0300H KD X101 1000B e 58H 0080H KC, KD X001 0001B e 11H 02E0H KD X101 0111B e 57H 0000H KC, KD X001 0000B e 10H 02C0H KD X101 0110B e 56H 02A0H KD X101 0101B e 55H 0280H KD X101 0100B e 54H 0260H KD X101 0011B e 53H Window in Lower Register File: 80H ±FFH Table 2. 64-Byte Windows Address to Remap Device Series WSR Contents 0240H KD X101 0010B e 52H KD X010 1111B e 2FH 0220H KD X101 0001B e 51H 0380H KD X010 1110B e 2EH 0200H KD X101 0000B e 50H 0340H KD X010 1101B e 2DH 01E0H KC, KD X100 1111B e 4FH 0300H KD X010 1100B e 2CH 01C0H KC, KD X100 1110B e 4EH 02C0H KD X010 1011B e 2BH 01A0H KC, KD X100 1101B e 4DH 0280H KD X010 1010B e 2AH 0180H KC, KD X100 1100B e 4CH 0240H KD X010 1001B e 29H 0160H KC, KD X100 1011B e 4BH 0200H KD X010 1000B e 28H 0140H KC, KD X100 1010B e 4AH 01C0H KC, KD X010 0111B e 27H 0120H KC, KD X100 1001B e 49H 0180H KC, KD X010 0110B e 26H 0100H KC, KD X100 1000B e 48H 0140H KC, KD X010 0101B e 25H 00E0H KC, KD X100 0111B e 47H 0100H KC, KD X010 0100B e 24H 00C0H KC, KD X100 0110B e 46H 00C0H KC, KD X010 0011B e 23H 00A0H KC, KD X100 0101B e 45H 0080H KC, KD X010 0010B e 22H 0080H KC, KD X100 0100B e 44H 0040H KC, KD X010 0001B e 21H 0060H KC, KD X100 0011B e 43H 0000H KC, KD X010 0000B e 20H 0040H KC, KD X100 0010B e 42H 0020H KC, KD X100 0001B e 41H 0000H KC, KD X100 0000B e 40H 03C0H Window in Lower Register File: C0H±FFH Window in Lower Register File: E0H±FFH 3 8XC196KD/8XC196KD20 PROCESS INFORMATION Table 5. 8XC196KD Memory Map This device is manufactured on PX29.5 or PX29.9, a CHMOS III process. Additional process and reliability information is available in the Intel® Quality System Handbook: http://developer.intel.com/design/quality/quality.htm x x x NOTE: 1. EPROMs are available as One Time Programmable (OTPROM) only. Figure 3. The 8XC196KD Family Nomenclature Table 4. Thermal Characteristics Package Type θ ja θ jc PLCC 35°C/W 13 °C/W QFP 56°C/W 12 °C/W SQFP 68°C/W 15.5 °C/W All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operation conditions and application. See the Intel Packaging Handbook (order number 240800) for a description of Intel’s thermal impedance test methodology. Description External Memory or I/O Address 0FFFFH 0A000H Internal ROM/OTPROM or External Memory (Determined by EA) 9FFFH 2080H Reserved. Must contain FFH. (Note 5) 207FH 205EH PTS Vectors 205DH 2040H Upper Interrupt Vectors 203FH 2030H ROM/OTPROM Security Key 202FH 2020H Reserved. Must contain FFH. (Note 5) 201FH 201AH Reserved. Must Contain 20H (Note 5) 2019H CCB 2018H Reserved. Must contain FFH. (Note 5) 2017H 2014H Lower Interrupt Vectors 2013H 2000H Port 3 and Port 4 1FFFH 1FFEH External Memory 1FFDH 0400H 1000 Bytes Register RAM (Note 1) 03FFH 0018H CPU SFR’s (Notes 1, 3) 0017H 0000H NOTES: 1. Code executed in locations 0000H to 03FFH will be forced external. 2. Reserved memory locations must contain 0FFH unless noted. 3. Reserved SFR bit locations must contain 0. 4. Refer to 8XC196KC for SFR descriptions. 5. WARNING: Reserved memory locations must not be written or read. The contents and/or function of these locations may change with future revisions of the device. Therefore, a program that relies on one or more of these locations may not function properly. 4 8XC196KD/8XC196KD20 272145 – 3 Figure 4. 68-Pin PLCC Package 5 8XC196KD/8XC196KD20 272145 – 4 NOTE: N.C. means No Connect (do not connect these pins). Figure 5. 80-Pin QFP Package 6 8XC196KD/8XC196KD20 272145 – 20 NOTE: N.C. means No Connect (do not connect these pins). Figure 6. 80-Pin SQFP Package 7 8XC196KD/8XC196KD20 PIN DESCRIPTIONS Symbol 8 Name and Function VCC Main supply voltage (5V). VSS Digital circuit ground (0V). There are multiple VSS pins, all of which must be connected. VREF Reference voltage for the A/D converter (5V). VREF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. VPP Timing pin for the return from powerdown circuit. This pin also supplies the programming voltage on the EPROM device. XTAL1 Input of the oscillator inverter and of the internal clock generator. XTAL2 Output of the oscillator inverter. CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator frequency. RESET Reset input and open drain output. BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus. NMI A positive transition causes a vector through 203EH. INST Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is activated only during external memory accesses and output low for a data fetch. EA Input for memory select (External Access). EA equal high causes memory accesses to locations 2000H through 9FFFH to be directed to on-chip ROM/E PROM. EA equal low causes accesses to those locations to be directed to off-chip memory. Also used to enter programming mode. ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a signal to demultiplex the address from the address/data bus. When the pin is ADV, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory accesses. RD Read signal output to external memory. RD is activated only during external memory reads. WR/WRL Write and Write Low output to external memory, as selected by the CCR. WR will go low for every external write, while WRL will go low only for external writes where an even byte is being written. WR/WRL is activated only during external memory writes. BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will go low for external writes to the high byte of the data bus. WRH will go low for external writes where an odd byte is being written. BHE/WRH is activated only during external memory writes. READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. When the external memory is not being used, READY has no effect. HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit. 8XC196KD/8XC196KD20 PIN DESCRIPTIONS (Continued) Symbol Name and Function Port 0 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. Port 1 8-bit quasi-bidirectional I/O port. Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the 8XC196KD. Pins 2.6 and 2.7 are quasi-bidirectional. Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. HOLD Bus Hold input requesting control of the bus. HLDA Bus Hold acknowledge output indicating release of the bus. BREQ Bus Request output activated when the bus controller has a pending external memory cycle. PMODE Determines the EPROM programming mode. PACT A low signal in Auto Programming mode indicates that programming is in process. A high signal indicates programming is complete. PALE A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that ports 3 and 4 contain valid programming address/command information (input to slave). PROG A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid programming data (input to slave). PVER A high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly. CPVER Cummulative Program Output Verification. Pin is high if all locations have programmed correctly since entering a programming mode. AINC Auto Increment. Active low input enables the auto increment mode. Auto increment allows reading or writing sequential EPROM locations without address transactions across the PBUS for each read or write. 9 8XC196KD/8XC196KD20 ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias................................. b 55§ C to a 125§ C Storage Temperature.................... b 65§ C to a 150§ C Voltage On Any Pin to VSS (1) Except EA and VPP................... b 0.5V to a 7.0V Voltage from EA or VPP to VSS or ANGND.............. b 0.5V to a 13.00V *WARNING: Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability. (2) Power Dissipation............................................1.5W NOTES: 1. This includes VPP and EA on ROM or CPU only devices. 2. Power dissipation is based on package heat transfer limitations, not device power consumption. OPERATING CONDITIONS Symbol Description Min Max TA TA 0 a 70 Ambient Temperature Under Bias Extended Temp. -40 +85 VCC Digital Supply Voltage 4.50 5.50 VREF Analog Supply Voltage 4.00 5.50 V ANGND Analog Ground Voltage VSS b 0.4 VSS a 0.4 V(1) FOSC Oscillator Frequency (8XC196KD) 8 16 MHz FOSC Oscillator Frequency (8XC196KD20) 8 20 MHz Ambient Temperature Under Bias Commercial Temp. Units §C °C V NOTE: 1. ANGND and VSS should be nominally at the same potential. DC CHARACTERISTICS (Over Specified Operating Conditions) Symbol Description VIL Input Low Voltage VIH Input High Voltage (Note 1) VHYS Hysteresis on RESET Min Max b 0.5 0.8 0.2 VCC a 1.0 VCC a 0.5 300 Units Test Conditions V V mV VCC e 5.0V VIH1 Input High Voltage on XTAL 1 0.7 VCC VCC a 0.5 VIH2 Input High Voltage on RESET 2.2 VCC a 0.5 V VOL Output Low Voltage 0.3 0.45 1.5 V V V IOL e 200 mA IOL e 2.8 mA IOL e 7 mA VOL1 Output Low Voltage in RESET on P2.5 (Note 2) 0.8 V IOL e a 0.4 mA VOH Output High Voltage (Standard Outputs) (Note 4) VCC b 0.3 VCC b 0.7 VCC b 1.5 V V V IOH e b 200 mA IOH e b 3.2 mA IOH e b 7 mA VOH1 Output High Voltage (Quasi-bidirectional Outputs) (Note 3) VCC b 0.3 VCC b 0.7 VCC b 1.5 V V V IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA 10 V 8XC196KD/8XC196KD20 DC CHARACTERISTICS (Over Specified Operating Conditions) (Continued) Symbol Description Min IOH1 Logical 1 Output Current in Reset on P2.0. Do not exceed this or device may enter test modes. b 0.8 IIL2 Logical 0 Input Current in Reset on P2.0. Maximum current that must be sunk by external device to ensure test mode entry. IIH1 Logical 1 Input Current. Maximum current that external device must source to initiate NMI. ILI Input Leakage Current (Std. Inputs) (Note 5) ILI1 Typ Max Units Test Conditions mA VIH e VCC b 1.5V b 12.0 mA VIN e 0.45V a 200 mA VIN e 2.4V g 10 mA 0 k VIN k VCC b 0.3V Input Leakage Current (Port 0) g3 mA 0 k VIN k VREF ITL 1 to 0 Transition Current (QBD Pins) b 650 mA VIN e 2.0V IIL Logical 0 Input Current (QBD Pins) b 70 mA VIN e 0.45V IIL1 AD Bus in Reset b 70 mA VIN e 0.45V ICC Active Mode Current in Reset (8XC196KD) 65 75 mA XTAL1 e 16 MHz VCC e VPP e VREF e 5.5V ICC Active Mode Current in Reset (8XC196KD20) 80 92 mA XTAL1 e 20 MHz VCC e VPP e VREF e 5.5V IIDLE Idle Mode Current (8XC196KD) 17 25 mA XTAL1 e 16 MHz VCC e VPP e VREF e 5.5V IIDLE Idle Mode Current (8XC196KD20) 21 30 mA XTAL1 e 20 MHz VCC e VPP e VREF e 5.5V IPD Powerdown Mode Current 8 15 mA VCC e VPP e VREF e 5.5V IREF A/D Converter Reference Current 2 5 mA VCC e VPP e VREF e 5.5V RRST Reset Pullup Resistor CS Pin Capacitance (Any Pin to VSS) 6K 65K X 10 pF VCC e 5.5V, VIN e 4.0V NOTES: 1. All pins except RESET and XTAL1. 2. Violating these specifications in Reset may cause the part to enter test modes. 3. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7. 4. Standard Outputs include AD0±15, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4, TXD/P2.0 and RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs. 5. Standard Inputs include HSI pins, READY, BUSWIDTH, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4. 6. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held below VCC b 0.7V: IOL on Output pins: 10 mA IOH on quasi-bidirectional pins: self limiting IOH on Standard Output pins: 10 mA 7. Maximum current per bus pin (data and control) during normal operation is g 3.2 mA. 8. During normal (non-transient) conditions the following total current limits apply: IOH is self limiting Port 1, P2.6 IOL: 29 mA IOH: 26 mA HSO, P2.0, RXD, RESET IOL: 29 mA IOL: 13 mA IOH: 11 mA P2.5, P2.7, WR, BHE IOH: 52 mA AD0±AD15 IOL: 52 mA IOH: 13 mA RD, ALE, INST±CLKOUT IOL: 13 mA 11 8XC196KD/8XC196KD20 272145 ±5 ICC Max e 4.13 c Frequency a 9 mA ICC Typ e 3.50 c Frequency a 9 mA IIDLE Max e 1.25 c Frequency a 5 mA IIDLE Typ e 0.88 c Frequency a 3 mA NOTE: Frequencies below 8 MHz are shown for reference only; no testing is performed. Figure 7. I CC and I IDLE vs Frequency AC CHARACTERISTICS For use over specified operating conditions. Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16/20 MHz The system must meet these specifications Symbol Description to work with the 80C196KD: Min Max 2 TOSC b 68 Units Notes TAVYV Address Valid to READY Setup TYLYH Non READY Time TCLYX READY Hold after CLKOUT Low TLLYX READY Hold after ALE Low TAVGV Address Valid to Buswidth Setup TCLGX Buswidth Hold after CLKOUT Low TAVDV Address Valid to Input Data Valid 3 TOSC b 55 ns (Note 2) TRLDV RD Active to Input Data Valid TOSC b 22 ns (Note 2) TCLDV CLKOUT Low to Input Data Valid TOSC b 45 ns TRHDZ End of RD to Input Data Float TOSC ns TRXDX Data Hold after RD Inactive No upper limit 0 TOSC b 30 ns (Note 1) TOSC b 15 2 TOSC b 40 ns (Note 1) 2 TOSC b 68 0 0 NOTES: 1. If max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 TOSC * N, where N e number of wait states. 12 ns ns ns ns ns 8XC196KD/8XC196KD20 AC CHARACTERISTICS (Continued) For use over specified operating conditions. Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16/20 MHz The 80C196KD will meet these specifications: Symbol Description Min Max Units Notes FXTAL Frequency on XTAL1 (8XC196KD) 8 16 MHz (Note 1) FXTAL Frequency on XTAL1 (8XC196KD20) 8 20 MHz (Note 1) TOSC I/F XTAL (8XC196KD) 62.5 125 ns TOSC I/F XTAL (8XC196KD20) 50 125 ns TXHCH XTAL1 High to CLKOUT High or Low a 110 ns TCLCL CLKOUT Cycle Time a 20 2 TOSC ns TOSC b 10 TOSCa 15 TCHCL CLKOUT High Period TCLLH CLKOUT Falling Edge to ALE Rising b5 a 15 ns ns TLLCH ALE Falling Edge to CLKOUT Rising b 20 a 15 ns TLHLH ALE Cycle Time 4 TOSC TLHLL ALE High Period TOSC b 10 TAVLL Address Setup to ALE Falling Edge TOSC b 15 TLLAX Address Hold after ALE Falling Edge TOSC b 35 TLLRL ALE Falling Edge to RD Falling Edge TOSC b 30 TRLCL RD Low to CLKOUT Falling Edge TRLRH RD Low Period TRHLH RD Rising Edge to ALE Rising Edge TRLAZ RD Low to Address Float TLLWL ALE Falling Edge to WR Falling Edge TCLWL CLKOUT Low to WR Falling Edge a4 ns TOSCa 10 ns a 30 ns ns (Note 4) TOSC a 25 ns (Note 2) a5 ns TOSC b 10 0 ns ns TOSC b 5 TOSC ns a 25 ns a 15 ns TOSC b 23 TQVWH Data Stable to WR Rising Edge TCHWH CLKOUT High to WR Rising Edge TWLWH WR Low Period TOSC b 20 ns TWHQX Data Hold after WR Rising Edge TOSC b 25 ns TWHLH WR Rising Edge to ALE Rising Edge TOSC b 10 TWHBX BHE, INST after WR Rising Edge TOSC b 10 ns TWHAX AD8±15 HOLD after WR Rising TOSC b 30 ns TRHBX BHE, INST after RD Rising Edge TOSC b 10 ns TRHAX AD8±15 HOLD after RD Rising TOSC b 25 ns b5 (Note 4) (Note 4) TOSC a 15 ns (Note 4) (Note 2) (Note 3) (Note 3) NOTES: 1. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz. 2. Assuming back-to-back bus cycles. 3. 8-Bit bus only. 4. If wait states are used, add 2 TOSC * N, where N e number of wait states. 13 8XC196KD/8XC196KD20 System Bus Timings 272145 ±6 14 8XC196KD/8XC196KD20 READY Timings (One Wait State) 272145 ±7 Buswidth Timings 272145 ±8 15 8XC196KD/8XC196KD20 HOLD/HLDA TIMINGS Symbol Description THVCH HOLD Setup a 55 TCLHAL CLKOUT Low to HLDA Low b 15 a 15 ns TCLBRL CLKOUT Low to BREQ Low b 15 a 15 ns THALAZ HLDA Low to Address Float a 15 ns THALBZ HLDA Low to BHE, INST, RD, WR Weakly Driven a 20 ns TCLHAH CLKOUT Low to HLDA High b 15 a 15 ns TCLBRH CLKOUT Low to BREQ High b 15 a 15 THAHAX HLDA High to Address No Longer Float b 15 THAHBV HLDA High to BHE, INST, RD, WR Valid b 10 a 15 ns TCLLH CLKOUT Low to ALE High b5 a 15 ns Min Max Units ns Notes (Note 1) ns ns NOTE: 1. To guarantee recognition at next clock. DC SPECIFICATIONS IN HOLD Description Min Max Units Weak Pullups on ADV, RD, WR, WRL, BHE 50K 250K VCC e 5.5V, VIN e 0.45V Weak Pulldowns on ALE, INST 10K 50K VCC e 5.5V, VIN e 2.4 272145 ±9 16 8XC196KD/8XC196KD20 MAXIMUM HOLD LATENCY Bus Cycle Type Internal Execution 1.5 States 16-Bit External Execution 2.5 States 8-Bit External Execution 4.5 States EXTERNAL CLOCK DRIVE (8XC196KD) Symbol Parameter Min Max Units 1/T XLXL Oscillator Frequency TXLXL Oscillator Period TXHXX High Time 20 TXLXX Low Time 20 TXLXH Rise Time 10 ns TXHXL Fall Time 10 ns 8 16.0 62.5 125 MHz ns ns ns EXTERNAL CLOCK DRIVE (8XC196KD20) Symbol Parameter Min Max Units 1/T XLXL Oscillator Frequency 8 20.0 MHz TXLXL Oscillator Period 50 125 ns TXHXX High Time 17 ns TXLXX Low Time 17 ns TXLXH Rise Time 8 ns TXHXL Fall Time 8 ns EXTERNAL CLOCK DRIVE WAVEFORMS 272145 ±10 17 8XC196KD/8XC196KD20 EXTERNAL CRYSTAL CONNECTIONS EXTERNAL CLOCK CONNECTIONS 272145 ±13 NOTE: Keep oscillator components close to chip and use short, direct traces to XTAL1, XTAL2 and VSS. When using ceramic crystals, C1 e 20 pF, C2 e 20 pF. When using ceramic resonators consult manufacturer for recommended capacitor values. AC TESTING INPUT, OUTPUT WAVEFORMS 272145 ±11 AC Testing inputs are driven at 2.4V for a Logic ``1'' and 0.45V for a Logic ``0'' Timing measurements are made at 2.0V for a Logic ``1'' and 0.8V for a Logic ``0''. 272145 ±14 NOTE: *Required if TTL driver used. Not needed if CMOS driver is used. FLOAT WAVEFORMS 272145 ±12 For Timing Purposes a Port Pin is no Longer Floating when a 150 mV change from Load Voltage Occurs, and Begins to Float when a 150 mV change from the Loaded VOH/V OL Level occurs; IOL/I OH e g 15 mA. EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ``T'' for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: H - High L - Low Signals: A - Address B - BHE L - ALE/ADV BR - BREQ V - Valid X - No Longer Valid Z - Floating CD- CLKOUT DATA R - RD W - WR/WRH /WRL GH- Buswidth HOLD XYQ- HA - HLDA 18 XTAL1 READY Data Out 8XC196KD/8XC196KD20 AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE SERIAL PORT TIMING-SHIFT REGISTER MODE (MODE0) Symbol Parameter TXLXL Serial Port Clock Period (BRR t 8002H) TXLXH Serial Port Clock Falling Edge to Rising Edge (BRR t 8002H) TXLXL Serial Port Clock Period (BRR e 8001H) TXLXH Serial Port Clock Falling Edge to Rising Edge (BRR e 8001H) 2 TOSC b 50 TQVXH Output Data Valid to Clock Rising Edge 2 TOSC b 50 TXHQX Output Data Hold after Clock Rising Edge 2 TOSC b 50 TXHQV Next Output Data Valid after Clock Rising Edge TDVXH Input Data Setup to Clock Rising Edge TXHDX Input Data Hold after Clock Rising Edge TXHQZ Last Clock Rising to Output Float Min Max 6 TOSC 4 TOSC b 50 Units ns 4 TOSC a 50 ns 2 TOSC a 50 ns 4 TOSC ns ns ns 2 TOSC a 50 ns TOSC a 50 ns 0 ns 1 TOSC ns WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE SERIAL PORT WAVEFORM-SHIFT REGISTER MODE (MODE 0) 272145 ±15 19 8XC196KD/8XC196KD20 A to D CHARACTERISTICS The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF. 10-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max 0 a 70 Units TA Ambient Temperature Commercial Temp. TA Ambient Temperature Extended Temp. VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V VSS b 0.40 VCC a 0.40 -40 +85 §C °C ANGND Analog Ground Voltage TSAM Sample Time V TCONV Conversion Time 10 20 ms(1) FOSC Oscillator Frequency (8XC196KD) 8.0 16.0 MHz FOSC Oscillator Frequency (8XC196KD20) 8.0 20.0 MHz ms(1) 1.0 NOTE: 1. The value of AD_TIME is selected to meet these specifications. 10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions) Parameter (1) Typical Resolution Absolute Error Full Scale Error 0.25 g 0.5 Zero Offset Error 0.25 g 0.5 Non-Linearity 1.0 g 2.0 Differential Non-Linearity Error Channel-to-Channel Matching g 0.1 Minimum Maximum 1024 10 1024 10 0 g3 Units* Levels Bits LSBs LSBs LSBs 0 g3 LSBs l b1 a2 LSBs 0 g1 LSBs Repeatability g 0.25 LSBs Temperature Coefficients: Offset Full Scale Differential Non-Linearity 0.009 0.009 0.009 LSB/ § C LSB/ § C LSB/ § C Off Isolation Notes b 60 dB 2, 3 Feedthrough b 60 dB 2 VCC Power Supply Rejection b 60 dB 2 X 4 5, 6 Input Series Resistance Voltage on Analog Input Pin DC Input Leakage Sampling Capacitor 3 750 1.2K ANGND b 0.5 VREF a 0.5 V 0 g 3.0 mA pF NOTES: *An ``LSB'' as used here has a value of approxiimately 5 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms.) 1. These values are expected for most parts at 25§ C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if the pin current is limited to g 2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions performed with processor in IDLE mode. 20 8XC196KD/8XC196KD20 8-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max 0 a 70 Units TA Ambient Temperature Commercial Temp. TA §C Ambient Temperature Extended Temp. -40 +85 °C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V ANGND Analog Ground Voltage VSS b 0.40 VSS a 0.40 TSAM Sample Time TCONV Conversion Time FOSC FOSC V ms(1) 1.0 7 20 ms(1) Oscillator Frequency (8XC196KD) 8.0 16.0 MHz Oscillator Frequency (8XC196KD20) 8.0 20.0 MHz NOTE: 1. The value of AD_TIME is selected to meet these specifications. 8-BIT MODE A/D CHARACTERISTICS Parameter (1) Typical Resolution Absolute Error Full Scale Error g 0.5 Zero Offset Error g 0.5 Non-Linearity Differential Non-Linearity Error (Over Specified Operating Conditions) Minimum Maximum Units* 256 8 256 8 Levels Bits 0 g1 LSBs LSBs LSBs 0 g1 LSBs l b1 a1 LSBs Channel-to-Channel Matching g1 LSBs Repeatability g 0.25 LSBs Temperature Coefficients: Offset Full Scale Differential Non-Linearity 0.003 0.003 0.003 LSB/ § C LSB/ § C LSB/ § C Off Isolation b 60 Feedthrough b 60 VCC Power Supply Rejection b 60 Input Series Resistance Voltage on Analog Input Pin DC Input Leakage Sampling Capacitor 3 Notes dB 2, 3 dB 2 dB 2 750 1.2K X 4 VSS b 0.5 VREF a 0.5 V 5, 6 0 g 3.0 mA pF NOTES: *An ``LSB'' as used here has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25§ C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if pin current is limited to g 2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions performed with processor in IDLE mode. 21 8XC196KD/8XC196KD20 OTPROM SPECIFICATIONS OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature During Programming 20 30 C VCC Supply Voltage During Programming 4.5 5.5 V(1) VREF Reference Supply Voltage During Programming 4.5 5.5 V(1) VPP Programming Voltage 12.25 12.75 V(2) VEA EA Pin Voltage 12.25 12.75 V(2) FOSC Oscillator Frequency during Auto and Slave Mode Programming 6.0 8.0 MHz FOSC Oscillator Frequency during Run-Time Programming (8XC196KD) 6.0 16.0 MHz FOSC Oscillator Frequency during Run-Time Programming (8XC196KD20) 6.0 20.0 MHz NOTES: 1. VCC and VREF should nominally be at the same voltage during programming. 2. VPP and VEA must never exceed the maximum specification, or the device may be damaged. 3. VSS and ANGND should nominally be at the same potential (0V). 4. Load capacitance during Auto and Slave Mode programming e 150 pF. AC OTPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE) Symbol Description Min Max Units TSHLL Reset High to First PALE Low TLLLH PALE Pulse Width TAVLL TLLAX TPLDV PROG Low to Word Dump Valid 50 TOSC TPHDX Word Dump Data Hold 50 TOSC TDVPL Data Setup Time 0 TOSC TPLDX Data Hold Time 400 TOSC TPLPH(1) PROG Pulse Width 50 TOSC TPHLL PROG High to Next PALE Low 220 TOSC TLHPL PALE High to PROG Low 220 TOSC TPHPL PROG High to Next PROG Low 220 TOSC TPHIL PROG High to AINC Low 0 TOSC TILIH AINC Pulse Width 240 TOSC TILVH PVER Hold after AINC Low 50 TOSC TILPL AINC Low to PROG Low 170 TPHVL PROG High to PVER Valid 1100 TOSC 50 TOSC Address Setup Time 0 TOSC Address Hold Time 100 TOSC TOSC 220 TOSC NOTE: 1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm. 22 8XC196KD/8XC196KD20 DC OTPROM PROGRAMMING CHARACTERISTICS Symbol Description IPP VPP Supply Current (When Programming) Min Max Units 100 mA NOTE: Do not apply VPP until VCC is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. OTPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 272145 ±16 NOTE: P3.0 must be high (``1'') 23 8XC196KD/8XC196KD20 SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT 272145 ±17 NOTE: P3.0 must be low (``0'') SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND AUTO INCREMENT 272145 ±18 24 8XC196KD/8XC196KD20 8XC196KC TO 8XC196KD DESIGN CONSIDERATIONS 1. Memory Map. The 8XC196KD has 1024 bytes of RAM/SFRs and 32K of OTPROM. The extra 512 bytes of RAM reside in locations 0200H to 03FFH, and the extra 16 Kbytes of OTPROM reside in locations 6000H to 9FFFH. On the 87C196KC these locations are always external, so KC code may have to be modified to run on the KD. 2. The vertical window scheme has been extended to include all on-chip RAM. 3. IOC3.1 controls the CLKOUT signal. This bit must be 0 to enable CLKOUT. 4. The 87C196KD has a different autoprogramming algorithm to support 32K of on-chip OTPROM. 8XC196KD ERRATA 1. 83C196KD can possibly miss interrupts on P0.7. See techbit MC0893. DATA SHEET REVISION HISTORY This data sheet is valid for devices with a ``D'' and ``E'' at the end of the topside tracking number. Data sheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. The following are important differences between the 272145-004 and 272145-005 datasheets: 1. Package prefix variables have been changed. Variables are now indicated with an "x". The following are important differences between the 272145-002 and 272145-003 data sheets: 1. IIL1 specification (logic 0 input current in reset) was misnamed. It is renamed IIL2. 2. TLLYV and TLLGV were removed. These specifications are not necessary for high-speed system designs. 3. An errata with 83C196KD P0.7 EXTINT was added to the errata section. The following are important differences between the 272145-001 and 272145-002 data sheets: 1. Added 20 MHz specifications. 2. Added 80-lead SQFP package pinout. 3. Changed QFP Package iJA to 56§ C/W from 42§ C/W. 4. Changed VHYS to 300 mV from 150 mV. 5. Changed ICC Typical specification at 16 MHz to 65 mA from 50 mA. 6. Changed ICC Maximum specification at 16 MHz to 75 mA from 70 mA. 7. Changed IIDLE Typical specification to 17 mA from 15 mA. 8. Changed IIDLE Maximum specification to 25 mA from 30 mA. 9. Changed IPD Typical specification to 8 mA from 15 mA. 10. Added IPD Maximum specification. 11. Changed TCLDV Maximum specification to TOSC b 45 from TOSC b 50. 12. Changed TLLAX Minimum specification to TOSC b 35 from TOSC b 40. 13. Changed TCHWH Minimum specification to b 5 from b 10. 14. Changed TRHAX Minimum specification to TOSC b 25 from TOSC b 30. 15. Changed THALAZ Maximum specification to a 15 from a 10. 16. Changed THALBZ Maximum specification to a 20 from a 15. 17. Added THAHBV Maximum specification. 18. Changed TSAM for 10-bit mode to 1 ms from 3 ms. 19. Changed TSAM for 8-bit mode to 1 ms from 2 ms. 20. Changed IIH1 test condition to VIN e 2.4V from 5.5V. 21. Changed IIH1 maximum specification to a 200 mA from a 100 mA. 22. Removed NMI from list of standard inputs. 23. Updated ICC and IIDLE vs frequency graph. 24. Updated note under DC EPROM Programming Characteristics. 25. Changed ILI1 maximum specification to b 12 mA from b 6 mA. 25