ISSI IS75V16F128GS32

ISSI
®
IS75V16F128GS32
3.0 Volt Multi-Chip Package (MCP)
— 128 Mbit Simultaneous Operation Flash
Memory and 32 Mbit Pseudo Static RAM
PRELIMINARY INFORMATION
MARCH 2003
MCP FEATURES
• Power supply voltage 2.7V to 3.3V
• High performance:
Flash: 70ns maximum access time
PSRAM: 65ns maximum access time
• Package: 107-ball BGA
• Operating Temperature: -30C to +85C
• Erase Algorithms:
Automatically preprograms/erases the flash memory
entirely, or by sector
• Program Algorithms:
Automatically writes and verifies data at specified
address
• Hidden ROM Region:
FLASH FEATURES
• Power Dissipation:
Read Current at 1 Mhz: 4 mA maximum
Read Current at 5 Mhz:18 mA maximum
Sleep Mode: 5 µA maximum
• User Configurable Banks
Flash 1 (64 Mbit)
Bank A1: 8Mbit (8KB x 8 and 64KB x 15)
Bank B1: 24Mbit (64KB x 48)
Bank C1: 24Mbit (64KB x 48)
Bank D1: 8Mbit (8KB x 8 and 64KB x 15)
Flash 2 (64 Mbit)
Bank A2: 8Mbit (8KB x 8 and 64KB x 15)
Bank B2: 24Mbit (64KB x 48)
Bank C2: 24Mbit (64KB x 48)
Bank D2: 8Mbit (8KB x 8 and 64KB x 15)
User chooses two virtual banks from a
combination of four physical banks
• Simultaneous R/W Operations (dual virtual bank):
Zero latency between read and write operations; Data
can be programmed or erased in one bank while data
is simultaneously being read from the other bank
• Low-Power Mode:
A period of no activity causes flash to enter a
low-power state
• Erase Suspend/Resume:
Suspends of erase activity to allow a read in the
same bank
256 byte with a Factory-serialized secure electronic
serial number (ESN), which is accessible through a
command sequence
• Data Polling and Toggle Bit:
Detects the completion of the program or erase cycle
• Ready-Busy Outputs (RY/BY)
Detection of program or erase cycle completion for
each flash chip
• Over 100,000 write/erase cycles
• Low supply voltage (Vccf ≤ 2.5V) inhibits writes
• WP/ACC input pin:
If VIL, allows partial protection of boot sectors
If VIH, allows removal of boot sector protection
If Vacc, program time is improved
PSRAM FEATURES (32 Mb density)
• Power Dissipation:
Operating: 25 mA maximum
Standby: 110 µA maximum
• Chip Selects: CE1r, CE2r
• Power down feature using CE2r
Sleep Mode: 10 µA maximum
Nap: 65 µA maximum
8 mbit Partial: 80 µA maximum
• Data retention supply voltage: 2.1 V to 3.3V
• Byte data control: LB (DQ0–DQ7), UB
(DQ8–DQ15)
• Sector Erase Architecture:
16 sectors of 4K words each and 126 sectors of 32K words
each in Word mode. Any combination of sectors, or
the entire flash can be simultaneously erased
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark
of Fujitsu Limited, Japan. Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
1
ISSI
IS75V16F128GS32
®
GENERAL DESCRIPTION
This 107-ball MCP is a space-saving combination of 3 memories: two 64Mbit Flash and one 32Mbit Pseudo SRAM.
Each 64Mbit Flash (Flash1 and Flash 2) contains 4,194,304 words and the 32Mbit PSRAM contains 2,097,152
words. Each word is 16 bits wide. Data lines DQ0-DQ15 handle the access for all three memories. Write Enable,
Output Enable, and A0-A20 are shared among the three memories. Single Byte data on the PSRAM can be
accessed one at a time on DQ0-DQ7 or DQ8-DQ15 by using LB or UB, respectively.
The package uses a 3.0V power supply for all operations. No other source is required for program and erase operations.
The flash can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM
programmer.
The flash chips are compatible with the JEDEC Flash command set standard. The flash access time is 70ns and the
PSRAM access time is 65ns.
Each Flash memory implements an architecture composed of two virtual banks that allows simultaneous operation on
each bank. Optimized performance can be achieved by first initializing a program or erase function in one bank, then
immediately starting a read from the other bank. Both operations would then be operating simultaneously on the same
chip, with zero latency.
MCP BLOCK DIAGRAM
VCCf1 GND
A0-A21
RESET1
CEf1
RY/BY1
64-MBIT
Flash Memory
(Flash 1)
VCCf2 GND
A0-A21
A0-A21
RY/BY2
WP/ACC
32-MBIT
Flash Memory
RESET2
CEf2
(Flash 2)
VCCr
DQ0-DQ15
GND
A0-A20
LB
UB
WE
OE
CE1r
CE2r
PE
2
32-MBIT
PSRAM
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
PIN CONFIGURATION (128 Mb Flash and 32 Mb PSRAM)
PACKAGE CODE: B 107 BALL FBGA (Top View) (9.00 mm x 10.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
L
M
NC
NC
GND RY/BY2 CEf2
NC
NC
A8
NC
NC
NC
NC
A11 NC
NC
NC
NC
NC
A7
LB WP/ACC WE
NC
A3
A6
UB RESET1 CE2r A19
A12 A15
NC
NC
A2
A5
A18 RY/BY1 A20
A9
A13 A21
NC
NC
A1
A4
A17
DU
DU
A10
A14
NC
NC
NC
A0
GND DQ1
DU
DU
DQ6
PE
A16
NC
NC
CEf1
OE
DQ3 DQ4 DQ13 DQ15 Vccf1
NC
NC
CE1r DQ0 DQ10 Vccf1 Vccr DQ12 DQ7 GND
NC
DQ9
Shared
DQ8 DQ2 DQ11 NC
NC
NC
NC
NC RESET2 GND Vccf2
NC
NC
DQ5 DQ14 NC
NC
NC
NC
NC
NC
Flash Only
NC
NC
NC
PSRAM Only
PIN DESCRIPTIONS
A0-A20
Address Inputs, Common
LB
Lower-byte Control, PSRAM
A21
Address Input, Both Flash
UB
Upper-byte Control, PSRAM
DQ0-DQ15
Data Inputs/Outputs, Common
WP/ACC
Write Protect/Acceleration Pin, Both Flash
RESET1
Reset, Flash1
RY/BY1
Ready/Busy Output , Flash1
RESET2
Reset, Flash2
RY/BY2
Ready/Busy Output , Flash2
CE1r, CE2r
Chip Enable, PSRAM
NC
No Connection
CEf1
Chip Enable, Flash1
DU
Do Not Use
CEf2
Chip Enable, Flash2
Vccf1
Power, Flash1
OE
Output Enable, Common
Vccf2
Power, Flash2
WE
Write Enable, Common
Vccr
Power, PSRAM
PE
Partial Enable, PSRAM
GND
Ground, Common
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
3
ISSI
IS75V16F128GS32
®
DEVICE BUS OPERATION
OPERATION(1,2) CEf1 CEf2 CE1r CE2r OE WE LB s UB s PE A21-A0 DQ7-DQ0 DQ15-DQ8 RESET1 RESET2 WP
WP/ACC(12)
Full Standby
H
(3)
H
H
H
X
X
X
X
H
X
High-Z
High-Z
H
H
X
(10)
High-Z High-Z
High-Z High-Z
High-Z High-Z
H
H
H
H
H
H
X
X
X
H
L
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
H
H
H
Read from FLASH 1(4)L
H
H
H
L
H
X
X
H Valid
DOUT
DOUT
H
H
X
Read from FLASH 2(4)H
Write to FLASH 1
L
L
H
H
H
H
H
L
H
H
L
X
X
X
X
H Valid
H Valid
DOUT
DIN
DOUT
DIN
H
H
H
H
X
X
Write to FLASH 2
L
H
H
H
L
X
X
H Valid
DIN
DIN
H
H
X
Output Disable
Read from PSRAM
H
(5)
(9)
(9)
X
X
X
H
H
L
H
L
H
L
L
H Valid
DOUT
DOUT
H
H
X
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L
L
H
H Valid
H Valid
H Valid
DIN
High-Z
DIN
DIN
DIN
High-Z
H
H
H
H
H
H
X
X
X
FLASH 1Temporary
Sector Group
X
(6)
Unprotection
X
X
X
X
X
X
X
X
X
X
X
VID
X
X
FLASH 2 Temporary
Sector Group
X
Unprotection(6)
X
X
X
X
X
X
X
X
X
X
X
X
VID
X
Write to PSRAM
FLASH 1
Hardware Reset
X
X
H
H
X
X
X
X
X
X
High-Z
High-Z
L
X
X
FLASH 2
Hardware Reset
X
X
H
H
X
X
X
X
X
X
High-Z
High-Z
X
L
X
Boot Block Sector
Write Protection
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
PSRAM Power(7)
Down Program
H
H
H
H
X
X
X
X
L
Valid
PSRAM No Read
H
H
L
H
L
H
H
H
H Valid
PSRAM
Power Down(8)
X
X
X
L
X
X
X
X
X
X
High-Z High-Z
H
H
X
High-Z
High-Z
H
H
X
X
X
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “DC CHARACTERISTICS” for voltage levels.
Notes:
1. Other operations except for indicated this column are prohibited.
2. Do not apply CEf = VIL, CE1r = VIL and CE2r = VIH all at once.
3. PSRAM Output Disable condition should not be kept longer than 1ms.
4. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
5. PSRAM LB,UB control at Read operation is not supported.
6. It is also used for the extended sector group protections.
7. The PSRAM Power Down Program can be performed one time after compliance of Power-UP timings and it should not be reprogrammed after regular Read or Write.
8. PSRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. IPDr current and data retention
depends on the selection of Power Down Program.
9. Either or both LB and UB must be Low for PSRAM Read Operation.
10. Can be either VIL or VIH but must be valid before Read or Write.
11. See “ PSRAM Power Down Program Key Table “ located in the next page.
12. Protect “ outer most “ 2x8K bytes ( 4 words ) on both ends of the boot block sectors.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
ABSOLUTE MAXIMUM RATINGS(1,5)
Rating
Symbol
Tstg
TA
Parameter
Storage Temperature
Ambient Temperature with Power Applied
Min.
–55
–30
Max.
+125
+85
Unit
°C
°C
VIN,VOUT
Voltage with Respect to Ground All Pins(2)
–0.3
VCC + 0.3(6)
V
VCCf1,VCCf2
VCCf Supply
(2)
–0.3
3.5
V
VCCr
VCCr Supply(2)
–0.3
3.5
V
VIN
RESET1, RESET2(3)
-0.5
+13.0
V
(4)
–0.5
+10.5
V
VACC
WP/ACC
Notes:
1. Voltage is defined on the basis of GND = 0 V.
2. Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot
GND to -1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf1+ 0.3V , VCCf2+ 0.3V
or VCCr + 0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf1+ 2.0V , VCCf2+ 2.0 V or VCCr + 1.0 V
for periods of up to 20 ns.
3. Minimum DC input voltage on RESET1 or RESET2 pin is -0.5 V. During voltage transitions, RESET1 or RESET2 pin may
undershoot GND to -2.0 V for periods of up to 20 ns.
The voltage difference between input and supply voltage (VIN-VCCf1 or VCCf2) does not exceed 9.0 V.
The maximum DC input voltage on the RESET pin is +13.0 V that may overshoot to +14.0 V for periods of up to 20 ns.
4. Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot
GND to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf1 or VCCf2 is applied.
5. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
6. This Vcc refers to the minimum of VCCf1, VCCf2, or Vccr .
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
TA
VCCf1,VCCf2
VCCr
Parameter
Ambient Temperature
VCCf Supply Voltages
VCCr Supply Voltages
Min.
–30
2.7
2.7
Max.
+85
3.3
3.3
Unit
°C
V
V
Note:
Voltage is defined on the basis of GND = 0 V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
5
ISSI
IS75V16F128GS32
®
DC CHARACTERISTICS
Symbol
ILI
ILO
ILIT
ICC1f
ICC2f
ICC3f
ICC4f
ICC5f
IACC
ICC1r
ISB1f
6
Parameter
Input Leakage
Output Leakage
RESET Inputs
Leakage Current
FLASH Vcc (1)
Active Current (Read)
Test Conditions
VIN=GND to VCCf, VCCr
VOUT=GND to VCCf, VCCr
VCCf=VCCf max.,
RESET = 12.5V
CEf=VIL, OE=VIH
tCycle = 5Mhz
tCycle = 1Mhz
FLASH Vcc Active(2)
CEf=VIL,
Current(Program/Erase) OE=VIH
FLASH Vcc Active(5)
CEf=VIL,
Current
OE=VIH
(Read-While-Program)
FLASH Vcc Active(5)
CEf=VIL,
Current
OE=VIH
(Read-While-Erase)
FLASH Vcc Active
CEf=VIL,
Current
OE=VIH
(Erase-Suspend-Program)
WP/ACC Acceleration
VCCf = Vcc max,
Program Current
WP/ACC = VACC max
PSRAM Vcc Active
VCCr = Vccr max,
trc / twc = min
Current
CE1r=VIL, CE2r=VIH,
VIN=VIH or VIL,
trc / twc = 1 µs
IOUT=0 mA
FLASH Vcc
VCCf = Vccf max, CEf= VCCf + 0.3V,
(7)
Standby Current
RESET = VCCf + 0.3V,
WP/ACC = VCCf + 0.3V
Min.
-1.0
-1.0
—
Typ.
—
—
—
Max.
+1.0
+1.0
35
Unit
µA
µA
µA
—
—
18
mA
—
—
—
—
4
35
mA
mA
—
—
53
mA
—
—
53
mA
—
—
40
mA
—
—
20
mA
—
—
25
mA
—
—
3
mA
—
1
5
µA
ISB2f
FLASH Vcc (7)
Standby Current
(RESET)
VCCf = Vccf max, RESET= GND + 0.3V,
WP/ACC = VCCf + 0.3V
—
1
5
µA
ISB3f
FLASH Vcc (3,7)
Current
(Automatic Sleep Mode)
VCCf = Vccf max, CEf = GND + 0.3V,
RESET = VCCf + 0.3V,
WP/ACC = VCCf + 0.3V,
VIN = VCCf + 0.3V OR GND + 0.3V
—
1
5
µA
ISB1r
PSRAM Vcc Standby(8)
Current
—
110
µA
IPDSr
PSRAM VCC Power
Down Current
(Sleep Mode)
VCCr = Vccr max, CE1r ≥ VCCr -0.2V,
CE2r ≥ VCCr -0.2V,
VIN ≤ 0.2 V or VIN ≥ VCCr -0.2V
VCCr = VCCr max.,
CE1r ≥ VCCr - 0.2 V
CE2r ≤ 0.2 V, VIN Cycle time = tRC min
—
—
10
µA
IPDNr
PSRAM VCC Power (8)
Down Current
(Nap Mode)
VCCr = VCCr max.,
CE1r ≥ VCCr - 0.2 V
CE2r ≤ 0.2 V, VIN Cycle time = tRC min
—
—
65
µA
—
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
DC CHARACTERISTICS (Continued)
Symbol Parameter
IPD8r
VIL
VIH
VIH
VID
VACC
VOL
VOH
VOL
VOH
VLKO
Test Conditions
Min.
PSRAM VCC Power
VCCr = VCCr max.,
—
Down Current
CE1r ≥ VCCr - 0.2 V
(8M Partial)(8)
CE2r ≤ 0.2 V, VIN Cycle time = tRC min
Input Low Level
-0.3
Input High Level (FLASH 1 or FLASH 2 )
VCCf X 0.75
Input High Level (PSRAM)
VCCr X 0.75
Voltage for Sector Protection
11.5
and Temp. Unprotection(RESET)(4)
Voltage for WP/ACC
8.5
Sector Protection/Unprotection
and Program Acceleration (4)
Output Low Level
VCCr = VCCr min., VCCS=VCCS min.
—
(PSRAM)
IOL = 1.0 mA
Output High Level
VCCr = VCCr min., VCCS=VCCS min.
2.2
(PSRAM)
IOH = -0.5 mA
Output Low Level
VCCf = VCCf min., VCCS=VCCS min.
—
(Flash)
IOL = 4.0 mA
Output High Level
VCCf = VCCf min., VCCS=VCCS min.
VCCf - 0.4
(Flash)
IOH = -0.1 mA
FLASH Low Vccf
2.3
Lock-Out Voltage
Typ.
Max.
Unit
—
80
µA
—
—
—
—
0.5
VCCf + 0.3
VCCr + 0.3
12.5
V
V
V
V
9.0
9.5
V
—
0.4
V
—
—
V
—
0.45
V
—
—
V
2.4
2.5
V
Notes:
1. ICC current listed includes both the DC operating current and the frequency dependent component.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
4. Applicable for only VCCf applying.
5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
6. ISB2 r depends on VIN cycle time. Please refer to “APPENDIX A”.
7. Standby current listed is for each FLASH chip.
8. Standby and Power down currents are reduced with Vccr < 3.0 V .
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
7
ISSI
IS75V16F128GS32
®
AC CHARACTERISTICS - CE TIMING
Parameter
Symbol
Condition
tCCR
—
0
—
ns
CEf Hold Time
tCHOLD
—
3
—
ns
CE1r High to WE Invalid time for
Standby Entry
tCHWX
—
10
—
ns
CEf Recover Time
Min Max
Unit
TIMING DIAGRAM FOR ALTERNATING PSRAM TO FLASH 1 OR FLASH 2
CEf
tCCR
tCCR
CE1r
WE
tCHWX
tCCR
tCHOLD
tCCR
CE2r
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH 1 or FLASH 2
Sector
Bank
Address
Sector
K-Word
Address
Bank
Address
K-Word
Address
Bank A
SA0
4
000000h
Bank B
SA36
32
0E8000h
Bank A
SA1
4
001000h
Bank B
SA37
32
0F0000h
Bank A
SA2
4
002000h
Bank B
SA38
32
0F8000h
Bank A
SA3
4
003000h
Bank B
SA39
32
100000h
Bank A
SA4
4
004000h
Bank B
SA40
32
108000h
Bank A
SA5
4
005000h
Bank B
SA41
32
110000h
Bank A
SA6
4
006000h
Bank B
SA42
32
118000h
Bank A
SA7
4
007000h
Bank B
SA43
32
120000h
Bank A
SA8
32
008000h
Bank B
SA44
32
128000h
Bank A
SA9
32
010000h
Bank B
SA45
32
130000h
Bank A
SA10
32
018000h
Bank B
SA46
32
138000h
Bank A
SA11
32
020000h
Bank B
SA47
32
140000h
Bank A
SA12
32
028000h
Bank B
SA48
32
148000h
Bank A
SA13
32
030000h
Bank B
SA49
32
150000h
Bank A
SA14
32
038000h
Bank B
SA50
32
158000h
Bank A
SA15
32
040000h
Bank B
SA51
32
160000h
Bank A
SA16
32
048000h
Bank B
SA52
32
168000h
Bank A
SA17
32
050000h
Bank B
SA53
32
170000h
Bank A
SA18
32
058000h
Bank B
SA54
32
178000h
Bank A
SA19
32
060000h
Bank B
SA55
32
180000h
Bank A
SA20
32
068000h
Bank B
SA56
32
188000h
Bank A
SA21
32
070000h
Bank B
SA57
32
190000h
Bank A
SA22
32
078000h
Bank B
SA58
32
198000h
Bank B
SA23
32
080000h
Bank B
SA59
32
1A0000h
Bank B
SA24
32
088000h
Bank B
SA60
32
1A8000h
Bank B
SA25
32
090000h
Bank B
SA61
32
1B0000h
Bank B
SA26
32
098000h
Bank B
SA62
32
1B8000h
Bank B
SA27
32
0A0000h
Bank B
SA63
32
1C0000h
Bank B
SA28
32
0A8000h
Bank B
SA64
32
1C8000h
Bank B
SA29
32
0B0000h
Bank B
SA65
32
1D0000h
Bank B
SA30
32
0B8000h
Bank B
SA66
32
1D8000h
Bank B
SA31
32
0C0000h
Bank B
SA67
32
1E0000h
Bank B
SA32
32
0C8000h
Bank B
SA68
32
1E8000h
Bank B
SA33
32
0D0000h
Bank B
SA69
32
1F0000h
Bank B
SA34
32
0D8000h
Bank B
SA70
32
1F8000h
Bank B
SA35
32
0E0000h
Bank C
SA71
32
200000h
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
9
ISSI
IS75V16F128GS32
®
FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH 1 or FLASH 2 (Continued)
Sector
Bank
Address
Sector
K-Word
Address
Bank
Address
K-Word
Address
Bank C
SA72
32
208000h
Bank C
SA107
32
320000h
Bank C
SA73
32
210000h
Bank C
SA108
32
328000h
Bank C
SA74
32
218000h
Bank C
SA109
32
330000h
Bank C
SA75
32
220000h
Bank C
SA110
32
338000h
Bank C
SA76
32
228000h
Bank C
SA111
32
340000h
Bank C
SA77
32
230000h
Bank C
SA112
32
348000h
Bank C
SA78
32
238000h
Bank C
SA113
32
350000h
Bank C
SA79
32
240000h
Bank C
SA114
32
358000h
Bank C
SA80
32
248000h
Bank C
SA115
32
360000h
Bank C
SA81
32
250000h
Bank C
SA116
32
368000h
Bank C
SA82
32
258000h
Bank C
SA117
32
370000h
Bank C
SA83
32
260000h
Bank C
SA118
32
378000h
Bank C
SA84
32
268000h
Bank D
SA119
32
380000h
Bank C
SA85
32
270000h
Bank D
SA120
32
388000h
Bank C
SA86
32
278000h
Bank D
SA121
32
390000h
Bank C
SA87
32
280000h
Bank D
SA122
32
398000h
Bank C
SA89
32
290000h
Bank D
SA124
32
3A8000h
Bank C
SA90
32
298000h
Bank D
SA125
32
3B0000h
Bank C
SA91
32
2A0000h
Bank D
SA126
32
3B8000h
Bank C
SA92
32
2A8000h
Bank D
SA127
32
3C0000h
Bank C
SA93
32
2B0000h
Bank D
SA128
32
3C8000h
Bank C
SA94
32
2B8000h
Bank D
SA129
32
3D0000h
Bank C
SA95
32
2C0000h
Bank D
SA130
32
3D8000h
Bank C
SA96
32
2C8000h
Bank D
SA131
32
3E0000h
Bank C
SA97
32
2D0000h
Bank D
SA132
32
3E8000h
Bank C
SA98
32
2D8000h
Bank D
SA133
32
3F0000h
Bank C
SA99
32
2E0000h
Bank D
SA134
4
3F8000h
Bank C
SA100
32
2E8000h
Bank D
SA135
4
3F9000h
Bank C
SA101
32
2F0000h
Bank D
SA136
4
3FA000h
Bank C
SA102
32
2F8000h
Bank D
SA137
4
3FB000h
Bank C
SA103
32
300000h
Bank D
SA138
4
3FC000h
Bank C
SA104
32
308000h
Bank D
SA139
4
3FD000h
Bank C
SA105
32
310000h
Bank D
SA140
4
3FE000h
Bank C
SA106
32
318000h
Bank D
SA141
4
3FF000h
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
USER CONFIGURABLE BANK ARCHITECTURE TABLE - FLASH 1 or FLASH 2
Virtual Bank 1
Virtual Bank 2
Bank Split
Volume
Combination
Volume
Combination
Choice 1
8 Mbit
Bank A
56 Mbit
Bank B, C, D
Choice 2
24 Mbit
Bank B
40 Mbit
Bank A, C, D
Choice 3
24 Mbit
Bank C
40 Mbit
Bank A, B, D
Choice 4
8 Mbit
Bank D
56 Mbit
Bank A, B, C
EXAMPLE OF VIRTUAL BANKS COMBINATION TABLE - FLASH 1 or FLASH 2
Virtual Bank 1
Virtual Bank 2
Bank Split Volume
Combination
Sector Size
Volume
Combination
Sector Size
Choice 1
Bank A
8x4 Kword
56 Mbit
Bank B, C, D
8x4 Kword
8 Mbit
15x32 Kword
Choice 2
16 Mbit
Bank A,D
16x4 Kword
111x32 Kword
48 Mbit
Bank B,C
96x32 Kword
40 Mbit
Bank A, C, D
16x4 Kword
30x32 Kword
Choice 3
24 Mbit
Bank B
48x32 Kword
78x32 Kword
Choice 4
32 Mbit
Bank A,B
8x4 Kword
32 Mbit
63x32 Kword
Bank C,D
8x4 Kword
63x32 Kword
Notes:
1) When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being
erased belongs. For example, if erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out. They
would output the sequence flag once they were selected. Meanwhile the system would get to read from either Bank C or Bank D.
2) Each word is made-up of 2 bytes: one upper byte and one lower byte. A KWord is 210 words.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
11
ISSI
IS75V16F128GS32
®
SIMULTANEOUS OPERATION TABLE - FLASH 1 or FLASH 2
Case
Virtual Bank 1 Status
Virtual Bank 2 Status
1
Read Mode
Read Mode
2
Read Mode
Autoselect Mode
3
Read Mode
Program Mode
4
Read Mode
Erase Mode (1)
5
Autoselect Mode
Read Mode
6
Program Mode
Read Mode
7
Note:
Erase Mode
(1)
Read Mode
1) By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it
enables reading from or programming the remaining sectors.
2) Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks,
Bank A, Bank B, Bank C, and Bank D. Bank Address (BA) means to specify each of the Banks.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2
Bank Address
Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Word Mode
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
13
ISSI
IS75V16F128GS32
®
SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 (Continued)
Bank Address
Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Word Mode
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
14
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 (Continued)
Bank Address
Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Word Mode
Bank B
Bank B
Bank B
Bank B
Bank B
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
200000h to 207FFFh
208000h to 20FFFFh
210000h to 217FFFh
218000h to 21FFFFh
220000h to 227FFFh
228000h to 22FFFFh
230000h to 237FFFh
238000h to 23FFFFh
240000h to 247FFFh
248000h to 24FFFFh
250000h to 257FFFh
258000h to 25FFFFh
260000h to 267FFFh
268000h to 26FFFFh
270000h to 277FFFh
278000h to 27FFFFh
280000h to 287FFFh
288000h to 28FFFFh
290000h to 297FFFh
298000h to 29FFFFh
2A0000h to 2A7FFFh
2A8000h to 2AFFFFh
2B0000h to 2B7FFFh
2B8000h to 2BFFFFh
2C0000h to 2C7FFFh
2C8000h to 2CFFFFh
2D0000h to 2D7FFFh
2D8000h to 2DFFFFh
2E0000h to 2E7FFFh
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
15
ISSI
IS75V16F128GS32
®
SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 (Continued)
Bank Address
Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Word Mode
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2E8000h to 2EFFFFh
2F0000h to 2F7FFFh
2F8000h to 2FFFFFh
300000h to 307FFFh
308000h to 30FFFFh
310000h to 317FFFh
318000h to 31FFFFh
320000h to 327FFFh
328000h to 32FFFFh
330000h to 337FFFh
338000h to 33FFFFh
340000h to 347FFFh
348000h to 34FFFFh
350000h to 357FFFh
358000h to 35FFFFh
360000h to 367FFFh
368000h to 36FFFFh
370000h to 377FFFh
378000h to 37FFFFh
380000h to 387FFFh
388000h to 38FFFFh
390000h to 397FFFh
398000h to 39FFFFh
3A0000h to 3A7FFFh
3A8000h to 3AFFFFh
3B0000h to 3B7FFFh
3B8000h to 3BFFFFh
3C0000h to 3C7FFFh
3C8000h to 3CFFFFh
3D0000h to 3D7FFFh
3D8000h to 3DFFFFh
3E0000h to 3E7FFFh
3E8000h to 3EFFFFh
3F0000h to 3F7FFFh
3F8000h to 3F8FFFh
3F9000h to 3F9FFFh
3FA000h to 3FAFFFh
3FB000h to 3FBFFFh
3FC000h to 3FCFFFh
3FD000h to 3FDFFFh
3FE000h to 3FEFFFh
3FF000h to 3FFFFFh
16
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
SECTOR ADDRESS GROUP TABLE - FLASH 1 or FLASH 2
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sectors
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SGA8
0
0
0
0
0
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
SGA25
SGA26
SGA27
SGA28
SGA29
SGA30
SGA31
SGA32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
X
X
X
SA8 to SA10
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA11 to SA14
SA15 to SA18
SA19 to SA22
SA23 to SA26
SA27 to SA30
SA31 to SA34
SA35 to SA38
SA39 to SA42
SA43 to SA46
SA47 to SA50
SA51 to SA54
SA55 to SA58
SA59 to SA62
SA63 to SA66
SA67 to SA70
SA71 to SA74
SA75 to SA78
SA79 to SA82
SA83 to SA86
SA87 to SA90
SA91 to SA94
SA95 to SA98
SA99 to SA102
SA103 to SA106
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
17
ISSI
IS75V16F128GS32
®
SECTOR ADDRESS GROUP TABLE - FLASH 1 or FLASH 2 (Continued)
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sectors
SGA33
SGA34
SGA35
SGA36
SGA37
SGA38
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
SGA39
1
1
1
1
1
SGA40
SGA41
SGA42
SGA43
SGA44
SGA45
SGA46
SGA47
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
0
0
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA107 to SA110
SA111 to SA114
SA115 to SA118
SA119 to SA122
SA123 to SA126
SA127 to SA130
X
X
X
SA131 to SA133
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
FLASH MEMORY AUTOSELECT CODES TABLE - FLASH 1 or FLASH 2
Type
A21 to A12
A6
A3
A2
A1
A0
Code (HEX)
Manufacturer's Code
BA
L
L
L
L
L
04h
Device Code
BA
L
L
L
L
H
227Eh
Extended Device
BA
L
H
H
H
L
2202h
BA
L
H
H
H
H
2201h
L
L
L
H
L
01h(1)
(2)
Code
Sector Group
Protection
Sector Group
Address
Legend: L = VIL, H = VIH. See “ DC CHARACTERISTICS” for voltage levels.
Notes:
1. Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
2. A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will require two
additional codes, called Extended Device Codes. Therefore the system may continue reading out these Extended Device Codes
at the address of (BA) 0Eh, as well as at (BA) 0Fh.
.
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
FLASH MEMORY COMMAND DEFINITIONS - FLASH 1 or FLASH 2
First Bus
Cycle
Second Bus
Write Cycle
Bus
Write
Cycle
Req'd
Addr.
Data
Addr.
Data
(1)
1
XXXh
F0h
—
—
Read / Reset (1)
3
555h
AAh
2AAh
55h
Autoselect
3
555h
AAh
2AAh
Program
4
555h
AAh
2AAh
Program Suspend
1
BA
B0h
—
Program Resume
1
BA
30h
Chip Erase
6
555h
AAh
Command
Sequence
Read / Reset
Third Bus
Write Cycle
Fourth Bus
Read/Write
Data
Addr.
Data
—
—
—
555h
F0h
RA
55h
(BA)
555h
90h
55h
555h
—
—
2AAh
Fifth Bus
Cycle
Data
Addr.
Data
—
—
—
—
RD
—
—
—
—
—
—
—
—
—
—
A0h
PA
PD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
55h
555h
80h
555h
AAh
2AAh
55h
555h
10h
—
—
—
—
—
Addr.
—
—
Addr.
Sixth Bus
Cycle
—
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
BA
B0h
—
—
—
—
—
—
1
BA
30h
—
—
—
—
—
—
Extended Sector
Group Protection
4
XXXh
60h
SGA
60h
SGA
40h
SGA
SD
—
—
—
—
Set to Fast
Mode (2)
3
555h
AAh
2AAh
55h
555h
20h
—
—
—
—
—
—
(2)
2
XXXh
A0h
PA
PD
—
—
—
—
—
—
—
Reset from Fast
Mode (2)
2
BA
90h
XXXh
(6)
F0H
—
—
—
—
—
—
—
(4)
1
(BA)
55h
98h
—
—
—
—
—
—
3
555h
AAh
2AAh
55h
555h
88h
—
—
—
—
4
555h
AAh
2AAh
55h
555h
A0h
(HRA)
PA
PD
—
—
—
—
4
555h
AAh
2AAh
55h
90h
XXXh
00h
—
—
—
—
Sector Erase
6
555h
Erase Suspend
1
Erase Resume
(3)
Fast Program
Query
Hi-ROM
Entry
Hi-ROM
Program
Hi-ROM
Exit (5)
(5)
(HRBA)
555h
55h
SA
30h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Notes:
1. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
2. This command is valid during Fast Mode.
3. This command is valid while RESET = VID
4. The valid address is A6 to A0.
5. This command is valid during Hi-ROM mode.
6. The data “00h” is also acceptable.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
19
ISSI
IS75V16F128GS32
®
FLASH MEMORY COMMAND DEFINITIONS - FLASH 1 or FLASH 2 (Continued)
Notes:
• Address bits A21 to A11 = X = “H” or “L” for all
address commands except or Program Address
(PA), Sector Address (SA), and Bank Address
(BA), and Sector Group Address (SPA).
• Bus operations are defined in "DEVICE BUS
OPERATIONS”.
• RA = Address of the memory location to be read
PA = Address of the memory location to be
programmed. Addresses are latched on the falling
edge of the write pulse.
• SA = Address of the sector to be erased. The
combination of A21, A20, A19, A18, A17, A16,
A15, A14, A13, and A12 will uniquely select any
sector. BA = Bank Address (A21, A20, A19)
• SPA = Sector group address to be protected.
Set sector group address and (A6, A3, A2, A1,
A0) = (0, 0, 0, 1, 0).
SD = Sector group protection verify data.
Output 01h at protected sector group
addresses and output 00h at unprotected
sector group addresses.
• HRA = Address of the Hi-ROM area :
000000h to 00007Fh
HRBA = Bank Address of the Hi-ROM area
(A21 = A20 = A19 = VIL)
• The system should generate the following address
patterns : 555h or 2AAh to addresses A10 to A0
• Both Read/Reset commands are functionally
equivalent, resetting the device to the read mode.
• RD = Data read from location RA during read
operation.
PD = Data to be programmed at location PA. Data
is latched on the rising edge of the write pulse.
20
• Command combinations not described in FLASH
Memory Command Definitions are illegal.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
FLASH READ ONLY OPERATIONS CHARACTERISTICS - FLASH 1 or FLASH 2
JEDEC
Symbol
Standard
Symbol
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
tACC
Chip Enable to Output Delay
tELQV
tCE
Output Enable to Output Delay
tGLQV
Chip Enable to Output High-Z
Parameter
Condition
Min Max
Unit
70
—
ns
CEf = VIL, OE = VIL
—
70
ns
OE = VIL
—
70
ns
tOE
—
30
ns
tEHQZ
tDF
—
25
ns
Output Enable to Output High-Z
tGHQZ
tDF
—
25
ns
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
tAXQX
tOH
0
—
ns
—
tREADY
—
20
µs
RESET Pin Low to Read Mode
Test Conditions:
Output Load : 1 TTL gate and 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or VCCf
Timing measurement reference level
Input : VCCf/2
Output : VCCf/2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
21
ISSI
IS75V16F128GS32
®
FLASH READ CYCLE - FLASH 1 or FLASH 2
tRC
Address
Address Stable
tACC
CEf1
tDF
tOE
OE
tOEH
WE
DQ
22
tCE
tOH
High-Z
High-Z
Output valid
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
FLASH HARDWARE RESET / READ OPERATION TIMING DIAGRAM - FLASH 1 or FLASH 2
tRC
Address
Address Stable
tACC
CEf1
tRH
tRP
tRH
tCE
RESET
tOH
DQ
High-Z
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
Output valid
23
ISSI
IS75V16F128GS32
®
FLASH WRITE/ERASE/PROGRAM OPERATIONS - FLASH 1 or FLASH 2
JEDEC
Symbol
Standard
Symbol
Min
Typ
Max
Unit
Write Cycle Time
tAVAV
tWC
70
tAVWL
tAS
0
—
tASO
12
—
—
—
ns
Address Setup Time
—
—
—
tWLAX
tAH
45
tAHT
0
—
—
ns
—
—
—
Data Setup Time
tDVWH
tDS
30
tWHDX
tDH
0
—
—
tOEH
0
tOEH
10
—
—
—
—
ns
Data Hold Time
—
—
—
—
—
—
tCEPH
20
20
Read Recover Time Before Write (OE to CEf)
tGHWL
tGHWL
0
Read Recover Time Before Write (OE to WE)
tGHEL
tGHEL
0
WE Setup Time (CEf to WE)
tWLEL
tWS
0
CEf Setup Time (WE to CEf)
tELWL
tCS
0
WE Hold Time (CEf to WE)
tEHWH
tWH
0
CEf Hold Time (WE to CEf)
tWHEH
tCH
0
Write Pulse Width
tWHWL
tWP
35
CEf Pulse Width
tELEH
tCP
35
Write Pulse Width High
tWHWL
tWP
25
CEf Pulse Width High
tEHEL
tCPH
25
—
—
—
—
—
—
—
—
—
—
—
—
ns
tOEPH
—
—
—
—
—
—
—
—
—
—
—
—
tWHWH1
tWHWH1
6
100
µs
tWHWH2
tWHWH2
—
—
0.5
2.0
s
—
—
—
—
—
tVCS
50
500
tVACCR
500
tVLHT
4
tWPP
100
—
—
—
—
—
µs
tVIDR
—
—
—
—
—
Parameter
Address Setup Time to OE Low
During Toggle Bit Polling
Address Hold Time
Address Hold Time from CEf or
OE High During Toggle Bit Polling
Output Enable Hold Time Read
Output Enable Hold Time
Toggle and Data Polling
CEf High During Toggle Bit Polling
OE High During Toggle Bit Polling
Word Programming Operation (1)
Sector Erase Operation
(1)
VCC Setup Time
Rise Time to VID (2)
Rise Time to VACC
(3)
Voltage Transition Time (2)
Write Pulse Width (2)
24
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
FLASH WRITE/ERASE/PROGRAM OPERATIONS - FLASH 1 or FLASH 2 (Continued)
Parameter
OE Setup Time to WE Active
(2)
CEf Setup Time to WE Active (2)
Recover Time from RY/BY
RESET Pulse Width
RESET High Level Period Before Read
Program/Erase Valid to RY/BY Delay
Delay Time from Embedded Output Enable
Erase Time-Out Time
Erase Suspend Transition Time
JEDEC
Symbol
Standard
Symbol
Min
Typ
Max
Unit
—
—
—
—
—
—
—
—
—
tOESP
4
4
tRB
0
tRP
500
tRH
200
—
—
—
—
—
µs
tCSP
tBUSY
90
ns
tEOE
—
—
70
ns
tTOW
50
—
µs
tSPD
—
—
—
—
—
—
—
—
—
—
20
µs
µs
ns
ns
ns
Notes:
1. Does not include preprogramming time.
2. For Sector Group Protection operation.
3. For Accelerated Program operation.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
25
ISSI
IS75V16F128GS32
®
FLASH WRITE CYCLE - FLASH 1 or FLASH 2
(WE CONTROL)
Data Polling
3rd Bus Cycle
555h
ADDRESS
CEf
tCS
OE
tGHWL
PA
PA
tWC
tAS
tRC
tAH
tCH
tWP
tWPH
tDS
tDH
tCE
tOE
tWHWH1
WE
DQ
A0h
tOH
tDF
PD
DQ7
Dout
Dout
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
26
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
FLASH WRITE CYCLE - FLASH 1 or FLASH 2
(CEf CONTROL)
Data Polling
3rd Bus Cycle
555h
ADDRESS
PA
tWC
tAS
PA
tAH
CEf1
tWS
tWH
OE
tGHEL
tCP
tCPH
tDS
tDH
tWHWH1
WE
DQ
A0h
PD
DQ7
Dout
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
27
ISSI
IS75V16F128GS32
®
FLASH AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS - FLASH 1 or FLASH 2
555h
tWC
ADDRESS
2AAh
tAS
555h
555h
*
2AAh
SA
tAH
CEf1
tCH
tCS
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
AAh
DQ
30h for Sector Erase
55h
80h
AAh
55h
10h/
30h
tVCS
Vccf
Notes:
1. SA is the sector address for Sector Erase. Address = 555h for Chip Erase.
28
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
FLASH AC WAVEFORMS FOR DATA POLLING
DURING EMBEDDED ALGORITHM OPERATIONS - FLASH 1 or FLASH 2
CEf1
tCH
tOE
tDF
OE
tOEH
WE
tCEf1
(1)
DQ
DQ7
Data In
DQ7 =
Valid Data
High - Z
tWHWH1 or 2
DQ0/DQ6
Data In
DQ0 to DQ6 = Output Flag
tBUSY
DQ0 to DQ6
Valid Data
High - Z
tEOE
RY/BY
Notes:
1. DQ7 = Valid Data (the device has completed the Embedded operation.)
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
29
ISSI
IS75V16F128GS32
®
FLASH AC WAVEFORMS
FOR TOGGLE BIT DURING EMBEDDED ALGORITHM OPERATIONS - FLASH 1 or FLASH 2
ADDRESS
tAHT
tASO
CEf1
tAHT tAS
tCEPH
WE
tOEH
tOEH
tOEPH
OE
tDH
tOE
tCEf
(1)
DQ6/DQ2
Data
Toggle
Data
Toggle
Data
Toggle
Data
Stop
Toggle
Output
Valid
tBUSY
RY/BY
Notes:
1. DQ6 stops toggling (the device has completed the Embedded operation).
30
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
FLASH BACK-to-BACK READ/WRITE TIMING DIAGRAM - FLASH 1 or FLASH 2
Read
ADDRESS
Command
tRC
tWC
Read
tRC
BA1
BA2
(555h)
BA1
tAS
Command
BA2
(PA)
tWC
Read
tRC
Read
tRC
BA1
BA2
(PA)
tACC
tAH
tAS
tCE
tAHT
CEf1
tCEPH
tOE
OE
tGHWL
tWP
tDF
tOEH
WE
tDS
DQ
Valid
Output
Valid
Input
tDH
tDF
Valid
Output
(A0h)
Valid
Input
Valid
Output
Status
(PD)
Note:
1. This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Virtual Bank 1.
BA2: Address of Virtual Bank 2.
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
31
ISSI
IS75V16F128GS32
®
BY TIMING DIAGRAM
FLASH RY/BY
DURING WRITE/ERASE OPERATIONS - FLASH 1 or FLASH 2
CEf
The rising edge of the last write pulse
WE
Entire programming
or erase operations
RY/BY
tBUSY
BY TIMING DIAGRAM - FLASH 1 or FLASH 2
FLASH RESET, RY/BY
WE
RESET
tRP
tRB
RY/BY
tREADY
32
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
FLASH TEMPORARY SECTOR GROUP UNPROTECTION - FLASH 1 or FLASH 2
tVIDR
VCCf
tVLHT
tVCS
VID
3V
RESET
CEf1
WE
tVLHT
Program or Erase Command Sequence
tVLHT
RY/BY
Unprotection Period
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PRELIMINARY INFORMATION Rev. 00D
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33
ISSI
IS75V16F128GS32
®
FLASH ACCELERATED PROGRAM - FLASH 1 or FLASH 2
VCCf
tVCS
tVACCR
tVLHT
VACC
VIH
WP/ACC
CEf1
WE
tVLHT
RY/BY
Program Command Sequence
tVLHT
Acceleration Period
34
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
FLASH EXTENDED SECTOR GROUP PROTECTION- FLASH 1 or FLASH 2
tVCS
Vccf
tVLHT
RESET
tWC
tWC
tVIDR
Address
SPAX
SPAX
SPAY
A6, A3
A2, A0
A1
CEf1
OE
tWP
TIME-OUT
WE
Data
60h
60h
01h
40h
60h
tOE
Notes:
1. SPAX : Sector Group Address to be protected, SPAY : Next Group Sector Address to be protected,
TIME-OUT: Time-Out window = 250 µs (Min)
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
35
ISSI
IS75V16F128GS32
®
FLASH ERASE AND PROGRAMMING PERFORMANCE - FLASH 1 or FLASH 2
Min.
Typ.(1)
Max.
Unit
Sector Erase Time
—
0.5
2.0
s
Excludes programming time
prior to erasure
Word Programming Time
—
6.0
100
µs
Excludes system-level
overhead
Chip Programming Time
—
—
200
s
Excludes system-level
overhead
100,000
—
—
cycle
Parameter
Erase/Program Cycle
Remarks
Note:
1. Typical Erase conditions TA = 25°C, VCCf_1 & VCCf_2 = 2.9V. Typical
Program conditions TA = 25°C, VCCf_1 & VCCf_2 = 2.9V. Data= Checker
36
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
PSRAM POWER DOWN PROGRAM KEY TABLE
Basic KEY Table
Definition
KEY
A16
A17
A18
Mode Select
A19
A20
Area Select
A18
A19
A20
AREA
L
L
L
BOTTOM
L
H
X
RESERVED
H
L
X
RESERVED
H
H
H
TOP
(3)
(2)
A16
A17
L
L
L
H
RESERVED
H
H
8M Partial
H
H
SLEEP
MODE
NAP (4)
(4,5)
Available KEY Table
A16
A17
A18
A19
A20
MODE
Mode Select
NAP
Area Select
Data Retention
Area
L
L
X
X
X
None
H
L
L
L
L
Bottom 8M Only
H
L
H
H
H
Top 8M only
H
H
X
X
X
None
8M Partial
SLEEP
Notes:
1: The Power Down Program can be performed one time after compliance of Power-up timings and it should not be
re-programmed after regular Read or Write. Unspecified addresses, A0 to A15, can be either High or Low during
the programming. The RESERVED key should not be used.
2: TOP area is from the lowest address location. (i.e., A[20:0] = H))
3: BOTTOM area is from the highest address location. (i.e., A[20:0] = L)
4: NAP and SLEEP do not retain the data and Area Select is ignored.
5: Default state. Power Down Program to this SLEEP mode can be omitted.
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
37
ISSI
IS75V16F128GS32
®
PSRAM READ OPERATIONS
Parameter
Symbol
Min
Max.
tRC
70
—
ns
Chip Enable Access Time
tCE
65
ns
Output Enable Access Time(1)
tOE
40
ns
tAA
—
—
—
65
ns
tOH
5
ns
CE1r Low to Output Low-Z
tCLZ
5
OE Low to Output Low-Z
tOLZ
0
—
—
—
tCHZ
20
ns
tOHZ
—
—
20
ns
Address Setup Time to CE1r Low
tASC
-5
ns
Address Setup Time to OE(3,6)
tASO
25
tASO(ABS)
10
LB/UB Set up Time to CE1r Low
tBSC
-5
LB/UB Set up Time to OE Low
tBSO
-10
—
—
—
—
—
Read Cycle Time
(1,3)
Address Access Time
(1,4)
Output Data Hold Time(1)
(2)
(2)
CE1r High to Output High-Z(2)
OE High to Output High-Z
(2)
(5)
Address Setup Time to OE
(7)
(5)
(4)
Unit
ns
ns
ns
ns
ns
ns
tAX
—
5
ns
(4)
tCLAH
70
ns
Address Hold Time from OE Low(4,8)
tOLAH
45
Address Hold Time from CE1r High
tCHAH
-5
Address Hold Time from OE High
tOHAH
-5
LB/UB Hold Time to CE1r Low
tCHBH
-5
tOHBH
-5
—
—
—
—
—
—
tCLOL
25
1000
ns
tOLCH
45
ns
CE1r High Pulse Width
tCP
12
—
—
OE High Pulse Width(6,8,9)
tOP
25
1000
ns
tOP(ABS)
12
—
ns
Address Invalid Time
Address Hold Time from CE1r Low
LB/UB Hold Time to OE Low
CE1r Low to OE Low Delay Time
(3,6,8,9)
OE Low to CE1r High Delay Time(8)
OE High Pulse Width
(7)
ns
ns
ns
ns
ns
ns
Notes:
1. The output load is 30 pF.
2. The output load is 5 pF.
3. The tCE is applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of both
or either tASO or tCLOL is shorter than specified value.
4. Applicable only to A0 and A1 when both CE1r and OE are kept at Low for the address access.
5. Applicable if OE is brought to Low before CE1r goes Low.
6. The tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE.
If the actual value of each parameter is shorter than the specified minimum value, tOE becomes longer by the amount
of subtracting actual value from specified minimum value.
For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control
access (i.e., CE1r stays Low) , the tOE becomes tOE (Max) + tASO (Min) - tASO (actual) .
7. The tASO[ABS] and tOP[ABS] are the absolute minimum values during OE control access.
8. If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min)
- tCLOL (actual) or tRC (Min) - tOP (actual) .
9. Maximum value is applicable if CE1r is kept at Low.
38
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
PSRAM WRITE OPERATIONS
Parameter
Symbol
Write Cycle Time(1)
Value
Min.
Max.
Unit
tWC
70
—
ns
tAS
0
—
ns
tAH
35
—
ns
CE1r Write Setup Time
tCS
0
1000
ns
CE1r Write Hold Time
tCH
0
1000
ns
WE Setup Time
tWS
0
—
ns
WE Hold Time
tWH
0
—
ns
LB adnd UB Setup Time
tBS
-5
—
ns
LB adnd UB Hold Time
tBH
-5
—
ns
OE Setup Time(3)
tOES
0
1000
ns
OE Hold Time
tOEH
25
1000
ns
OE Hold Time
tOEH(ABS)
12
—
ns
OE High to CE1r Low Setup Time(6)
tOHCL
-5
—
ns
OE High to Address Hold Time
tOHAH
-5
—
ns
CE1r Write Pulse Width
tCW
45
—
ns
WE Write Pulse Width
tWP
45
—
ns
CE1r Write Recovery Time(1,9)
tWRC
10
—
ns
WE Write Recovery Time(1,3,9)
tWR
10
1000
ns
Data Setup Time
tDS
15
—
ns
Data Hold Time
tDH
0
—
ns
CE1r High Pulse Width(9)
tCP
12
—
ns
Address Setup Time
Address Hold Time
(2)
(2)
(3,4)
(5)
(7)
(1,8)
(1,8)
Notes:
1. Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR).
2. New write address is valid from either CE1r or WE that is brought to High.
3. Maximum value is applicable if CE1r is kept at Low and both WE and OE are kept at High.
4. The tOEH is specified from end of tWC (Min), and is a reference value when access time is determined by tOE.
If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual
value from specified minimum value.
5. The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1r stay Low.
6. tOHCL (Min) must be satisfied if read operation is not performed prior to write operation.
In case OE is disabled after tOHCL (Min), WE Low must be asserted after tRC (Min) from CE1r Low.
In other words, read operation is initiated if tOHCL (Min) is not satisfied.
7. Applicable if CE1r stays Low after read operation.
8. tCW and tWP are applicable if write operation is initiated by CE1r and WE, respectively.
9. tWRC and tWR are applicable if write operation is terminated by CE1r and WE, respectively.
The tWR (Min) can be ignored if CE1r is brought to High together or after WE is brought to High.
In such a case, the tCP (Min) must be satisfied.
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
39
ISSI
IS75V16F128GS32
®
PSRAM POWER DOWN PARAMETERS
Parameter
Symbol
Value
Min.
Max.
CE2r Low Setup Time for Power down Entry
tCSP
10
CE2r Low Hold Time after Power down Entry
tC2LP
70
CE1r High Hold Time Following CE2r High after Power down Exit
SLEEP Mode only
tCHH
350
CE1r High Setup Time following CE2r High after Power down Exit
(Except for SLEEP Mode)
tCHHN
1
CE1r High Setup Time following CE2r High after Power down Exit
tCHS
10
tEPS
70
tEP
70
tEPH
70
tEAS
15
tEAH
0
CE1r High to PE Low Setup Time
(1)
PE Power Down Program Pulse Width
(1)
PE High to CE1r Low Hold Time (1)
Address Setup Time to PE High
(1)
Address Setup Time from PE High
(1)
Unit
—
—
ns
—
—
µs
—
—
—
—
—
—
ns
ns
µs
ns
ns
ns
ns
ns
Note:
1. Applies to Power Down Program.
PSRAM OTHER TIMING PARAMETERS
Parameter
Symbol
CE1r High to OE Invalid for Standby Entry
CE1r High to WE Invalid for Standby Entry
(1)
(2)
CE2r Low Hold Time after Power-up
CE2r High Hold Time after Power-up(3)
CE1r High Hold Time Following CE2r High after Power-up
Input Transition Time(4)
(2)
Value
Min.
Max.
Unit
µs
350
—
—
—
—
—
1
25
ns
tCHOX
10
tCHWX
10
tC2LH
50
tC2HL
50
tCHH
tT
ns
ns
µs
µs
Notes:
1. Unintended data may be written into any address location if tCHWX is not satisfied.
2. Must satisfy tCHH (Min) after tC2LH (Min) .
3. Requires Power Down mode entry and exit after tC2HL.
4. Input Transition Time (tT) at AC testing is 5 ns as shown below. If actual tT is longer than 5 ns,
it may violate some timing parameters.
PSRAM AC TEST CONDITIONS
Parameter
Input High Level
Input Low Level
Input Timing Measurement Level
Input Transition Time
40
Symbol
Condition
Value
Unit
VIH
VCCr = 2.7V to 3.3V
2.3
V
VIL
VREF
tT
VCCr = 2.7V to 3.3V
VCCr = 2.7V to 3.3V
Between VIL and VIH
0.4
1.3
5
V
V
ns
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PRELIMINARY INFORMATION Rev. 00D
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ISSI
IS75V16F128GS32
®
PSRAM READ TIMING (OE Control Access)
tRC
ADDRESS
tRC
ADDRESS VALID
ADDRESS VALID
tASO
tCE
tOHAH
tOHAH
CE1r
tOE
tCLOL
tOLCH
tOE
OE
tASO
tOP
tOHBH
tBSO
tBSO
tOHBH
LB / UB
tOHZ
tOHZ
tOH
tOLZ
tOH
tOLZ
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
PSRAM READ TIMING (CE1r Control Access)
tRC
ADDRESS
tRC
ADDRESS VALID
tASC
tCE
ADDRESS VALID
tASC
tCHAH
tCHAH
tCE
CE1r
tCP
OE
tBSC
tCHBH
tBSC
tCHBH
LB / UB
tCHZ
tCLZ
tOH
tCHZ
tCLZ
tOH
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
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PRELIMINARY INFORMATION Rev. 00D
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41
ISSI
IS75V16F128GS32
®
PSRAM READ TIMING (Address Access after OE Control Access)
tRC
tRC
ADDRESS
(A20-A3)
ADDRESS VALID
ADDRESS VALID
(No Change)
ADDRESS
(A2-A0)
ADDRESS VALID
ADDRESS VALID
tOLAH
tASO
tOHAH
tAA
tAX
CE1r
tOE
tOHZ
OE
tBSO
tOHBH
LB / UB
tOH
tOH
tOLZ
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
PSRAM READ TIMING (Address Access after CE1r Control Access)
tRC
tRC
ADDRESS
(A20-A3)
ADDRESS VALID
ADDRESS VALID
(No Change)
ADDRESS
(A2-A0)
ADDRESS VALID
ADDRESS VALID
tCLAH
tASC
tCHAH
tAA
tAX
CE1r
tCHZ
tCE
OE
tCHBH
tBSC
UB, LB
tCLZ
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
42
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
PSRAM WRITE TIMING (CE1r Control)
tWC
Address
Address Valid
tAH
tAS
tAS
CE1r
tWRC
tCW
tWS
tWH
tWS
tBH
tBS
WE
tBS
UB, LB
tOHCL
OE
tDH
tDS
DQ
(Input)
Valid Data Input
Note: CE2r and PE must be High during write cycle.
PSRAM WRITE TIMING (WE Control, Single Write Operation)
tWC
Address
Address Valid
tOHAH
tAS
tAH
tAS
tCH
CE1r
tCP
WE
tOHCL
tCS
tOHBH
tBS
tWP
tWR
tBH
UB, LB
tOES
OE
tOHz
tDS
tDH
DQ
(Input)
Valid Data Input
Note: CE2r and PE must be High during write cycle.
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PRELIMINARY INFORMATION Rev. 00D
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43
ISSI
IS75V16F128GS32
®
PSRAM WRITE TIMING (WE Control, Continuous Write Operation)
tWC
ADDRESS
Address Valid
tOHAH
tAH
tAS
CE1r
tOHCL
tAS
tWR
tWP
tCS
WE
tBH
tBS
tBH
tBS
UB, LB
tOES
OE
tDS
tOHz
tDH
DQ
(Input)
Valid Data Input
Note: CE2r and PE must be High during write cycle.
PSRAM READ / WRITE TIMING (CE1r Control)
tWC
ADDRESS
Write Address
tAS
tCHAH
Read Address
tASC
tAH
CE1r
tWRC
tCP
WE
tWH
tWS
tCHBH
tBS
tWH
tCW
tBH
tWS
tCLOL
tBSO
UB, LB
tOHCL
OE
tCHZ
tOH
tOLz
tDS
tDH
DQ
Read Data Output
Valid Data Input
Note: Write address is valid from either CE1r or WE of last falling edge.
44
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
PSRAM READ / WRITE TIMING (CE1r Control)
tRC
ADDRESS
Read Address
Write Address
tASC
tWRC
tAS
tCHAH
CE1r
tWRC (Min)
tCP
tWS
tWH
tCE
tWH
tWS
WE
tBSC
tBH
tCHBH
tBS
UB, LB
tOEH
tOHCL
OE
tCHZ
tCLZ
tDH
tOH
DQ
Read Data Output
Write Data Input
Note: The tOEH is specified from the time satisfied oth tWRC and tWR(min).
PSRAM READ / WRITE TIMING (READ = OE Control, WRITE = WE Control)
tWC
ADDRESS
Write Address
tAS
tOHAH
CE1r
Read Address
tASO
tAH
Low
tWR
tWP
tOEH
WE
tOHBH
tBS
tBH
tBSO
UB, LB
tOES
OE
tOHZ
tOH
tDS
tDH
tOLZ
DQ
Read Data Output
Write Data Input
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is
exclusively controlled by OE.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
45
ISSI
IS75V16F128GS32
®
PSRAM READ / WRITE TIMING (READ = OE Control, WRITE = WE Control)
tRC
Address
tASO
CE1r
Write Address
Read Address
tAS
tOHAH
Low
tWR
tOEH
WE
tBH
tOHBH
tBSO
tBS
UB, LB
tOES
tOE
OE
tOHZ
tDH
tOLZ
tOH
DQ
Write Data Input
Read Data Output
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is
exclusively controlled OE.
46
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
PSRAM POWER DOWN TIMING
CE1r
tEPS
tEPH
tEP
PE
tEAS
tEAH
KEY
ADDRESS
A20-A16
Note: CE2r must be High for Power Down Programming. Any other inputs not specified above can be either
High or Low.
PSRAM STANDBY ENTRY and EXIT TIMING
CE1r
tCHS
CE2r
tCSP
tC2LP
tCHH (CHHN)
High - Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Note: This Power Down mode can be also used for Power-up Timing #2 except that tCHHN can not be used at
Power-up Timing.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
47
ISSI
IS75V16F128GS32
®
PSRAM POWER UP TIMING 1
CE1r
tCHS
tCHH
tC2LH
CE2r
Vccr Min
Vccr
0V
Note: The tC2LH specifies after Vccr reaches specfied minimum level.
PSRAM POWER UP TIMING 2
CE1r
tCHS
tCSP
tC2HL
tC2LP
tCHH
CE2r
tC2HL
Vccr Min
Vccr
0V
Note: The tC2HL specifies from CE2r Low to High transition after Vccr reaches specified minimum level. CE1r must
be brought to High prior to or together with CE2r Low to High transition.
48
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
PSRAM DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
VDR
Vccr Data Retention Supply Voltage
CE1r = CE2r ≥ VCCr -0.2V OR,
CE1r = CE2r = VIH
2.1
3.3
V
IDR
Vccr Data Retention Supply Current
2.1 V ≤ VCCr ≤ 2.7 V,≥
VIN = VIH (1) or VIL
CE1r = CE2r = VIH (1),
IOUT = 0 MA
—
1.5
mA
IDR1
Vccr Data Retention Supply Current
2.1 V ≤VCCr ≤ 2.7 V,≥
VIN ≤ 0.2 V or VIN ≥ VCCr -0.2 V,
CE1r = CE2r ≥ VCCr -0.2 V
IOUT = 0 mA
—
100
µA
tDRS
Data Retention SetupTime
2.7 V ≤ VCCr ≤ 3.3 V,≥
At Data Retention Entry
0
—
ns
tDRR
Data Retention RecoveryTime
2.7 V ≤ VCCr ≤ 3.3 V,≥
After Data Retention
200
—
ns
∆V/∆t
VCCR Voltage Transition Time
—
0.2
—
V/µs
Note:
1. 2.0 V ≤ VIN ≤ VCCr + 0.3
PSRAM DATA RETENTION TIMING
tDRS
3.3V
2.7V
tDRR
∆V/∆t
Vccr
∆V/∆t
2.1V
CE2r
CE1r
CE1r = CE2r >Vccr - 0.2V or
VIH(1) Min
0.4V
GND
Data Retention Mode
Data bus must be in High-Z at data retention entry
Note:
1. 2.0 V ≤ VIH ≤ VCCr + 0.3 V
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
49
ISSI
IS75V16F128GS32
®
PIN CAPACITANCE
Symbol
Parameter
Conditions
CIN
Input Capacitance
VIN
COUT
Output Capacitance
CIN2
Control Pin Capacitance
=0V
VOUT = 0 V
VIN = 0 V
Min.
Max.
Unit
-
20
pF
-
25
pF
-
25
pF
Notes:
1. Test conditions TA = +25 °C, f = 1.0 MHz
HANDLING OF PACKAGE:
Please handle this package carefully because the sides of the package have acute angles.
CAUTION:
1) The high voltage (VID) cannot be applied to address pins and control pins except RESET. Exception is when
autoselect and sector group protection function are used. Then the high voltage (VID) can be applied to RESET.
2) Without the high voltage (VID) sector group protection can be achieved by using the “Extended Sector Group
Protection” command.
50
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
ISSI
IS75V16F128GS32
®
MINI BALL GRID ARRAY – 107-Ball BGA
PACKAGE CODE: B (9.00 mm x 10.00 mm Body, 0.8 mm Ball Pitch)
ø 0.40 + 0.10/−0.05 (107X)
1 2 3 4 5 6 7 8 9 10
10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
G
H
J
K
L
M
e
D1
D
E1
e
E
A1
A
SEATING PLANE
Symbol
Min.
Typ.
Max.
Units
A
1.15
1.25
1.40
mm
A1
0.05
0.10
0.15
mm
D
9.90
10.00
10.10
mm
D1
—
8.80
—
mm
E
8.90
9.00
9.10
mm
E1
—
7.20
—
mm
e
—
0.80
—
mm
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
51
ISSI
IS75V16F128GS32
®
ORDERING INFORMATION
Industrial Range: -30oC to +85oC
Flash Bank
Order Part No.
Organization
IS75V16F128GS32-7065BI User Configurable
52
Flash
Speed(ns)
70
PSRAM
Speed(ns)
65
Package
107-ball BGA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03