TI SN74AVC1T45YZPR

SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
FEATURES
1
• Available in the Texas Instruments NanoFree™
Package
• Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
• VCC Isolation Feature - If Either VCC Input Is at
GND, Both Ports Are in the High-Impedance
State
• DIR Input Circuit Referenced to VCCA
• ±12-mA Output Drive at 3.3 V
• I/Os Are 4.6-V Tolerant
• Ioff Supports Partial-Power-Down Mode
Operation
•
2
DBV PACKAGE
(TOP VIEW)
VCCA
1
6
•
•
Typical Max Data Rates
– 500 Mbps (1.8-V to 3.3-V Translation)
– 320 Mbps (<1.8-V to 3.3-V Translation)
– 320 Mbps (Translate to 2.5 V or 1.8 V)
– 280 Mbps (Translate to 1.5 V)
– 240 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCK PACKAGE
(TOP VIEW)
VCCB
VCCA
1
2
GND
GND
2
5
DIR
A
3
4
B
3
A
6
5
4
DRL PACKAGE
(TOP VIEW)
VCCB
DIR
VCCA
1
6
VCCB
GND
2
5
DIR
A
3
4
B
B
YZP PACKAGE
(BOTTOM VIEW)
A
GND
VCCA
C1
B1
A1
3 4 C2 B
2 5 B2 DIR
1 6 A2 VCCB
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The
SN74AVC1T45 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as
low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The
B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
ORDERING INFORMATION
TA
–40°C to 85°C
(1)
(2)
(3)
PACKAGE
(1) (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING (3)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74AVC1T45YZPR
_ _ _TC_
SOT (SOT-23) – DBV
Reel of 3000
SN74AVC1T45DBVR
DT1_
SOT (SC-70) – DCK
Reel of 3000
SN74AVC1T45DCKR
TC_
SOT (SOT-553) – DRL
Reel of 4000
SN74AVC1T45DRLR
TC_
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2008, Texas Instruments Incorporated
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data
from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the
A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic
HIGH or LOW level applied to prevent excess ICC and ICCZ.
The SN74AVC1T45 is designed so that the DIR input is powered by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance
state.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
FUNCTION TABLE (1)
(1)
INPUT
DIR
OPERATION
L
B data to A bus
H
A data to B bus
Input circuits of the data I/Os
always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
DIR
A
5
3
4
VCCA
2
B
VCCB
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Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AVC1T45
www.ti.com
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCCA
VCCB
Supply voltage range
VI
Input voltage range (2)
MIN
MAX
–0.5
4.6
I/O ports (A port)
–0.5
4.6
I/O ports (B port)
–0.5
4.6
Control inputs
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
UNIT
V
V
VO
Voltage range applied to any output in the high-impedance or
power-off state (2)
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCCA, VCCB, or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
DBV package
165
DCK package
259
DRL package
142
YZP package
(1)
(2)
(3)
(4)
V
V
°C/W
123
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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Copyright © 2003–2008, Texas Instruments Incorporated
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SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
Recommended Operating Conditions (1) (2) (3)
VCCI
VCCO
MIN
MAX
UNIT
VCCA
Supply voltage
1.2
3.6
V
VCCB
Supply voltage
1.2
3.6
V
High-level
input voltage
VIH
Low-level
input voltage
VIL
High-level
input voltage
VIH
VIL
Low-level
input voltage
VI
Input voltage
Data inputs
Data inputs
DIR
(referenced to VCCA)
DIR
(referenced to VCCA)
1.2 V to 1.95 V
VCCI × 0.65
1.95 V to 2.7 V
1.6
2.7 V to 3.6 V
2
1.2 V to 1.95 V
VCCI × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
0.8
1.2 V to 1.95 V
VCCA × 0.65
1.95 V to 2.7 V
1.6
2.7 V to 3.6 V
2
Output voltage
IOH
VCCA × 0.35
1.95 V to 2.7 V
0.7
IOL
3.6
Active state
0
VCCO
3-state
0
3.6
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
(2)
(3)
4
V
0.8
0
High-level output current
V
V
1.2 V to 1.95 V
2.7 V to 3.6 V
VO
V
1.2 V
–3
1.4 V to 1.6 V
–6
1.65 V to 1.95 V
–8
2.3 V to 2.7 V
–9
3 V to 3.6 V
–12
1.2 V
3
1.4 V to 1.6 V
6
1.65 V to 1.95 V
8
2.3 V to 2.7 V
9
3 V to 3.6 V
12
–40
V
V
mA
mA
5
ns/V
85
°C
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
Electrical Characteristics (1) (2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOL
II
1.2 V to 3.6 V
1.2 V to 3.6 V
IOH = –3 mA
1.2 V
1.2 V
IOH = –6 mA
1.4 V
1.4 V
1.05
IOH = –8 mA
1.65 V
1.65 V
1.2
IOH = –9 mA
2.3 V
2.3 V
1.75
IOH = –12 mA
3V
3V
2.3
IOL = 100 µA
1.2 V to 3.6 V
1.2 V to 3.6 V
IOL = 3 mA
1.2 V
1.2 V
IOL = 6 mA
1.4 V
1.4 V
0.35
1.65 V
1.65 V
0.45
IOL = 9 mA
2.3 V
2.3 V
0.55
IOL = 12 mA
3V
3V
1.2 V to 3.6 V
1.2 V to 3.6 V
Ioff
IOZ
IOL = 8 mA
DIR
A port
B port
B port
A port
ICCA
VI = VIH
VI = VIL
VI = VCCA or GND
VI or VO = 0 to 3.6 V
VO = VCCO or GND,
VI = VCCI or GND
VI = VCCI or GND, IO = 0
ICCB
VI = VCCI or GND, IO = 0
ICCA + ICCB
(see Table 1)
–40°C to 85°C
VCCB
IOH = –100 µA
VOH
TA = 25°C
VCCA
VI = VCCI or GND, IO = 0
MIN
TYP
MAX
MIN
MAX
UNIT
VCCO
– 0.2
0.95
V
0.2
0.15
V
0.7
±0.025
±0.25
±1
0V
0 to 3.6 V
±0.1
±1
±5
0 to 3.6 V
0V
±0.1
±1
±5
0V
3.6 V
±0.5
±2.5
±5
3.6 V
0V
±0.5
±2.5
±5
1.2 V to 3.6 V
1.2 V to 3.6 V
10
0V
3.6 V
–2
3.6 V
0V
10
1.2 V to 3.6 V
1.2 V to 3.6 V
10
0V
3.6 V
10
3.6 V
0V
–2
1.2 V to 3.6 V
1.2 V to 3.6 V
20
µA
µA
µA
µA
µA
µA
Ci
Control
inputs
VI = 3.3 V or GND
3.3 V
3.3 V
2.5
pF
Cio
A or B
port
VO = 3.3 V or GND
3.3 V
3.3 V
6
pF
(1)
(2)
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
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SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL
(1)
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
3.3
2.7
2.4
2.3
2.4
3.3
2.7
2.4
2.3
2.4
3.3
3.1
2.9
2.8
2.7
3.3
3.1
2.9
2.8
2.7
5.1
5.2
5.3
5.2
3.7
5.1
5.2
5.3
5.2
3.7
5.3
4.3
4
3.3
3.7
5.3
4.3
4
3.3
3.7
8.6
7.3
6.8
6.1
6.4
8.6
7.3
6.8
6.1
6.4
8.3
7.8
7.7
7.5
5.8
8.3
7.8
7.7
7.5
5.8
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL
(1)
6
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.9
0.7
5.6
0.6
5.2
0.5
4.2
0.5
3.8
2.9
0.7
5.6
0.6
5.2
0.5
4.2
0.5
3.8
2.6
0.6
5.5
0.4
5.3
0.3
4.9
0.3
4.8
2.6
0.6
5.5
0.4
5.3
0.3
4.9
0.3
4.8
3.8
1.6
6.7
1.5
6.8
0.3
6.9
0.9
6.9
3.8
1.6
6.7
1.5
6.8
0.3
6.9
0.9
6.9
5.1
1.8
8.1
1.6
7.1
1.1
4.7
1.4
4.5
5.1
1.8
8.1
1.6
7.1
1.1
4.7
1.4
4.5
7.7
13.6
12.4
9.6
9.3
7.7
13.6
12.4
9.6
9.3
6.7
12.3
12
11.1
10.7
6.7
12.3
12
11.1
10.7
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
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Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AVC1T45
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL (1)
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.7
0.6
5.3
0.5
5
0.4
3.9
0.4
3.4
2.7
0.6
5.3
0.5
5
0.4
3.9
0.4
3.4
2.3
0.5
5.2
0.4
5
0.3
4.6
0.2
4.4
2.3
0.5
5.2
0.4
5
0.3
4.6
0.2
4.4
3.8
1.6
5.9
1.6
5.9
1.6
5.9
0.5
6
3.8
1.6
5.9
1.6
5.9
1.6
5.9
0.5
6
5
1.8
7.7
1.4
6.8
1
4.4
1.4
5.3
5
1.8
7.7
1.4
6.8
1
4.4
1.4
5.3
7.3
12.9
11.8
9
8.7
7.3
12.9
11.8
9
8.7
6.5
11.2
10.9
9.8
9.4
6.5
11.2
10.9
9.8
9.4
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL
(1)
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.6
0.5
4.9
0.4
4.6
0.3
3.4
0.3
3
2.6
0.5
4.9
0.4
4.6
0.3
3.4
0.3
3
2.2
0.4
4.2
0.3
3.8
0.2
3.4
0.2
3.3
2.2
0.4
4.2
0.3
3.8
0.2
3.4
0.2
3.3
2.8
0.3
3.8
0.8
3.8
0.4
3.8
0.5
3.8
2.8
0.3
3.8
0.8
3.8
0.4
3.8
0.5
3.8
4.9
2
7.6
1.5
6.5
0.6
4.1
1
4
4.9
2
7.6
1.5
6.5
0.6
4.1
1
4
7.1
11.8
10.3
7.5
7.3
7.1
11.8
10.3
7.5
7.3
5.4
8.6
8.1
7
6.6
5.4
8.6
8.1
7
6.6
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
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Product Folder Link(s): SN74AVC1T45
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SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH (1)
tPZL (1)
tPZH (1)
tPZL (1)
(1)
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.6
0.4
4.7
0.3
4.4
0.2
3.3
0.2
2.8
2.6
0.4
4.7
0.3
4.4
0.2
3.3
0.2
2.8
2.2
0.4
3.8
0.3
3.4
0.2
3
0.1
2.8
2.2
0.4
3.8
0.3
3.4
0.2
3
0.1
2.8
3.1
1.3
4.3
1.3
4.3
1.3
4.3
1.3
4.3
3.1
1.3
4.3
1.3
4.3
1.3
4.3
1.3
4.3
4
0.7
7.4
0.6
6.5
0.7
4
1.5
4.9
4
0.7
7.4
0.6
6.5
0.7
4
1.5
4.9
6.2
11.2
9.9
7
6.7
6.2
11.2
9.9
7
6.7
5.7
8.9
8.5
7.2
6.8
5.7
8.9
8.5
7.2
6.8
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
Operating Characteristics
TA = 25°C
PARAMETER
CpdA (1)
CpdB (1)
(1)
8
A-port input,
B-port output
B-port input,
A-port output
A-port input,
B-port output
B-port input,
A-port output
TEST
CONDITIONS
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
VCCA =
VCCB = 1.2 V
VCCA =
VCCB = 1.5 V
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
3
3
3
3
4
13
13
14
15
15
13
13
14
15
15
3
3
3
3
3
UNIT
pF
pF
Power dissipation capacitance per transceiver
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SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
Power-Up Considerations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up VCCA.
3. VCCB can be ramped up along with or after VCCA.
Table 1. Typical Total Static Power Consumption (ICCA + ICCB)
VCCB
VCCA
0V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0V
0
<0.5
<0.5
<0.5
<0.5
<0.5
1.2 V
<0.5
<1
<1
<1
<1
1
1.5 V
<0.5
<1
<1
<1
<1
1
1.8 V
<0.5
<1
<1
<1
<1
<1
2.5 V
<0.5
1
<1
<1
<1
<1
3.3 V
<0.5
1
<1
<1
<1
<1
UNIT
µA
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SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
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SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
TYPICAL CHARACTERISTICS
6
6
5
5
4
4
tPHL - ns
tPLH - ns
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 1.2 V
3
2
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
0
0
10
20
30
40
50
VCCB = 3.3 V
0
60
0
10
20
CL - pF
30
CL - pF
40
50
60
6
6
5
5
4
4
tPHL - ns
tPLH - ns
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 1.5 V
3
2
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
0
0
10
20
30
40
50
60
0
0
10
CL - pF
10
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20
30
CL - pF
40
50
60
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SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
TYPICAL CHARACTERISTICS
6
6
5
5
4
4
tPHL - ns
tPLH - ns
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 1.8 V
3
2
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
0
0
10
20
30
40
50
VCCB = 3.3 V
0
60
0
10
20
CL - pF
30
CL - pF
40
50
60
50
60
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 2.5 V
6
6
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
5
VCCB = 1.8 V
5
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
4
tPHL - ns
tPLH - ns
4
3
3
2
2
1
1
0
0
10
20
30
40
50
60
0
0
10
CL - pF
20
30
CL - pF
40
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SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
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SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 3.3 V
6
6
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
5
VCCB = 1.8 V
5
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
4
tPHL - ns
tPLH - ns
4
3
3
2
2
1
1
0
0
10
20
30
40
50
60
0
0
10
CL - pF
12
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20
30
CL - pF
40
50
60
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SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
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SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.2 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
15 pF
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
tPLZ
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
tPZH
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
Figure 1. Load Circuit and Voltage Waveforms
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SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
APPLICATION INFORMATION
Figure 2 shows an example of the SN74AVC1T45 being used in a unidirectional logic level-shifting application.
VCC1
VCC1
VCC2
1
6
2
5
3
4
SYSTEM-1
VCC2
SYSTEM-2
PIN
NAME
FUNCTION
DESCRIPTION
1
VCCA
VCC1
SYSTEM-1 supply voltage (1.2 V to 3.6 V)
2
GND
GND
Device GND
3
A
OUT
Output level depends on VCC1 voltage.
4
B
IN
Input threshold value depends on VCC2 voltage.
5
DIR
DIR
GND (low level) determines B-port to A-port direction.
6
VCCB
VCC2
SYSTEM-2 supply voltage (1.2 V to 3.6 V)
Figure 2. Unidirectional Logic Level-Shifting Application
14
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WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
APPLICATION INFORMATION
Figure 3 shows the SN74AVC1T45 being used in a bidirectional logic level-shifting application. Since the
SN74AVC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
VCC1
VCC1
VCC2
Pullup/Pulldown
or Bus Hold†
I/O-1
VCC2
Pullup/Pulldown
or Bus Hold†
1
6
2
5
3
4
I/O-2
DIR CTRL
SYSTEM-1
SYSTEM-2
The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to
SYSTEM-1.
STATE
DIR CTRL
I/O-1
I/O-2
1
H
Out
In
2
H
Hi-Z
Hi-Z
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The
bus-line state depends on pullup or pulldown. (1)
3
L
Hi-Z
Hi-Z
DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or
pulldown. (1)
4
L
Out
In
(1)
DESCRIPTION
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 data to SYSTEM-1
SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 3. Bidirectional Logic Level-Shifting Application
Enable Times
Calculate the enable times for the SN74AVC1T45 using the following formulas:
• tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
• tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
• tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
• tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVC1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AVC1T45DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DBVRE4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DBVTE4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DCKR
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DCKRE4
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DCKRG4
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DCKTE4
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DRLR
ACTIVE
SOT
DRL
6
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45DRLRG4
ACTIVE
SOT
DRL
6
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVC1T45YZPR
ACTIVE
WCSP
YZP
6
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2007
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Nov-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AVC1T45DBVR
DBV
6
SITE 35
180
9
3.23
3.17
1.37
4
8
Q3
SN74AVC1T45DBVT
DBV
6
SITE 35
180
9
3.23
3.17
1.37
4
8
Q3
SN74AVC1T45DCKR
DCK
6
SITE 35
180
9
2.24
2.34
1.22
4
8
Q3
SN74AVC1T45DCKT
DCK
6
SITE 35
180
9
2.24
2.34
1.22
4
8
Q3
SN74AVC1T45DRLR
DRL
6
SITE 35
180
9
1.78
1.78
0.69
4
8
Q3
SN74AVC1T45YZPR
YZP
6
SITE 55
180
8
1.02
1.52
0.66
4
8
Q1
SN74AVC1T45YZPR
YZP
6
SITE 12
180
8
1.02
1.52
0.66
4
8
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Nov-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74AVC1T45DBVR
DBV
6
SITE 35
202.0
201.0
28.0
SN74AVC1T45DBVT
DBV
6
SITE 35
202.0
201.0
28.0
SN74AVC1T45DCKR
DCK
6
SITE 35
202.0
201.0
28.0
SN74AVC1T45DCKT
DCK
6
SITE 35
202.0
201.0
28.0
SN74AVC1T45DRLR
DRL
6
SITE 35
202.0
201.0
28.0
SN74AVC1T45YZPR
YZP
6
SITE 55
220.0
220.0
34.0
SN74AVC1T45YZPR
YZP
6
SITE 12
220.0
220.0
0.0
Pack Materials-Page 2
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