IX4R11 Preliminary Data Sheet 4A Half-Bridge Driver Features • Floating High Side Driver with boot-strap Power supply along with a Low Side Driver. • Fully operational to 650V • ± 50V/ns dV/dt immunity • Gate drive power supply range: 10 - 35V • Undervoltage lockout for both output drivers • Separate Logic power supply range: 3.3V to VCL • Built using the advantages and compatibility of CMOS and IXYS HDMOSTM processes • Latch-Up protected over entire operating range • High peak output current: 4A • Matched propagation delay for both outputs • Low output impedance • Low power supply current • Immune to negative voltage transients Warning: The IX4R11 is ESD sensitive. General Description The IX4R11 Bridge Driver for N-channel MOSFETs and IGBTs with a high side and low side output, whose input signals reference the low side. The High Side driver can control a MOSFET or IGBT connected to a positive buss voltage up to 650V. The logic input stages are compatible with TTL or CMOS, have built-in hysteresis and are fully immune to latch up over the entire operating range. The IX4R11 can withstand dV/dt on the output side up to ± 50V/ns. The IX4R11 comes in either the 16-PIN SOIC package (IX4R11S3) or the 14-PIN DIP through-hole package (IX4R11P7) Applications • • • • • • Driving MOSFETs and IGBTs in half-bridge circuits High voltage, high side and low side drivers Motor Controls Switch Mode Power Supplies (SMPS) DC to DC Converters Class D Switching Amplifiers IX4R11S3 Figure 1. Typical Circuit Connection Copyright © IXYS CORPORATION 2004 DS99164A(08/04) First Release IX4R11 Figure 2 - IX4R11 Functional Block Diagram VDD VCH Low to HIN HIN HIN VCH High OUT RST IN Gate Current Output HGO UVCC Detect DG HS HS Isolated High Side VCL VDD LIN VCL Low to High Side Delay Equalizer and Shutdown Gate Current Output Shutdown Logic ENB LGO UVCC Detect DG DG LS LS 1 Ohm Pin Description And Configuration SYMBOL VDD HIN LIN ENB DG VCH HGO HS VCL FUNCTION Logic Supply HS Input LS Input Enable Ground Supply Voltage Output Return Supply Voltage LGO LS DESCRIPTION Positive power supply for the chip CMOS functions High side Input signal, TTL or CMOS compatible; HGO in phase Low side Input signal, TTL or CMOS compatible; LGO in phase Chip enable. When driven high, both outputs go low. Logic Reference Ground High Side Power Supply High side driver output High side voltage return pin Low side power supply. This power supply provides power for both outputs. Voltage range is from 4.5 to 25V. Low side driver output Low side return Output Ground 16-PIN SOIC N/C HGO 7 9 VDD VCH 6 10 HIN HS 5 11 ENB N/C 4 12 LIN VCL 3 13 DG LS 2 14 NC LGO 1 IX4R11P7 8 IX4R11S3 14-PIN DIP 2 IX4R11 Absolute Maximum Ratings Symbol VCH Definition High side floating supply voltage Min -25 Max 650 Units V VHS High side floating supply offset voltage VCH-200 VCH+.3 V VHGO High side floating output voltage VHS-.3 VCH+.3 V VCL Low side fixed supply voltage -0.3 35 V VLGO Low side output voltage -0.3 VCL+.3 V VDD Logic supply voltage -0.3 VDG+35 V VDG Logic supply offset voltage VLS-3.8 VLS+3.8 V VIN Logic input voltage(HIN & LIN) VSS-.3 VDD+.3 V dVS/dt Allowable offset supply voltage transient 50 V/ns PD PD RTHJA RTHJc Package power dissipation@ TA ≤ 25C Package power dissipation@ TC ≤ 25C Thermal resistance, junction-to-ambient Thermal resistance, junction-to-case 1.25 2.5 100 50 W W K/W K/W TJ Junction Temperature 150 o C TS Storage temperature 150 o C TL Lead temperature (soldering, 10 s) 300 o C -55 Recommended Operating Conditions Symbol VCH Definition Min High side floating supply absolute voltage VHS+10 Max VHS+20 Units V VHS High side floating supply offset voltage -20 650 V VHGO VCL High side floating output voltage VHS VCH+20 V Low side fixed supply voltage 10 20 V VLGO Low side output voltage 0 VCC V VDD Logic supply voltage VDG+3 VDG+20 V VDG Logic supply voffset voltage VLS-1 VLS+1 V VIN Logic input voltage(HIN, LIN, ENbar) VDG VDD TA Ambient Temperature -40 125 Ordering Information Part Number Package Type IX4R11P7 IX4R11S3 14-PIN DIP 16-PIN SOIC 3 V o C IX4R11 Dynamic Electrical Characteristics Symbol ton Definition Turn-on propagation delay Test Conditions VHS= 0V, Cload= 2nF toff Turn-off propagation delay VHS= 600V, Cload= 2nF ten Device enable delay tr Turn-on rise time tf tdm Min Typ 120 Max Units ns 87 ns 202 ns Cload= 2nF 23 ns Turn-off fall time Cload= 2nF 22 ns Delay matching, HS & LS turn-on/off Cload= 2nF 10 20 Typ Max ns Static Electrical Characteristics Symbol Definition Test Conditions Min VINH Logic “1” input voltage VDD= VCL= 15V 7.0 VINL Logic “0” input voltage VDD= VCC= 15V VHLGO // VHHGO High level output voltage, Units V 6 V IO= 0A 0.28 V IO= 0A .23 V VCH-VHGO or VCL-VLGO VLLGO // VLHGO High level output voltage, VHGO or VLGO IHL HS to LS bias current. VHS= VCH= 600V .17 mA IQHS Quiescent VCH supply current VIN= 0V or VDD .77 mA IQLS Quiescent VCL supply current VIN= 0V or VDD .79 mA IQDD Quiescent VDD supply current VIN= 0V or VDD 36 uA IIN+ Logic “1” input bias current VIN= VDD 2 uA IIN- Logic “0” input voltage VIN= 0V 1 uA VCHUV+ VCH supply undervoltage positive going threshold. 8.3 V VCHUV- VCH supply undervoltage negative going threshold. 8.2 V VCLUV+ VCL supply undervoltage positive going threshold 8.1 V VCLUV- VCL supply undervoltage negative going threshold. 8.0 V IGO+ HS or LS Output low short circuit current; VGO= 15V, VIN= 0V, PW<10us +4 IGO- HS or LS Output low short circuit current; VGO= 15V, VIN=0V, PW<10us A -4 Timing Waveform Definitions ENB HIN/LIN 50% ENB tenb LGO/HGO LGO/HGO Figure 3. INPUT/OUPUT Timing Diagram 10% Figure 4. ENABLE Waveform Definitions 4 A IX4R11 Timing Waveform Definitions Figure 5. Definitions of Switching Time Waforms 50% HIN LIN Figure 6. Definitions of Delay Matching Waveforms 50% 50% tr HIN LIN tdoff tdon 90% 50% Input Signal tf 90% 90% LGO tdm HGO 10% HGO LGO 10% 10% LGO HGO tdm Outgoing Signal 15V + C2 10uF U1 9 10 11 12 13 14 15 16 IX4R11S3 HS NC VDD HIN ENB LIN DG LS HGO VCH HS NC NC VCL LS LGO 8 7 6 5 4 3 2 1 C5 0.1uF L1 200uH C6 0.1uF U2 HGO HS GND2 GND2 D1 DSEI12-10A 100uF/250V + + C3 10uF OUTPUT MONITOR HV SCOPE PROBE C1 15V 1 BATTERY 3 GND1 dVs/dt > 50v/ns HV 600V GND1 2 18V V1 Vout GND Vin 15V V3 BNC PULSE 2 VCC 16 U3 OUT 3 GND2 C8 0.1uF HCPL-314J 1/2 14 VEE 15 GND3 C9 10uF Measure dVdt ( HV Scope Probe ) Q1 U2 2 D2 DSEI12-10A 1,8 6,7 IXDD414 4,5 IXFP4N100Q -600V GND3 Figure 7. Test circuit for allowable offset supply voltage transient. 5 IX4R11 IX4R11S3 Package Outline IX4R11P7 Package Outline IXYS Corporation 3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 e-mail: [email protected] www.ixys.com IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: [email protected] 6 DS99164(04/04)