IXDD408PI / 408SI / 408YI / 408CI 8 Amp Low-Side Ultrafast MOSFET Driver Features General Description • Built using the advantages and compatibility of CMOS and IXYS HDMOSTM processes. • Latch Up Protected • High Peak Output Current: 8A Peak • Operates from 4.5V to 25V • Ability to Disable Output under Faults • High Capacitive Load Drive Capability: 2500pF in <15ns • Matched Rise And Fall Times • Low Propagation Delay Time • Low Output Impedance • Low Supply Current The IXDD408 is a high speed high current gate driver specifically designed to drive the largest MOSFETs and IGBTs to their minimum switching time and maximum practical frequency limits. The IXDD480 can source and sink 8A of peak current while producing voltage rise and fall times of less than 30ns. The input of the driver is compatible with TTL or CMOS and is fully immune to latch up over the entire operating range. Designed with small internal delays, cross conduction/current shootthrough is virtually eliminated in the IXDD408. Its features and wide safety margin in operating voltage and power make the IXDD408 unmatched in performance and value. Applications The IXDD408 incorporates a unique ability to disable the output under fault conditions. When a logical low is forced into the Enable input, both final output stage MOSFETs (NMOS and PMOS) are turned off. As a result, the output of the IXDD408 enters a tristate mode and achieves a Soft Turn-Off of the MOSFET/IGBT when a short circuit is detected. This helps prevent damage that could occur to the MOSFET/IGBT if it were to be switched off abruptly due to a dv/dt over-voltage transient. • • • • • • • • • • Driving MOSFETs and IGBTs Limiting di/dt under Short Circuit Motor Controls Line Drivers Pulse Generators Local Power ON/OFF Switch Switch Mode Power Supplies (SMPS) DC to DC Converters Pulse Transformer Driver Class D Switching Amplifiers The IXDD408 is available in the standard 8-pin P-DIP (PI), SOP-8 (SI), 5-pin TO-220 (CI) and in the TO-263 (YI) surface-mount package. Figure 1 - Functional Diagram Copyright © IXYS CORPORATION 2001 Patent Pending First Release IXDD408PI/408SI//408YI/408CI Absolute Maximum Ratings (Note 1) Operating Ratings Parameter Value Parameter Value Supply Voltage All Other Pins 25 V -0.3 V to VCC + 0.3 V Maximum Junction Temperature Operating Temperature Range Power Dissipation, TAMBIENT ≤25 oC 8 Pin PDIP (PI) 8 Pin SOIC (SI) TO220 (CI), TO263 (YI) Derating Factors (to Ambient) 8 Pin PDIP (PI) 150 oC -40 oC to 85 oC 975mW 1055mW 17W Thermal Impedance (Junction To Case) TO220 (CI), TO263 (YI) (θJC) 0.95 oC/W 8 Pin SOIC (SI) TO220 (CI), TO263 (YI) Storage Temperature Lead Temperature (10 sec) 7.6mW/oC 8.2mW/oC 0.14W/oC -65 oC to 150 oC 300 oC Electrical Characteristics Unless otherwise noted, TA = 25 oC, 4.5V ≤ VCC ≤ 25V . All voltage measurements with respect to GND. IXDD408 configured as described in Test Conditions. Symbol Parameter VIH High input voltage VIL Low input voltage VIN Input voltage range IIN Input current VOH High output voltage VOL Low output voltage ROH Output resistance @ Output high Output resistance @ Output Low Peak output current ROL IPEAK IDC Test Conditions Min 0V ≤ VIN ≤ VCC V V -5 VCC + 0.3 V -10 10 µA VCC - 0.025 V 0.025 V IOUT = 10mA, VCC = 18V 0.8 1.5 Ω IOUT = 10mA, VCC = 18V 0.8 1.5 Ω VCC is 18V 8 VENH High En Input Voltage VENL Low En Input Voltage tR Rise time CL=2500pF Vcc=18V 12 tF Fall time CL=2500pF Vcc=18V tONDLY VCC On-time propagation delay Off-time propagation delay Enable to output high delay time Disable to output low Disable delay time Power supply voltage ICC Power supply current VIN = 3.5V VIN = 0V VIN = + VCC tDOLD Units 0.8 VEN tENOH Max 3.5 Continuous output current Enable voltage range tOFFDLY Typ Limited by package power dissipation - .3 A 2 A Vcc + 0.3 V 2/3 Vcc V 1/3 Vcc V 14 18 ns 13 15 19 ns CL=2500pF Vcc=18V 37 38 42 ns CL=2500pF Vcc=18V 32 34 38 ns Vcc=18V 52 ns Vcc=18V 30 ns 18 25 V 1 0 3 10 10 mA µA µA 4.5 Specifications Subject To Change Without Notice 2 IXDD408PI/408SI/408YI/408CI Pin Configurations I X D D 4 0 8 2 IN 3 EN 4 GND VCC 8 1 2 OUT 7 OUT 6 3 4 GND 5 5 Vcc OUT GND IN EN IX D D 4 0 8 Y I IX D D 4 0 8 C I 1 VCC TO220 (CI) TO263 (YI) 8 PIN DIP (PI) SO8 (SI) Pin Description SYMBOL FUNCTION VCC Supply Voltage IN Input EN Enable OUT Output GND Ground DESCRIPTION Positive power-supply voltage input. This pin provides power to the entire chip. The range for this voltage is from 4.5V to 25V. Input signal-TTL or CMOS compatible. The system enable pin. This pin, when driven low, disables the chip, forcing high impedance state to the output. Driver Output. For application purposes, this pin is connected, through a resistor, to Gate of a MOSFET/IGBT. The system ground pin. Internally connected to all circuitry, this pin provides ground reference for the entire chip. This pin should be connected to a low noise analog ground plane for optimum performance. Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when handling and assembling this component. Figure 2 - Characteristics Test Diagram VIN 3 IXDD408PI/408SI//408YI/408CI Typical Performance Characteristics Fig. 4 Rise Time vs. Supply Voltage Fig. 3 50 100 40 80 Rise Time (ns) Fall Time (ns) CL=10,000 pF 30 4700 pF 20 Fall Time vs. Supply Voltage 60 40 CL=10,000 pF 4700 pF 2200 pF 20 10 2200 pF 0 0 8 10 12 14 16 8 18 10 12 14 16 18 Supply Voltage (V) Supply Voltage (V) Fig. 5 Rise And Fall Times vs. Junction Temperature Fig. 6 CL = 2500pF, VCC = 18V Rise Time vs. Load Capacitance 50 25 8V 40 20 Time (ns) 15 10 Rise Time (ns) 10V tF tR 18V 14V 16V 20 10 5 0 -40 0 2k -20 0 20 40 60 80 100 4k 120 6k 8k 10k Load Capacitance (pF) Temperature (°C) Fig. 7 12V 30 Fig. 8 Fall Time vs. Load Capacitance 90 Max / Min Input vs. Junction Temperature CL=2500pF VCC = 18V 3.2 8V 80 3.0 70 Max / Min Input (V) Fall Time (ns) 60 10V 50 40 12V 30 14V 16V 18V 2.6 2.4 2.2 Maximum Input Low 2.0 20 1.8 10 0 2k Minimum Input High 2.8 4k 6k 8k 1.6 -60 10k Load Capacitance (pF) -40 -20 0 20 40 o Temperature ( C) 4 60 80 100 IXDD408PI/408SI/408YI/408CI Supply Current vs. Load Capacitance Vcc=18V Fig. 9 Fig. 10 Supply Current vs. Frequency Vcc=18V 100 100 CL= 5000 pF 10 Supply Current (mA) Supply Current (mA) 1 MHz 10 500 KHz 100 kHz 1 50 kHz 2500 pF 1000 pF 1 0.1 10 kHz 0.1 0.1k 1.0k 1 10.0k 10 Supply Current vs. Load Capacitance Vcc=12V Fig. 11 100 1000 Frequency (kHz) Load Capacitance (pF) Fig. 12 Supply Current vs. Frequency Vcc=12V 100 100 CL= 5000 pF 10 Supply Current (mA) Supply Current (mA) 10 1 MHz 500 KHz 1 100 kHz 1000 pF 1 0.1 50 kHz 10 kHz 0.1 0.1k 2500 pF 1.0k 1 10.0k 10 Fig. 13 100 1000 Frequency (kHz) Load Capacitance (pF) Fig. 14 Supply Current vs. Load Capacitance Vcc=8V Supply Current vs. Frequency Vcc=8V 100 100 10 2 MHz Supply Current (mA) Supply Current (mA) CL= 5000 pF 10 1 MHz 500 KHz 1 100 kHz 2500 pF 1000 pF 1 0.1 50 kHz 0.1 10 kHz 0.1k 1.0k 1 10.0k 10 100 Frequency (kHz) Load Capacitance (pF) 5 1000 IXDD408PI/408SI//408YI/408CI Fig. 15 Propagation Delay vs. Supply Voltage CL=2500pF VIN=5V@1kHz 70 60 60 50 50 Propagation Delay (ns) Propagation Delay (ns) Propagation Delay vs. Input Voltage CL=2500pF VCC=15V Fig. 16 tONDLY 40 tOFFDLY 30 20 tONDLY 40 tOFFDLY 30 20 10 10 0 0 8 10 12 14 16 2 18 4 6 Fig. 17 8 10 12 Input Voltage (V) Supply Voltage (V) Propagation Delay Times vs. Junction Temperature CL = 2500pF VCC = 18V Fig. 18 60 Quiescent Supply Current vs. Junction Temperature VCC=18V VIN=5V@1kHz 0.66 55 0.64 Quiescent Supply Current (mA) tONDLY 50 Time (ns) 45 40 tOFFDLY 35 30 25 20 15 10 0.62 0.60 0.58 0.56 0.54 -40 -20 0 20 40 60 80 100 120 -40 -20 0 P Channel Peak Output Current vs. Case Temperature CI and YI Packages, CL=.1uF VCC=18V 60 80 Fig. 20 N Channel Peak Output Current vs. Case Temperature CI and YI Packages, CL=.1uF VCC=18V 9 12 11 N Channel Output Current (A) P Channel Output Current (A) 40 Temperature (oC) Temperature (°C) Fig. 19 20 10 9 8 7 6 8 -40 -20 0 20 40 60 80 -40 100 -20 0 20 40 Temperature (oC) o Temperature ( C) 6 60 80 100 IXDD408PI/408SI/408YI/408CI Fig. 21 High State Output Resistance vs. Supply Voltage Fig. 22 Enable Threshold vs. Supply Voltage 14 3 High State Output Resistance (Ohm) Enable Threshold (V) 12 10 2 8 6 1 4 2 0 4 6 8 10 12 14 16 18 20 22 24 0 26 5 10 Fig. 23 15 20 25 Supply Voltage (V) Supply Voltage (V) Low-State Output Resistance vs. Supply Voltage Fig. 24 0 3.0 Vcc vs. P Channel Output Current CL=15nF P Channel Output Current (A) Low-State Output Resistance (Ohms) -2 2.0 1.0 -4 -6 -8 -10 -12 -14 -16 0.0 8 10 15 20 5 25 Supply Voltage (V) Fig. 25 10 N Channel Output Current (A) 6 4 2 0 15 20 20 25 Figure 26 - Typical Application Short Circuit di/dt Limit Vcc vs. N Channel Output Current CL=15nF 10 15 Vcc 8 5 10 25 30 Vcc 7 30 IXDD408PI/408SI//408YI/408CI APPLICATIONS INFORMATION Short Circuit di/dt Limit ground. (Those glitches might cause false triggering of the comparator). A short circuit in a high-power MOSFET module such as the VM0580-02F, (580A, 200V), as shown in Figure 26, can cause the current through the module to flow in excess of 1500A for 10µs or more prior to self-destruction due to thermal runaway. For this reason, some protection circuitry is needed to turn off the MOSFET module. However, if the module is switched off too fast, there is a danger of voltage transients occuring on the drain due to Ldi/dt, (where L represents total inductance in series with drain). If these voltage transients exceed the MOSFET's voltage rating, this can cause an avalanche breakdown. The comparator's output should be connected to a SRFF(Set Reset Flip Flop). The flip-flop controls both the Enable signal, and the low power MOSFET gate. Please note that CMOS 4000series devices operate with a VCC range from 3 to 15 VDC, (with 18 VDC being the maximum allowable limit). A low power MOSFET, such as the 2N7000, in series with a resistor, will enable the VMO580-02F gate voltage to drop gradually. The resistor should be chosen so that the RC time constant will be 100us, where "C" is the Miller capacitance of the VMO580-02F. The IXDD408 has the unique capability to softly switch off the high-power MOSFET module, significantly reducing these Ldi/dt transients. For resuming normal operation, a Reset signal is needed at the SRFF's input to enable the IXDD408 again. This Reset can be generated by connecting a One Shot circuit between the IXDD408 Input signal and the SRFF restart input. The One Shot will create a pulse on the rise of the IXDD408 input, and this pulse will reset the SRFF outputs to normal operation. Thus, the IXDD408 helps to prevent device destruction from both dangers; over-current, and avalanche breakdown due to di/dt induced over-voltage transients. The IXDD408 is designed to not only provide ±8A under normal conditions, but also to allow it's output to go into a high impedance state. This permits the IXDD408 output to control a separate weak pull-down circuit during detected overcurrent shutdown conditions to limit and separately control dVGS/dt gate turnoff. This circuit is shown in Figure 27. When a short circuit occurs, the voltage drop across the lowvalue, current-sensing resistor, (Rs=0.005 Ohm), connected between the MOSFET Source and ground, increases. This triggers the comparator at a preset level. The SRFF drives a low input into the Enable pin disabling the IXDD408 output. The SRFF also turns on the low power MOSFET, (2N7000). Referring to Figure 27, the protection circuitry should include a comparator, whose positive input is connected to the source of the VM0580-02. A low pass filter should be added to the input of the comparator to eliminate any glitches in voltage caused by the inductance of the wire connecting the source resistor to In this way, the high-power MOSFET module is softly turned off by the IXDD408, preventing its destruction. Figure 27 - Application Test Diagram + Ld 10uH VCC VCCA Rg OUT IN EN VCC + - VIN High_Power VMO580-02F 1ohm Rsh 1600ohm GND SUB Rs Low_Power 2N7002/PLP Ls R+ 10kohm 20nH One ShotCircuit Rcomp 5kohm NAND CD4011A NOT1 CD4049A NOT2 CD4049A Ccomp 1pF Ros 0 Comp LM339 + V+ V- C+ 100pF + R 1Mohm REF Cos 1pF Q NOT3 CD4049A NOR1 CD4001A EN NOR2 CD4001A SR Flip-Flop 8 VB Rd 0.1ohm IXDD408 + - - S - IXDD408PI/408SI/408YI/408CI Supply Bypassing and Grounding Practices, Output Lead inductance TTL to High Voltage CMOS Level Translation When designing a circuit to drive a high speed MOSFET utilizing the IXDD408, it is very important to keep certain design criteria in mind, in order to optimize performance of the driver. Particular attention needs to be paid to Supply Bypassing, Grounding, and minimizing the Output Lead Inductance. The enable (EN) input to the IXDD408 is a high voltage CMOS logic level input where the EN input threshold is ½ VCC, and may not be compatible with 5V CMOS or TTL input levels. The IXDD408 EN input was intentionally designed for enhanced noise immunity with the high voltage CMOS logic levels. In a typical gate driver application, VCC =15V and the EN input threshold at 7.5V, a 5V CMOS logical high input applied to this typical IXDD408 application’s EN input will be misinterpreted as a logical low, and may cause undesirable or unexpected results. The note below is for optional adaptation of TTL or 5V CMOS levels. Say, for example, we are using the IXDD408 to charge a 5000pF capacitive load from 0 to 25 volts in 25ns… Using the formula: I= ∆V C / ∆t, where ∆V=25V C=5000pF & ∆t=25ns we can determine that to charge 5000pF to 25 volts in 25ns will take a constant current of 5A. (In reality, the charging current won’t be constant, and will peak somewhere around 8A). SUPPLY BYPASSING In order for our design to turn the load on properly, the IXDD408 must be able to draw this 5A of current from the power supply in the 25ns. This means that there must be very low impedance between the driver and the power supply. The most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is a magnitude larger than the load capacitance. Usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (These capacitors should be carefully selected, low inductance, low resistance, high-pulse currentservice capacitors). Lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the IXDD408 to an absolute minimum. GROUNDING In order for the design to turn the load off properly, the IXDD408 must be able to drain this 5A of current into an adequate grounding system. There are three paths for returning current that need to be considered: Path #1 is between the IXDD408 and it’s load. Path #2 is between the IXDD408 and it’s power supply. Path #3 is between the IXDD408 and whatever logic is driving it. All three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. In addition, every effort should be made to keep these three ground paths distinctly separate. Otherwise, (for instance), the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the IXDD408. The circuit in Figure 28 alleviates this potential logic level misinterpretation by translating a TTL or 5V CMOS logic input to high voltage CMOS logic levels needed by the IXDD408 EN input. From the figure, VCC is the gate driver power supply, typically set between 8V to 20V, and VDD is the logic power supply, typically between 3.3V to 5.5V. Resistors R1 and R2 form a voltage divider network so that the Q1 base is positioned at the midpoint of the expected TTL logic transition levels. A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied to the Q1 emitter will drive it on. This causes the level translator output, the Q1 collector output to settle to VCESATQ1 + VTTLLOW=<~2V, which is sufficiently low to be correctly interpreted as a high voltage CMOS logic low (<1/3VCC=5V for VCC =15V given in the IXDD408 data sheet.) A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high, V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in Figure 28 will cause Q1 to be biased off. This results in Q1 collector being pulled up by R3 to VCC=15V, and provides a high voltage CMOS logic high output. The high voltage CMOS logical EN output applied to the IXDD408 EN input will enable it, allowing the gate driver to fully function as an 8 Amp output driver. The total component cost of the circuit in Figure 28 is less than $0.10 if purchased in quantities >1K pieces. It is recommended that the physical placement of the level translator circuit be placed close to the source of the TTL or CMOS logic circuits to maximize noise rejection. Figure 28 - TTL to High Voltage CMOS Level Translator CC (From Gate Driver Power Supply) OUTPUT LEAD INDUCTANCE Of equal importance to Supply Bypassing and Grounding are issues related to the Output Lead Inductance. Every effort should be made to keep the leads between the driver and it’s load as short and wide as possible. If the driver must be placed farther than 2” from the load, then the output leads should be treated as transmission lines. In this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connect directly to the ground terminal of the load. VDD (From Logic Power Supply) 10K 3.3K R3 High Voltage CMOS EN Output R1 Q1 2N3904 3.3K or TTL Input) 9 R2 (To IXDD408 EN Input) IXDD408PI/408SI//408YI/408CI Package Information NOTE: Mounting or solder tabs on all packages are connected to ground IXYS Corporation 3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 e-mail: [email protected] Ordering Information P a rt N u m b e r IX D D 4 0 8 P I IX D D 4 0 8 S I IX D D 4 0 8 Y I IX D D 4 0 8 C I P ackag e T ype 8 -P in P D IP 8 -P in S O IC 5 -P in T O -2 6 3 5 -P in T O -2 2 0 Tem p. R ange -4 0 °C to + 8 5 ° C -4 0 °C to + 8 5 ° C -4 0 °C to + 8 5 ° C -4 0 °C to + 8 5 ° C IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: [email protected] Directed Energy, Inc. An IXYS Company 2401 Research Blvd. Ste. 108 Ft. Collins, CO 80526 Tel: 970-493-1901; Fax: 970-493-1903 e-mail: [email protected] 10 Doc #9200-0227 R7