TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 DUAL OUTPUT BOOST REGULATOR USING SINGLE INDUCTOR FEATURES • • • • • • • • • • • • • • DESCRIPTION 3V to 6 V Input Voltage Range Two Outputs Each up to 27 V 0.7 A Integrated Switch Built-in Power Diode 1.2 MHz PWM for WLED Driver PFM for OLED Supply Individually Programmable Output Input to Output Isolation Short-Circuit Protection Built-in Soft Start Overvoltage Protection Up to 82% Efficiency Up to 30 kHz PWM Dimming Frequency Available in a 10 Pin, 3 × 3 mm QFN Package The TPS61140/1 is a dual output boost converter IC. It is intended to be configured as a highly integrated power solution providing regulated voltage and current output with one boost converter. This device is ideal for driving the OLED sub display and WLED backlight for the LCD main display in clam shell phones. The voltage and current can be individually programmed through external resistors. There is a dedicated selection pin for each output, so the two outputs can be turned on separately or simultaneously. When only the voltage output is enabled, the boost converter is controlled by pulse frequency modulation (PFM) in order to achieve high efficiency over a wide load range. If the current output is selected, the device adopts a 1.2 MHz pulse width modulation control (PWM) method in order to maximize output current. Applying an external PWM signal to the select pin (SELI) reduces the output current thereby allowing WLED dimming. APPLICATIONS • The TPS61140/1 has a built-in power MOSFET and power diode; thereby, eliminating the needs for any external active power components. In addition, the high switching frequency reduces the external inductor and capacitor sizes. Overall, the IC provides a highly compact solution with high efficiency and plenty of flexibility. Clamshell Phone With OLED/LCD Screen TYPICAL APPLICATION 3 V to 6 V Input L1 10 mH C1 4.7 mF SW Iout Vin Vout GND R1 SELI ISET IFB C3 1 mF R2 OLED VFB SEL V C2 4.7 mF R3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PACKAGE OVP (typ) PACKAGE MARKING –40 to 85°C TPS61140DRCR 28V BCP –40 to 85°C TPS61141DRCR 22V BRG –40 to 85°C TPS61140DRCT 28V BCP –40 to 85°C TPS61141DRCT 22V BRG DEVICE INFORMATION 10 pin 3*3 mm QFN PACKAGE (TOP VIEW) Vout 1 10 IFB VFB 2 9 Iset SELV 3 8 GND SELI 4 7 Iout Vin 5 6 SW Exposed Thermal Pad TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION VIN 5 I The input pin to the IC. It provides the current to the boost regulator output, and also powers the IC circuit. When the Vin voltage is below the undervoltage lockout threshold, the IC turns off and disables outputs. GND 8 O The ground of the IC. Connect the input and output capacitors very close to this pin. SW 6 I This is the switching node of the IC where the PWM switching Is created. IOUT 7 O The output of the constant current supply. It is directly connected to the boost regulator output. VOUT 1 O The output of the voltage regulator. There is a low dropout linear regulator (LDO) between the Iout and Vout pins which regulates the Vout voltage. Turning off the LDO disconnects the Vout from Iout. VFB 2 I The voltage feedback pin for Vout regulation. It is regulated to an internal reference voltage. An external voltage divider connected to this pin programs the output voltage. IFB 10 I The return path for the Iout regulation. The current regulator is connected to this pin, and it can be disabled by opening the current path. ISET 9 I The current output programming pin. The resistor connected to the pin programs the regulated current of the Iout pin. SELI, SELV 4,3 I Mode selection pins. See Table 1 for details. Thermal Pad 2 The thermal pad should be soldered to the analog ground. If possible, use thermal via to connect to ground plane for ideal power dissipation. Submit Documentation Feedback TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 Table 1. TPS61140/1 mode selection SELV SELI Vout Iout H L Enable Disable L H Disable Enable H H Enable Enable L L IC Shutdown FUNCTIONAL BLOCK DIAGRAM Iout Q2 Q1 VIN C1 + − Vout Level Shift GND OLED A1 C3 1.229 V SEL V VFB PWM/PFM Control Logic C2 IFB Q3 Current Sink SELI TPS61140/1 ISET ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Supply voltages on pin VIN (2) Voltages on pins SELI, SELV, ISET and VFB (2) Voltage on pin Iout, SW, Vout and IFB (2) Total output current on pin Iout and pin Vout Continuous power dissipation VALUE UNIT –0.3 to 7 V –0.3 to 7 V 30 V 50 mA See Dissipation Rating Table Operating junction temperature range –40 to 150 °C Storage temperature range –65 to 150 °C 260 °C Lead temperature (soldering, 10 sec) (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Submit Documentation Feedback 3 TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 DISSIPATION RATINGS RθJA TA≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING QFN (1) 270°C/W 370 mW 204 mW 148 mW QFN(2) 48.7°C/W 2.05 W 1.13 W 821 mW PACKAGE RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX Vin Input voltage range 3.0 6.0 Vout Output voltage range Vin 27 L Inductor (1) Ci Input capacitor (1) UNIT V V µH 10 µF 4.7 Iout (1) Output capacitor on CO2 Output capacitor on Vout TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C (1) 1 µF CO1 (1) 4.7 µF 1 See Application Section for further information. ELECTRICAL CHARACTERISTICS Vin = 3.6 V, SELx = Vin, Rset = 80 kΩ, Vout=15V, Viout=15V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT Vin Input voltage range 3.0 6.0 Device not switching IQ Operating quiescent current into Vin IQ_Iout Operating quiescent current into Iout ISD Shutdown current SELx = GND VUVLO Under-voltage lockout threshold Vin falling Vhys Under-voltage lockout hysterisis 0.125 Device PWM switching no load 2 1.65 V mA 50 µA 1.5 µA 1.8 70 V mV ENABLE AND SOFT START Vselh SEL logic high voltage Vin = 2.7 V to 6 V Vsell SEL logic low voltage Vin = 2.7 V to 6 V Ren Enable pull down resistor Toff EN pulse width to disable Kss IFB soft start current steps Tss Soft start time step Measured as clock divider Tss_en Soft start enable time Time between falling and rising edges of two adjacent SELI pulses 4 1.2 300 EN high to low V 0.4 700 40 V kΩ ms 16 Submit Documentation Feedback 64 40 ms TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS (Continued) Vin = 3.6 V, SELx = Vin, Rset = 80 kΩ, Vout=15V, Viout=15V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 100 nA 1.204 1.229 1.254 V 1.204 1.229 1.254 V 820 900 990 300 330 360 VOLTAGE AND CURRENT CONTROL IFB Voltage feedback input bias current VFB Voltage feedback regulation voltage VISET ISET pin voltage KISET Current multipler VIFB IFB Regulation voltage VFB = 1.229 V Iout/Iset (1) 60 mV VIFB_L IFB low threshold Tisink Current sink settle time Measured from SELx rising edge (2) 6 µs Ileak IFB pin leakage current IFB voltage = 25 V 1 µA Vdelta Iout-Vout regulation threshold Iout-Vout 380 mV Vdelta_l Iout-Vout low threshold (3) ILDO_leak LDO leakage current Iout = 25 V, Vout = 0 V PSRR LDO PSRR Iout–Vout = 330 mV, 2 mA, 20 kHz 20 0.6 270 330 mV 45 mV 1 µA dB POWER SWITCH AND DIODE RDS(ON) N-channel MOSFET on-resistance VIN = VGS = 3.6 V ILN_NFET N-channel leakage current VDS = 25 V VF Power diode forward voltage Id = 0.7 A 0.9 Ω 1 µA 0.83 1.0 V OC AND OVP Dual output, V(Iout)=15V, D=76% 0.75 1.0 1.26 Single output (PFM) 0.27 0.32 0.38 Single output (PWM), V(Iout)=15V, D=76% 0.40 0.55 0.70 ILIM N-Channel MOSFET current limit (4) ILDO_MAX LDO max output current Iout–Vout = 330 mV 35 IIFB_MAX Current sink max output current IFB = 330 mV 35 TPS61140 27 28 29 TPS61141 21 22 23 Vovp Overvoltage threshold Vovp_hys Overvoltage hysteresis A mA mA TPS61140 550 TPS61141 440 V mV PWM AND PFM CONTROL fS Oscillator frequency Dmax Maximum duty cycle PWM, VFB = 1.0 V 1.0 1.2 90 93 Ton_max Maximum on time Toff_min Minimum off time 1.5 MHz % PFM only 5.7 µs PFM only 413 ns 160 °C 15 °C THERMAL SHUTDOWN Tshutdown Thermal shutdown threshold Thys Thermal shutdown threshold hysteresis (1) (2) (3) (4) When the IFB pin voltage drops this amount below VIFB, the IFB pin is used as the boost converter feedback if the Iout-Vout voltage is in regulation. This only occurs in BOTH-ON mode. This specification determines the minimum on time required for PWM dimming. Using this specification, the maximum PWM dimming frequency can be calculated from the minimum duty cycle required in the application. When Iout-Vout voltage drops this amount below Vdelta, Iout-Vout is used as the boost rconverter feedback input regardless of the IFB voltage. This only occurs in BOTH-ON mode. Measured with DC current. See APPLICATION INFORMATION for details. Submit Documentation Feedback 5 TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS Table of Graphs TITLE CONDITIONS FIGURES K value over current Vin = 3.6 V, Iload = 2 mA to 25 mA Figure 1 OLED efficiency vs load current Vin = 3.3 V, 3.6 V and 4.0 V, Vout = 15 V Figure 2 WLED efficiency vs load current Vin = 3.3 V, 3.6 and 4.0 V, 3 WLED, WLED voltage = 11 V Figure 3 WLED efficiency vs load current Vin = 3.3 V, 3.6 V and 4.0 V, 4 WLED, WLED voltage = 15 V Figure 4 WLED efficiency vs load current Vin = 3.3 V, 3.6 V and 4.0 V, 5 WLED, WLED voltage = 19 V Figure 5 WLED efficiency vs load current Vin = 3.3 V, 3.6 V and 4.0 V, 6 WLED, WLED voltage = 23 V Figure 6 OLED load regulation Vin = 3.6 V, Iout = 15 V, Iload = 2 mA to 20 mA Figure 7 OLED line regulation Vin = 3.0 V to 5 V, Iout = 15 V, Iload = 10 mA OLED ripple voltage waveform Vin = 3.6 V, Vout = 15 V, Iload = 20, 2mA Figure 8 Figure 9, 10 WLED PWM dimming waveform Figure 11 WLED PWM dimming linearity Frequency = 20 kHz and 30 KHz Figure 12 Trainsition between OLED+WLED and OLED only 4 WLED and Vout=15V Figure 13 WLED start up waveform Figure 14 OLED start up waveform Figure 15 PWM Mode Overcurrent Limit WLED Only Figure 16 PWM Mode Overcurrent Limit WLED + OLED Figure 17 K VALUE vs WLED CURRENT EFFICIENCY vs OLED CURRENT 85 950 VI = 3.6 V, WLED Voltage = 15 V 83 910 81 890 79 Efficiency - % K - Value 930 870 850 830 77 Vin = 3.6 V Vin = 3.3 V 73 71 790 69 770 67 65 0 2 4 6 8 10 12 14 16 18 20 22 24 WLED - Current - mA 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 1718 19 20 OLED Current - mA Figure 1. 6 Vin = 4 V 75 810 750 Vout = 15 V, SELV = High SELI = Low Figure 2. Submit Documentation Feedback TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 EFFICIENCY vs WLED CURRENT EFFICIENCY vs WLED CURRENT 90 90 WLED Voltage = 15 V, 4 WLED VSEL = low ISEL = high WLED Voltage = 11 V, 3 WLED, VSEL = Low, ISEL = high VI = 3.3 V VI = 3.6 V 70 VI = 3.6 V 80 Efficiency - % Efficiency - % 80 VI = 3.3 V 70 VI = 4 V VI = 4 V 60 60 50 50 90 5 10 15 IL - Load Current - mA Figure 3. Figure 4. EFFICIENCY vs WLED CURRENT EFFICIENCY vs WLED CURRENT 15 WLED Voltage = 19 V, 5 WLED VSEL = low ISEL = high VI = 4 V 80 Efficiency - % IL - Load Current - mA 10 20 90 5 60 25 20 25 VI = 3.6 V 80 VI = 3.3 V 20 WLED Voltage = 23 V, 6 WLED VSEL = low ISEL = high VI = 4 V VI = 3.6 V 70 50 0 0 25 Efficiency - % 0 VI = 3.3 V 70 60 50 5 10 15 IL - Load Current - mA 20 25 0 5 10 15 IL - Load Current - mA Figure 5. Figure 6. Submit Documentation Feedback 7 TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 OLED LOAD REGULATION OLED LINE REGULATION 14.95 14.94 OLED Current = 10 mA VI = 3.6 V 14.94 VO - Output Voltage - V VI - Input Voltage - V 14.93 14.92 14.93 14.92 14.91 14.91 14.90 14.90 2 4 6 8 10 12 14 16 IL - Load Current - mA 18 20 3 3.4 3.6 3.8 4 4.2 4.4 VI - Input Voltage - V 4.6 4.8 Figure 7. Figure 8. OLED RIPPLE UNDER 20 mA LOAD (PFM MODE) OLED RIPPLE UNDER 2 mA LOAD (PFM MODE) VO 10 mV/div, AC VO 10 mV/div, AC IO 50 mV/div, AC IO 50 mV/div, AC Inductor Current 200 mA/div, DC Inductor Current 200 mV/div, AC t - Time - 2 ms/div Figure 9. 8 3.2 t - Time - 20 ms/div Figure 10. Submit Documentation Feedback 5 TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 WLED PWM BRIGHTNESS DIMMING WLED PWM BRIGHTNESS DIMMING LINEARITY 25 ISEL 2 5 V/div, DC 20 WLED Current - mA SW 10 V/div, DC IO 1 V/div, DC 15 V Offset Inductor Current 20 mA/div, DC 15 10 f = 20 kHz 5 f = 30 kHz t - Time - 20 ms/div 0 0 20 40 60 PWM Duty cycle - % Figure 11. Figure 12. TRANSITION BETWEEN 4WLED+OLED AND OLED ONLY (SELV ALWAYS HIGH) WLED START UP 80 100 SELI 5 V/div, DC SELI 5 V/div, DC IO 200 mV/div, AC IO Pin 10 V/div, DC Inductor Current 500 mA/div, DC VO 200 mV/div, AC WLED Current 20 mA/div, DC WLED Current 20 mA/div, DC t - Time - 1 ms/div Figure 13. t - Time - 200 ms/div Figure 14. Submit Documentation Feedback 9 TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 OLED START UP PWM MODE OVERCURRENT LIMIT (WLED Only) vs DUTY CYCLE SELV 5 V/div, DC 600 IO Pin 10 V/div, DC 500 VI = 4.2 V Current Limit - mA VI = 3.6 V VO 10 V/div, DC Inductor Current 200 mA/div, DC 400 VI = 3 V 300 200 100 t - Time - 1 ms/div 0 10 20 30 40 50 60 Duty Cycle - % Figure 15. Figure 16. PWM MODE OVERCURRENT LIMIT (WLED+OLED) vs DUTY CYCLE 1200 Vin = 3 V Current Limit - mA 1000 800 Vin = 3.6 V Vin = 4.2 V 600 400 200 0 10 20 30 40 50 60 70 Duty Cycle - % Figure 17. 10 Submit Documentation Feedback 80 90 70 80 90 TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 DETAILED DESCRIPTION The TPS61140/1 uses a single boost converter to provide pre-regulated power for the device’s current output and voltage output. The current output is regulated by a low side current sink connected to the IFB pin, while a low dropout linear regulator (LDO) on the output of the boost regulator provides the voltage output. The LDO is used for its low ripple and fast transient response. The device automatically sets the boost output voltage to minimize power losses of the linear circuits (i.e., the current sink and LDO), and yet provide enough headroom for their DC operation and transient response. Such an implementation takes advantage of the high quality output of linear circuits, while maintaining high efficiency offered by the boost converter. VOLTAGE OUTPUT MODE When only the voltage output is enabled (i.e., SELV high and SELI low), LDO pass element Q2, shown in the block diagram, regulates Vout per the external resistor divider connected to the VFB pin. Current sink Q3 turns off, thereby opening the current path. The boost converter operates in PFM (pulse frequency modulation) mode for high efficiency over a wide load range. Operating in PFM mode, the device turns on the power switch Q1 when the voltage drop across the LDO (i.e., V(IOUT)–VOUT) falls below the regulation voltage (Vdelta). The input voltage is applied across the inductor, and its current linearly increases until reaching current limit, upon which Q1 is turned off. At this time, the built-in power diode is then forward biased and releases the inductor energy to the output. After the minimum off time, Q1 is allowed to turn back on again only if the voltage across the LDO is still below the threshold. Otherwise, Q1 stays off to reduce the switching losses and IC quiescent current. The minimum off time ensures discontinuous operation (DCM) in which inductor current always ramps down to zero in each switching cycle. DCM operation is required for feedback loop stability. There is also a maximum Q1 on time which turns off Q1 even if the current is still below the current limiting threshold. By minimizing the voltage drop across the LDO, the LDO maintains high efficiency. For 15V output, the LDO accounts for approximately 2% of efficiency loss. Because PFM control reduces the switch frequency at light load, the boost regulator produces higher output ripple. Fortunately, the LDO’s high PSRR (power supply rejection ratio) attenuates the ripple on the VOUT pin for optimal OLED display performance. The output voltage of the Vout pin can be programmed by the resistor divider connected to the VFB pin, as shown in the Typical Application. R1 Vout VFB R1 R2 (1) Where VFB = reference voltage of the VFB pin CURRENT OUTPUT MODE When only the current output is selected (i.e., SELV low and SELI high), the LDO, and therefore VOUT is turned off, and the current sink device Q3, shown in the block diagram, regulates the current output. The boost converter uses fixed frequency PWM control to provide high output current and low output ripple noises. In this mode, the feedback loop regulates the IFB pin to a threshold voltage (VIFB), giving current sink circuit minimum headroom to operate and minimizing losses across the current sink circuit. The regulation current is set by the resistor on the Iset pin based on V I O ISET KISET RSET (2) where Io = output current VISET = Iset pin voltage (1.229V typical) RSET = Iset pin resistor value KISET = current multiplier (900 typical) Submit Documentation Feedback 11 TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 DETAILED DESCRIPTION (continued) BOTH ON MODE When both the voltage and current outputs are enabled (i.e., SELV high and SELI high), the boost converter operates in the PWM mode and regulates to the one requiring higher IOUT pin voltage by choosing the smaller of V(IOUT)–VOUT and V(IFB) as the feedback signal. For example, if voltage regulation requires higher boost output, V(IOUT)–VOUT is automatically selected as feedback signal for the boost converter. During this time, the IFB pin voltage is higher than its regulation voltage (VIFB). However, if the IFB pin voltage drops below its regulation voltage by the IFB low threshold (VIFB_L), the PWM loop switches its feedback path to the IFB pin to ensure the proper operation of current sink circuit. The same operation occurs if the current output requires higher boost output. When both V(IOUT)–VOUT and V(IFB) are below their respective low thresholds, the V(IOUT)–VOUT takes priority as the boost converter's feedback signal. The overall efficiency in this mode depends on the voltage difference between the current and voltage loads. A large difference reduces the efficiency due to additional power losses across the linear circuits (i.e., either the LDO or current sink circuit). START UP During start up, two feedback loops for the boost converter and linear regulators, are trying to establish steady state simultaneously. Figure 14 and Figure 15 demonstrate the start up waveform for WLED only and OLED only outputs. When only the voltage output is enabled, the Vout ramp time is set by the LDO. The LDO uses an internal RC circuit to slow down the startup ramp and limit in-rush current. The boost converter output V(IOUT) ramps up with the LDO output VOUT maintaining a fixed voltage across the LDO. The boost converter charges both C2 and C3 shown in the block diagram, and the peak inductor current is clamped by the overcurrent limit circuitry. When only the current output is enabled, Q3 control circuitry ramps up the sink current in 16 steps with each step taking 64 clock cycles. This soft start mode makes the current sink loop slower than the boost converter’s loop. Therefore, the boost output can only slowly comes up as the current sink circuitry increases its needed voltage. This ensures smooth start up and avoids any in rush current. Soft start is also important for transitioning from voltage only to both on mode. During transition, soft start slowly adds the load, thereby giving the boost converter enough time to ramp the inductor current and preventing LDO drop out or VOUT voltage dip. OVERVOLTAGE PROTECTION To prevent the boost output run away as the result of WLED disconnection, there is an overvoltage protection (OVP) circuit which stops the boost converter from switching as soon as its output exceeds the OVP threshold. When the voltage falls below the OVP threshold, the converter resumes switching. The two OVP options offer the choices to prevent a 25V rated output capacitor or the internal 30-V FET from breaking down. UNDERVOLTAGE LOCKOUT An undervoltage lockout prevents mis-operation of the device for input voltages below 1.65 V (typical). When the input voltage is below the undervoltage threshold, the device remains off and both the boost converter and linear circuit are turned off, providing isolation between input and output. THERMAL SHUTDOWN An internal thermal shutdown turns off the IC when the typical junction temperature of 160°C is exceeded. The thermal shutdown has a hysteresis of typically 15°C. 12 Submit Documentation Feedback TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 DETAILED DESCRIPTION (continued) ENABLE Pulling either the SELI or SELV pin low turns off the corresponding output. If both SELI and SELV are low for more than 40 ms, the IC shuts down and consumes less than 1 µA current. When only the current output is selected for driving WLED, the SELI pin can be used for PWM brightness dimming. To improve PWM dimming linearity, soft start is disabled if the time between falling and rising edges of two adjacent SELI pulses is less than 40 ms. See APPLICATION INFORMATION for details on PWM dimming. Each SELx input pin has an internal pull down resistor to disable the device when the pin is floating. Submit Documentation Feedback 13 TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 APPLICATION INFORMATION MAXIMUM OUTPUT CURRENT – PWM CONTROL The over-current limit in a boost converter limits the maximum input current and thus maximum input power for a given input voltage. Maximum output power is less than maximum input power due to power conversion losses. Therefore, the current limit setting, input voltage, output voltage and efficiency can all change maximum current output. Since current limit clamps peak inductor current, ripple has to be subtracted to derive maximum DC current. The ripple current is a function of switching frequency, inductor value and duty cycle. The following equations take into account of all the above factors for maximum output current calculation. 1 Ip 1 L 1 Fs VioutVfVin Vin (3) where Ip = inductor peak to peak ripple L = inductor value Vf = power diode forward voltage Fs = Switching frequency Viout = boost output voltage. It is equal to the higher of either 330mV+Vout or 330mV+voltage drop across WLED. Vin Iout_max Ilim Ip 2 Viout (4) where Iout_max = Maximum output current of the boost converter Ilim = overcurrent limit η = efficiency To keep a tight range of the overcurrent limit, The TPS61140/1 uses the Vin and Iout pin voltage to compensate for the overcurrent limit variation caused by the slope compensation. However, the current threshold still has residual dependency on the Vin and Iout voltage. Use Figure 16 and Figure 17 to identify the typical overcurrent limit in your application, and use ±25% tolerance to account for temperature dependency and process variations. The maximum output current can also be limited by the current capability of the LDO and the current sink circuitry. Both are designed to provide maximum 35 mA current regardless of the current capability of the boost converter. MAXIMUM OUTPUT CURRENT – PFM CONTROL When only voltage output is selected, the boost operates in PFM mode, and the maximum output current can be calculated as, LI lim T on V in (5) LI lim T off V Vƒ V iout in (6) I out_max T on T V off lim IN 2V T on T iout off_min I Toff_min = minimum off time 14 Submit Documentation Feedback (7) TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) To estimate worse case maximum output current, use following conditions Vin = lowest input voltage Vf =1.0 V In applications, overcurrent limit Ilim in the PFM mode is typically 60mA higher than the value listed in the ELECTRICAL CHARACTERISTICS which is measured with DC current. In reality, the inductor current ramps pass specification value due to the delay of the overcurrent limit comparator. The LDO has 35 mA maximum output current, regardless of the current output capability of the boost converter. WLED BRIGHTNESS DIMMING There are three ways to dynamically change the output current 'on the fly'' for WLED dimming. The first method parallels an additional resistor with the ISET pin resistor as shown in Figure 18 . The switch, Q1, can change the ISET pin resistance, and therefore modify the output current. This method is very simple, but can only provide limited dimming steps. ISET R1 RISET Q1 ON/OFF Logic Figure 18. Switching In/Out an Additional Resistor to Change Output Current Alternatively, a PWM dimming signal at the SELI pin will modulate the output current by the duty cycle of the signal. The logic high of the signal turns on the current sink circuit, while the logic low turns it off. This operation creates an averaged DC output current proportional to the duty cycle of the PWM signal. The frequency of the PWM signal must be high enough to avoid flashing of the WLEDs. The soft start of the current sink circuit is disabled during the PWM dimming to improve linearity. PWM dimming in the audible frequency range can cause audible noises from the inductor and/or output capacitor of the boost converter. A voltage ripple in the audible frequency range causes the output capacitor to vibrate at the same frequency. Because the TPS61140/1 disconnects the WLEDs from the output capacitor when the SELI pin is low, the output capacitor is not discharged by the WLEDs, which reduces the voltage ripple, and potential for audible noise from the output capacitor. Audible noises from both the inductor and output capacitor can be prevented by using a PWM dimming frequency above or below the audible frequency range. The maximum PWM dimming frequency of the TPS61140/1 is determined by the current settling time (Tisink) which is the time required for the circuit sink circuit to reach steady state after the SELI pin transitions from low to high. The maximum dimming frequency can be calculated by D F PWM_MAX T min isink (8) Dmin = min duty cycle of the PWM dimming required in the application. For 20% Dmin, PWM dimming frequency up to 33 kHz is possible, which is above the audible range. The third method uses an external DC voltage and resistor as shown in Figure 19 to change the ISET pin current, and thus control the output current. The DC voltage can be the output of a filtered PWM signal. The equation to calculate the output current is either Submit Documentation Feedback 15 TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) I WLED K ISET 1.229 R ISET 1.229 V R1 for DC voltage input for PWM signal input DC (9) OR I WLED K ISET 1.229 V 1.229 DC R R 1 10K ISET (10) where KISET = current multiplier between the ISET pin current and the IFB pin current. VDC= voltage of the DC voltage source or the DC value of the PWM signal source. ISET ISET Filter PWM Signal R1 RISET DC Voltage 10 k 0.1 F R1 RISET Figure 19. Analog Dimming Uses an External Voltage Source to Control the Output Current INDUCTOR SELECTION Because the selection of the inductor affects the power supply's steady state operation (e.g., efficiency and output ripple), transient behavior and loop stability, the inductor is the most important component in power regulator design. There are three specifications most important to the performance of the inductor, inductor value, DC resistance and saturation current. Considering inductor value alone is not enough. The inductor’s inductance value determines the inductor ripple current. It is generally recommended setting the peak to peak ripple current given by Equation 3 to 30–40% of the DC current. It is a good compromise of power losses and inductor size. For this reason, 10 µH inductors are recommended for TPS61140/1. Inductor DC current can be calculated as V I out I iout L_DC V in (11) Use the maximum load current and minimum Vin for calculation. The internal loop compensation for PWM control is optimized for the external component values, including typical tolerances, shown in the typical application circuit. Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation level, its inductance can decrease 20 to 35% from the 0A value depending on how the inductor vendor defines saturation. Using an inductor with a smaller inductance value forces discontinuous PWM operation in which the inductor current ramps down to zero before the end of each switching cycle. It reduces the boost converter’s maximum output current, and causes large input voltage ripple. An inductor with larger inductance will reduce the gain and phase margin of the feedback loop, possibly resulting in instability. Inductor selection is also important for PFM operation. As seen in I(out_max) calculation, the maximum output current in PFM mode goes up with the inductor’s inductance value. A smaller value inductor, such as 4.7 µH, reduces the available output current, while a larger inductor raises the risk of instability by entering continuous operation. 16 Submit Documentation Feedback TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) Regulator efficiency is dependent on the resistance of its high current path and switching losses associated with the PWM switch and power diode. Although the TPS61140/1 has optimized the internal switches, the overall efficiency still relies on inductor’s DC resistance (DCR); Lower DCR improves efficiency. However, there is a trade off between DCR and inductor size, furthermore, shielded inductors typically have higher DCR than unshielded ones. DCR in range of 150 mΩ to 350 mΩ is suitable for applications requiring both on mode. DCR is the range of 250 mΩ to 450 mΩ is a good choice for single output application. Table 2 and Table 3 list recommended inductor models. Table 2. Recommended Inductors for Single Output L (µH) DCR Typ (mΩ) Isat (A) SIZE (L×W×H mm) VLF3012AT-100MR49 10 360 0.49 2.8×3.0×1.2 VLCF4018T-100MR74-2 10 163 0.74 4.0×4.0×1.8 CDRH2D11/HP 10 447 0.52 3.2×3.2×1.2 CDRH3D16/HP 10 230 0.84 4.0×4.0×1.8 TDK Sumida Table 3. Recommended Inductors for Both-On Mode L (µH) DCR Typ (mΩ) Isat (A) SIZE (L×W×H mm) VLCF4018T-100MR74-2 10 163 0.74 4.0X4.0X1.8 VLF4012AT-100MR79 10 300 0.85 3.5X3.7X1.2 CDRH3D16/HP 10 230 0.84 4.0X4.0X1.8 CDRH4D11/HP 10 340 0.85 4.8X4.8X1.2 TDK Sumida INPUT AND OUTPUT CAPACITOR SELECTION The output capacitor is mainly selected to minimize the output ripple from the converter. This ripple voltage is the sum of the ripple caused by the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming fixed frequency PWM operation and a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by C out Viout Vin Iout V iout Fs V ripple (12) Vripple = Peak to peak output ripple. For Vin = 3.6 V, Vout = 20 V, and Fs = 1.2 MHz, 0.1% ripple (20 mV) would require 4.7 µ capacitor. For this value, ceramic capacitors are the best choice for its size, cost and availability. The additional output ripple component caused by ESR is calculated using: V(ripple_ESR) = Iout× R(ESR) V(ripple_ESR) can be neglected for ceramic capacitors due to their low ESR, but must be considered if tantalum or electrolytic capacitors are used. Submit Documentation Feedback 17 TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 During a load transient, the capacitor at the output of the boost converter has to supply or absorb additional current before the inductor current ramps up the steady state value. Larger capacitors always help to reduce the voltage over and under shoot during a load transient. A larger capacitor also helps improve loop stability. When the OLED output is enabled, a load transient disturbs the output of the boost converter when the WLED output is enabled or disabled. Although the LDOs PSRR (power supply rejection ratio) reduces the disturbance propagated to the Vout, additional capacitance may be needed if a high precision OLED voltage is required. For its stability, the LDO requires a minimum output capacitance (C3 in the block diagram) of 1 µF. Additional capacitance improves the LDO’s PSRR for low frequency noises. Care must be taken when evaluating a ceramic capacitors derating due to applied dc voltage, aging and over frequency. For example, larger form factor capacitors (in 1206 size) have their self resonant frequencies in the range of the TPS61140/1’s switching frequency. So the effective capacitance is significantly lower. Therefore, it may be necessary to use small capacitors in parallel instead of one large capacitor. 18 Submit Documentation Feedback TPS61140 TPS61141 www.ti.com SLVS624A – JANUARY 2006 – REVISED FEBRUARY 2006 The popular vendors for high value ceramic capacitors are: TDK (http://www.component.tdk.com/components.php) Murata (http://www.murata.com/cap/index.html) Table 4. Recommended Input and Output Capacitors Capacitance (µF) Voltage (V) Case C3216X5R1E475K 4.7 25 1206 C2012X5R1E105K 1 25 805 C1005X5R0J105K 1 6.3 402 GRM319R61E475KA12D 4.7 25 1206 GRM216R61E105KA12D 1 25 805 GRM155R60J105KE19D 1 6.3 402 TDK Murata LAYOUT CONSIDERATION As for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step. If layout is not carefully done, the regulator could show instability as well as EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor needs not only to be close to the Vin pin, but also to the GND pin in order to reduce the input ripple seen by the IC. The Vin and SW pins are conveniently located on the edges of the IC, therefore the inductor can be placed close to the IC. The output capacitor needs to be placed near the load to minimize ripple and maximize transient performance. It is also beneficial to have the ground of the output capacitor close to the GND pin since there will be large ground return current flowing between them. When laying out signal ground, it is recommended to use short traces separated from power ground traces, and connect them together at a single point. Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 14-Mar-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS61140DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61140DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61140DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61140DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61141DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61141DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61141DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61141DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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