TAS5622A www.ti.com SLAS845 – MAY 2012 125-W Stereo / 250-W Stereo PurePath™ HD Digital-Input Class-D Power Stage Check for Samples: TAS5622A FEATURES DESCRIPTION • PurePath™ HD Integrated Feedback Provides: – 0.025% THD at 1 W into 4 Ω – >65 dB PSRR (No Input Signal) – >105 dB (A weighted) SNR • Pre-Clipping Output for Control of a Class-G Power Supply • Reduced Heat Sink Size due to use of 40mΩ Output MOSFET with >90% Efficiency at Full Output Power • Output Power at 10%THD+N – 125 W / 4 Ω BTL Stereo Configuration – 250 W / 2 Ω PBTL Mono Configuration • Output Power at 1%THD+N – 105 W / 4 Ω BTL Stereo Configuration – 210 W / 2 Ω PBTL Mono Configuration • Click and Pop Free Startup • Error Reporting Self-protected Design with UVP, Over Temperature, and Short Circuit Protection • EMI Compliant when used with Recommended System Design • 44-Pin HTSSOP (DDV) Package for Reduced Board Size The TAS5622A is a thermally-enhanced version of the class-D power amplifier based on the TAS5612A using large MOSFETs for improved power efficiency and a novel gate drive scheme for reduced losses in idle and at low output signals leading to reduced heat sink size. 1 234 The unique pre clipping output signal can be used to control a Class-G power supply. This combined with the low idle loss and high power efficiency of the TAS5622A leads to industry leading levels of efficiency ensuring a super “green” system. The TAS5622A uses constant voltage gain. The internally matched gain resistors ensure a high Power Supply Rejection Ratio giving an output voltage only dependent on the audio input voltage and free from any power supply artifacts. The high integration of the TAS5622A makes the amplifier easy to use; and, using TI’s reference schematics and PCB layouts leads to fast design in time. The TAS5622A is available in the space saving surface mount 44-pin HTSSOP package. PowerPAD™ PurePath™ HD PurePath HDTM TAS 5630 TAS5622A TASxxxx DIGITAL AUDIO INPUT Digital Audio Processor APPLICATIONS +12V • • • • Blu-ray™/DVD Receivers High Power Sound Bars Powered Subwoofer and Active Speakers Mini Combo Systems 18V-32.5V PurePath HDTM Class G Power Supply Ref design +3.3V REG. 105VAC → 240VAC 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD, PurePath are trademarks of Texas Instruments. Blu-ray is a trademark of Blu-ray Disk Association (BDA). All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TAS5622A SLAS845 – MAY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. GENERAL INFORMATION Terminal Assignment The TAS5622A is available in a thermally enhanced package: • 44-Pin HTSSOP package (DDV) The package contains a PowerPAD™ that is located on the top side of the device for convenient thermal coupling to the heat sink. 44 PIN DDV PACKAGE (TOP VIEW) GVDD_AB VDD OC_ADJ RESET INPUT_A INPUT_B C_START DVDD GND BST_A BST_B GND GND OUT_A OUT_A PVDD_AB PVDD_AB PVDD_AB OUT_B GND GND GND AVDD INPUT_C INPUT_D FAULT OTW CLIP M1 GND GND OUT_C PVDD_CD PVDD_CD PVDD_CD OUT_D OUT_D GND GND BST_C BST_D M2 M3 GVDD_CD 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A TAS5622A www.ti.com SLAS845 – MAY 2012 PIN FUNCTIONS PINOUT DDV-44 I/O/P (1) AVDD 13 P Internal voltage regulator, analog section BST_A 44 P Bootstrap pin, A-side BST_B 43 P Bootstrap pin, B-side BST_C 24 P Bootstrap pin, C-side BST_D 23 P Bootstrap pin, D-side CLIP 18 O Clipping warning; open drain; active low C_START 7 O Startup ramp PIN NAME DESCRIPTION DVDD 8 P Internal voltage regulator, digital section FAULT 16 O Shutdown signal, open drain; active low 9, 10, 11, 12, 25, 26, 33, 34, 41, 42 P Ground GVDD_AB 1 P Gate-drive voltage supply; AB-side GVDD_CD 22 P Gate-drive voltage supply; CD-side INPUT_A 5 I PWM Input signal for half-bridge A INPUT_B 6 I PWM Input signal for half-bridge B INPUT_C 14 I PWM Input signal for half-bridge C INPUT_D 15 I PWM Input signal for half-bridge D M1 19 I Mode selection 1 (LSB) M2 20 I Mode selection 2 M3 21 I Mode selection 3 (MSB) OC_ADJ 3 O Over-Current threshold programming pin OTW 17 O Over-temperature warning; open drain; active low OUT_A 39, 40 O Output, half-bridge A OUT_B 35 O Output, half-bridge B OUT_C 32 O Output, half-bridge C OUT_D 27, 28 O Output, half-bridge D PVDD_AB 36, 37, 38 P PVDD supply for half-bridge A and B PVDD_CD GND 29, 30, 31 P PVDD supply for half-bridge C and D RESET 4 I Device reset Input; active low VDD 2 P Input power supply P Ground, connect to grounded heat sink TM PowerPAD (1) I = Input, O = Output, P = Power Table 1. ORDERING INFORMATION (1) TA 0°C–70°C (1) PACKAGE TAS5622ADDV TAS5622ADDVR DESCRIPTION 44 pin HTSSOP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A 3 TAS5622A SLAS845 – MAY 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TAS5622A UNIT –0.3 to 13.2 V –0.3 to 50 V BST_X to GND (3) (4) –0.3 to 62.5 V DVDD to GND –0.3 to 4.2 V AVDD to GND –0.3 to 8.5 V OC_ADJ, M1, M2, M3, C_START, INPUT_X to GND –0.3 to 4.2 V RESET, FAULT, OTW, CLIP, to GND –0.3 to 4.2 V VDD to GND, GVDD_X (2) to GND PVDD_X (2) to GND (3), OUT_X to GND (3), BST_X to GVDD_X (2) (3) Maximum continuous sink current (FAULT, OTW, CLIP) Maximum operating junction temperature range, TJ Storage temperature, Tstg Lead temperature Human body model (4) (all pins) Electrostatic discharge (1) (2) (3) (4) Charged device model (4) (all pins) 9 mA 0 to 150 °C –40 to 150 °C 260 °C ±2 kV ±500 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. GVDD_X and PVDD_X represents a full bridge gate drive or power supply. GVDD_X is GVDD_AB or GVDD_CD, PVDD_X is PVDD_AB or PVDD_CD These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions. Maximum BST_X to GND voltage is the sum of maximum PVDD to GND and GVDD to GND voltages minus a diode drop. THERMAL INFORMATION THERMAL METRIC (1) TAS5622A DDV (44 PIN) θJH Junction-to-heat sink thermal resistance (2) 1.9 θJCtop Junction-to-case (top) thermal resistance 0.6 θJB Junction-to-board thermal resistance 1.7 ψJT Junction-to-top characterization parameter 0.6 ψJB Junction-to-board characterization parameter 1.7 θJCbot Junction-to-case (bottom) thermal resistance n/a (1) (2) 4 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Thermal data are obtained with 85°C heat sink temperature using thermal compound with 0.7W/mK thermal conductivity and 2mil thickness. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A TAS5622A www.ti.com SLAS845 – MAY 2012 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT PVDD_X Full-bridge supply DC supply voltage 12 32.5 34 V GVDD_X Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V 2.5 4.0 1.5 3.0 1.5 2.0 BTL RL Load impedance Output filter: L = 10 uH, 1 µF. Output AD modulation, switching frequency > 350 kHz. SE PBTL Minimum inductance at overcurrent limit, including inductor tolerance, temperature and possible inductor saturation Ω μH LOUTPUT Output filter inductance 5 FPWM PWM frame rate 352 384 CPVDD PVDD close decoupling capacitors 0.44 1 μF 100 nF BTL and PBTL configuration C_START Startup ramp capacitor ROC Over-current programming resistor Resistor tolerance = 5% 24 ROC_LATCHED Over-current programming resistor Resistor tolerance = 5% 47 TJ Junction temperature SE and 1xBTL+2xSE configuration 500 μF 1 62 0 kHz 33 kΩ 68 kΩ 125 °C MODE SELECTION PINS MODE PINS PWM Input (1) Output Configuration Input A 0 2N + 1 2 x BTL 1 1N + 1 (2) 2 x BTL 2N + 1 2 x BTL 1N + 1 (2) 1 x BTL + 2 x SE M3 M2 M1 0 0 0 0 0 1 0 0 1 1 1 0 0 2N + 1 (1) (2) (3) 1N + 1 (2) Input B Input C Input D MODE PWMa PWMb PWMa Unused PWMc PWMd AD Mode PWMc Unused AD Mode PWMa PWMa PWMb PWMc PWMd BD Mode Unused PWMc PWMd 1 x PBTL PWMa AD Mode PWMb 0 0 AD Mode 1 0 0 1 x PBTL PWMa Unused 0 1 AD Mode 1 0 0 2N + 1 1 x PBTL PWMa PWMb 1 0 BD Mode 1 0 1 1N + 1 4 x SE (3) PWMa PWMb PWMc PWMd AD Mode The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode. Using 1N interface in BTL and PBTL mode results in increased DC offset on the output terminals. The 4xSE mode can be used as 1xBTL + 2xSE configuration by feeding a 2N PWM signal to either INPUT_AB or INPUT_CD for improved DC offset accuracy Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A 5 TAS5622A SLAS845 – MAY 2012 www.ti.com TYPICAL SYSTEM BLOCK DIAGRAM Capacitors for External Filtering & Startup/Stop System microcontroller /AMP RESET C_START /CLIP *NOTE1 /OTW TASxxxx PWM Modulator /FAULT I2C /RESET VALID BST_A BST_B LeftChannel Output PWM_A INPUT_A PWM_B INPUT_B OUT_A Input H-Bridge 1 Output H-Bridge 1 OUT_B Bootstrap Capacitors nd 2 Order L-C Output Filter for each H-Bridge 2-CHANNEL H-BRIDGE BTL MODE nd PWM_C INPUT_C PWM_D INPUT_D PVDD 32.5V Output H-Bridge 2 OUT_D PVDD GVDD, VDD, & VREG Power Supply Decoupling OC_ADJ DVDD AVDD VDD M3 2 Order L-C Output Filter for each H-Bridge BST_C GND M2 GVDD_AB, CD M1 Power Supply Decoupling SYSTEM Power Supplies BST_D Bootstrap Capacitors Hardwire OverCurrent Limit GND GND 12V Input H-Bridge 2 GND Hardwire Mode Control OUT_C PVDD_AB, CD RightChannel Output GVDD (12V)/VDD (12V) VAC (1) Logic AND is inside or outside the micro processor. 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A TAS5622A www.ti.com SLAS845 – MAY 2012 FUNCTIONAL BLOCK DIAGRAM /CLIP /OTW /FAULT BST_X GVDD_X AVDD DVDD UVP /RESET PROTECTION & I/O LOGIC MODE1-3 AVDD AVDD VDD DVDD DVDD POWER-UP RESET TEMP SENSE CB3C OVERLOAD PROTECTION STARTUP CONTROL C_START BST_A PVDD_AB INPUT_A PWM RECEIVER ANALOG LOOP FILTER + - PWM & TIMING CONTROL GATE-DRIVE OUT_A GND GVDD_AB BST_B PVDD_AB INPUT_B PWM RECEIVER ANALOG LOOP FILTER + - PWM & TIMING CONTROL GATE-DRIVE OUT_B GND BST_C PVDD_CD INPUT_C PWM RECEIVER ANALOG LOOP FILTER + - PWM & TIMING CONTROL GATE-DRIVE OUT_C GND GVDD_CD BST_D PVDD_CD INPUT_D PWM RECEIVER ANALOG LOOP FILTER + - PWM & TIMING CONTROL GATE-DRIVE OUT_D GND Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A 7 TAS5622A SLAS845 – MAY 2012 www.ti.com AUDIO SPECIFICATION STEREO (BTL) Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and a TAS5622A power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 32.5V, GVDD_X = 12V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C,Output Filter: LDEM = 10 μH, CDEM = 1 µF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX RL = 3 Ω, 10% THD+N 150 RL = 4 Ω, 10% THD+N 125 RL = 3 Ω, 1% THD+N 140 UNIT PO Power output per channel THD+N Total harmonic distortion + noise 1 W, 1 kHz signal Vn Output integrated noise A-weighted, AES17 measuring filter VOS Output offset voltage No signal SNR Signal-to-noise ratio (1) A-weighted, AES17 measuring filter 105 dB DNR Dynamic range A-weighted, –60 dBFS (rel 1% THD+N) 105 dB Pidle Power dissipation due to Idle losses (IPVDD_X) PO = 0, channels switching (2) 0.8 W RL = 4 Ω, 1% THD+N (1) (2) W 105 0.025 % 180 μV 10 20 mV SNR is calculated relative to 1% THD-N output level. Actual system idle losses also are affected by core losses of output inductors. AUDIO SPECIFICATION 4 CHANNELS (SE) Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and a TAS5622A power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 32.5V, GVDD_X = 12V, RL = 4Ω, fS = 384 kHz, ROC = 24kΩ, TC = 75°C,Output Filter: LDEM = 10μH, CDEM = 1 µF, CDCB = 470µF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX RL = 3 Ω, 10% THD+N 43 RL = 3 Ω, 1% THD+N 35 UNIT PO Power output per channel THD+N Total harmonic distortion + noise 1 W, 1 kHz signal 0.025 % Vn Output integrated noise A-weighted, AES17 measuring filter 180 μV SNR Signal-to-noise ratio (1) A-weighted, AES17 measuring filter 102 dB DNR Dynamic range A-weighted, –60 dBFS (rel 1% THD+N) 102 dB Pidle Power dissipation due to Idle losses (IPVDD_X) 0.8 W (1) (2) 8 PO = 0, channels switching (2) W SNR is calculated relative to 1% THD-N output level. Actual system idle losses also are affected by core losses of output inductors. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A TAS5622A www.ti.com SLAS845 – MAY 2012 AUDIO SPECIFICATION MONO (PBTL) Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and a TAS5622A power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 32.5V, GVDD_X = 12V, RL = 4Ω, fS = 384kHz, ROC = 24kΩ, TC = 75°C, Output Filter: LDEM = 10μH, CDEM = 1μF, unless otherwise noted. PARAMETER PO TEST CONDITIONS Power output per channel MIN TYP MAX RL = 1.5 Ω, 10%, THD+N 330 RL = 2 Ω, 10% THD+N 250 RL = 4 Ω, 10% THD+N 130 RL = 1.5 Ω, 1% THD+N 270 RL = 2 Ω, 1% THD+N 210 RL = 4 Ω, 1% THD+N 105 UNIT W THD+N Total harmonic distortion + noise 1 W, 1 kHz signal Vn Output integrated noise A-weighted, AES17 measuring filter VOS Output offset voltage No signal SNR Signal to noise ratio (1) A-weighted, AES17 measuring filter 105 dB DNR Dynamic range A-weighted, –60 dBFS (rel 1% THD) 105 dB Pidle Power dissipation due to idle losses (IPVDD_X) 0.8 W (1) (2) 0.025 % 180 μV 10 PO = 0, All channels switching (2) 20 mV SNR is calculated relative to 1% THD-N output level. Actual system idle losses are affected by core losses of output inductors. ELECTRICAL CHARACTERISTICS PVDD_X = 32.5V, GVDD_X = 12V, VDD = 12V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX 3.0 3.3 3.6 UNIT INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION DVDD Voltage regulator, only used as a reference node VDD = 12 V AVDD Voltage regulator, only used as a reference node VDD = 12 V 7.8 IVDD VDD supply current Operating, 50% duty cycle 20 Idle, reset mode 20 IGVDD_X Gate-supply current per full-bridge 50% duty cycle 12 IPVDD_X Full-bridge idle current Reset mode V mA mA 3 50% duty cycle without load 12 RESET low 1.7 VDD and GVDD_X at 0V V mA 0.35 OUTPUT-STAGE MOSFETs RDS(on), LS Drain-to-source resistance, low side (LS) RDS(on), HS Drain-to-source resistance, high side (HS) TJ = 25°C, excludes metallization resistance, GVDD = 12 V 40 mΩ 40 mΩ 8.5 V 0.7 V 8.5 V 0.7 V 8.5 V I/O PROTECTION Vuvp,GVDD Vuvp,GVDD, hyst (1) Vuvp,VDD Vuvp,VDD, hyst (1) Vuvp,PVDD Vuvp,PVDD,hyst (1) OTW (1) OTWhyst OTE (1) (1) Undervoltage protection limit, GVDD_X Undervoltage protection limit, VDD Undervoltage protection limit, PVDD_X Overtemperature warning (1) 0.7 115 Temperature drop needed below OTW temperature for OTW to be inactive after OTW event. Overtemperature error 125 V 135 25 145 155 °C °C 165 °C Specified by design. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A 9 TAS5622A SLAS845 – MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) PVDD_X = 32.5V, GVDD_X = 12V, VDD = 12V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified. PARAMETER OTE-OTWdifferential (1) OTEHYST (1) OLPC TEST CONDITIONS MIN TYP MAX UNIT OTE-OTW differential 30 °C A device reset is needed to clear FAULT after an OTE event 25 °C Overload protection counter fPWM = 384 kHz 2.6 ms IOC Overcurrent limit protection Resistor – programmable, nominal peak current in 1Ω load, ROC = 24 kΩ 15 A IOC_LATCHED Overcurrent limit protection, latched Resistor – programmable, nominal peak current in 1Ω load, ROC = 62 kΩ 15 A IOCT Overcurrent response time Time from application of short condition to Hi-Z of affected half bridge 150 ns IPD Internal pulldown resistor at output of each half bridge Connected when RESET is active to provide bootstrap charge. Not used in SE mode. 3 mA STATIC DIGITAL SPECIFICATIONS VIH High level input voltage VIL Low level input voltage LEAKAGE Input leakage current INPUT_X, M1, M2, M3, RESET 1.9 V 0.8 V 100 μA 33 kΩ OTW / SHUTDOWN (FAULT) RINT_PU Internal pullup resistance, OTW, CLIP, FAULT to DVDD VOH High level output voltage Internal pullup resistor VOL Low level output voltage IO = 4mA FANOUT Device fanout OTW, FAULT, CLIP No external pullup 10 20 Submit Documentation Feedback 3 26 3.3 3.6 V 200 500 mV 30 devices Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A TAS5622A www.ti.com SLAS845 – MAY 2012 TYPICAL CHARACTERISTICS, BTL CONFIGURATION Measurement conditions are: 1kHz, PVDD_X = 32.5V, GVDD_X = 12V, RL = 4Ω, fS = 384 kHz, ROC = 24kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20Hz to 20kHz BW (AES17 low pass filter), unless otherwise noted. OUTPUT POWER vs SUPPLY VOLTAGE vs DISTORTION + NOISE = 10% TOTAL HARMONIC+NOISE vs OUTPUT POWER, 1kHz 220 3Ω 4Ω 8Ω 3Ω 4Ω 8Ω 200 180 160 1 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 0.1 140 120 100 80 60 40 0.01 TC = 75°C THD+N at 10% 20 TC = 75°C 0.005 0.02 0.1 1 10 0 100 200 PO − Output Power − W 15 20 25 PVDD − Supply Voltage − V 35 G001 G003 Figure 2. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY, 4Ω OUTPUT POWER vs SUPPLY VOLTAGE, vs DISTORTION + NOISE = 1% 180 1W 10 W 80 W 3Ω 4Ω 8Ω 160 140 PO − Output Power − W 1 0.1 0.01 120 100 80 60 40 20 TC = 75°C 0.001 30 Figure 1. 10 THD+N − Total Harmonic Distortion + Noise − % 10 20 100 1k Frequency − Hz 10k TC = 75°C 20k 0 10 15 20 25 PVDD − Supply Voltage − V 30 G002 Figure 3. 35 G004 Figure 4. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A 11 TAS5622A SLAS845 – MAY 2012 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) Measurement conditions are: 1kHz, PVDD_X = 32.5V, GVDD_X = 12V, RL = 4Ω, fS = 384 kHz, ROC = 24kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20Hz to 20kHz BW (AES17 low pass filter), unless otherwise noted. 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 SYSTEM POWER LOSS vs OUTPUT POWER 45 3Ω 4Ω 8Ω 40 35 30 Power Loss − W Efficiency − % SYSTEM EFFICIENCY vs OUTPUT POWER 25 20 15 10 3Ω 4Ω 8Ω 5 TC = 75°C TC = 75°C 0 0 100 200 300 Total Output Power − W 400 0 100 200 300 Total Output Power − W G006 G005 Figure 5. Figure 6. OUTPUT POWER vs TEMPERATURE NOISE AMPLITUDE vs FREQUENCY 200 180 140 Noise Amplitude − dB PO − Output Power − W 160 120 100 80 60 40 3Ω 4Ω 8Ω 20 0 −10 0 10 THD+N at 10% 20 30 40 50 60 70 80 TC − Case Temperature − °C 90 100 110 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 −170 −180 −190 −200 TC = 75°C VREF = 20.5 V Sample Rate = 48kHz FFT Size = 16384 0 2k 4k 6k 4Ω 8k 10k 12k 14k 16k 18k 20k 22k 24k f − Frequency − Hz G007 Figure 7. 12 400 G008 Figure 8. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A TAS5622A www.ti.com SLAS845 – MAY 2012 TYPICAL CHARACTERISTICS, SE CONFIGURATION Measurement conditions are: 1kHz, PVDD_X = 32.5V, GVDD_X = 12V, RL = 4Ω, fS = 384kHz, ROC = 24kΩ, TC = 75°C, Output Filter: LDEM = 10μH, CDEM = 1µF, CDCB = 470µF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise noted. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 80 2Ω 3Ω 4Ω 2Ω 3Ω 4Ω 60 1 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 0.1 40 20 TC = 75°C THD+N at 10% 0.01 TC = 75°C 0.005 0.02 0.1 1 10 0 100 PO − Output Power − W 10 15 20 25 PVDD − Supply Voltage − V 30 35 G009 G010 Figure 9. Figure 10. TYPICAL CHARACTERISTICS, PBTL CONFIGURATION Measurement conditions are: 1 kHz, PVDD_X = 32.5V, GVDD_X = 12V, RL = 4 Ω, fS = 384kHz, ROC = 24kΩ, TC = 75°C, Output Filter: LDEM = 10μH, CDEM = 1µF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise noted. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 340 2Ω 3Ω 4Ω 2Ω 3Ω 4Ω 320 300 280 260 1 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 0.1 240 220 200 180 160 140 120 100 80 60 40 0.01 0.005 0.02 0.1 1 10 PO − Output Power − W 100 TC = 75°C THD+N at 10% 20 TC = 75°C 400 0 10 15 20 25 PVDD − Supply Voltage − V 30 G011 Figure 11. 35 G012 Figure 12. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A 13 TAS5622A SLAS845 – MAY 2012 www.ti.com THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5622A needs only a 12V supply in addition to the (typical) 32.5 V powerstage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge. To provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_X) and each full-bridge has separate power stage supply (PVDD_X) and gate supply (GVDD_X) pins. Although supplied from the same 12 V source, it is highly recommended to separate GVDD_AB, GVDD_CD, and VDD on the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided. (See reference board documentation for additional information.) Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X connection is decoupled with minimum 2x 220 nF ceramic capacitors placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the TAS5622A reference design. For additional information on recommended power supply and required components, see the application diagrams in this data sheet. The 12V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 32.5 V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5622A is fully protected against erroneous power-stage turn on due to parasitic gate charging when power supplies are applied. Thus, voltagesupply ramp rates (dV/dt) are non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet). Boot Strap Supply For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 300kHz to 400 kHz, it is recommended to use 33 nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle. SYSTEM POWER-UP/POWER-DOWN SEQUENCE Powering Up The TAS5622A does not require a power-up sequence. The outputs of the H-bridges remain in a highimpedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. Powering Down The TAS5622A does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks. 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A TAS5622A www.ti.com SLAS845 – MAY 2012 STARTUP AND SHUTDOWN RAMP SEQUENCE The integrated startup and stop sequence ensures a click and pop free startup and shutdown sequence of the amplifier. The startup sequence uses a voltage ramp with a duration set by the CSTART capacitor. The sequence uses the input PWM signals to generate output PWM signals, hence input idle PWM should be present during both startup and shut down ramping sequences. VDD, GVDD_X and PVDD_X power supplies must be turned on and with settled outputs before starting the startup ramp by setting RESET high. During startup and shutdown ramp the input PWM signals should be in muted condition with the PWM processor noise shaper activity turned off (50% duty cycle). The duration of the startup and shutdown ramp is 100 ms + X ms, where X is the CSTART capacitor value in nF. It is recommended to use 100nF CSTART in BTL and PBTL mode and 1 µF in SE mode configuration. This results in ramp times of 200 ms and 1.1s respectively. The longer ramp time in SE configuration allows charge and discharge of the output AC coupling capacitor without audible artifacts. STARTUP/SHUTDOWN RAMP Ramp Start Ramp Start Ramp End Ramp End 3.3V /RESET 0V INPUT_X OUT_X INPUT_X IS SWITCHING (MUTE) NOISE SHAPER OFF (UNMUTED) INPUT_X IS SWITCHING (MUTE) NOISE SHAPER OFF OUT_X IS SWITCHING (MUTE) (UNMUTED) OUT_X IS SWITCHING (MUTE) 3.3V Hi-Z 0V PVDD_X Hi-Z 0V VI_CM DC_RAMP 0V 50% PVDD_X/2 0V tStartup Ramp tStartup Ramp INPUT_X IS SWITCHING (MUTE) NOISE SHAPER ON UNUSED OUTPUT CHANNELS If all available output channels are not used, it is recommended to disable switching of unused output nodes to reduce power consumption. Furthermore by disabling unused output channels the cost of unused output LC demodulation filters can be avoided. Disabling a channel is done by leave the bootstrap capacitor (BST) unstuffed and connecting the respective input to GND. The unused output pin(s) can be left floating. Please note that the PVDD decoupling capacitors still need to be mounted. Table 2. Unused Output Channels Operating Mode PWM Input 000 2N + 1 001 1N + 1 010 2N + 1 101 1N + 1 Output Configuration Unused Channel INPUT_A INPUT_B INPUT_C INPUT_D Unstuffed Component 2 x BTL AB CD GND PWMa GND PWMb PWMc GND PWMd GND BST_A & BST_B capacitor BST_C & BST_D capacitor A GND PWMb PWMc PWMd BST_A capacitor B PWMa GND PWMc PWMd BST_B capacitor C PWMa PWMb GND PWMd BST_C capacitor D PWMa PWMb PWMc GND BST_D capacitor 4 x SE Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A 15 TAS5622A SLAS845 – MAY 2012 www.ti.com DEVICE PROTECTION SYSTEM The TAS5622A contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. The TAS5622A responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been removed, i.e., the supply voltage has increased. The device will function on errors, as shown in the following table. Table 3. Device Protection BTL Mode PBTL Mode SE Mode Channel Fault Turns Off Channel Fault Turns Off Channel Fault Turns Off A A+B A A+B+C+D A A+B B C C+D D B B C C D D C+D Bootstrap UVP does not shutdown according to the table, it shuts down the respective high-side FET. spacer PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC) The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is shorted to GND or PVDD_X. For comparison, the OC protection system detects an over current after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at startup i.e. when VDD is supplied, consequently a short to either GND or PVDD_X after system startup will not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half bridges are kept in a Hi-Z state until the short is removed, the device then continues the startup sequence and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that there are no shorts from OUT_X to GND, the second step tests that there are no shorts from OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is <15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the device will not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and FAULT is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection system it is recommended not to insert resistive load to GND or PVDD_X. OVERTEMPERATURE PROTECTION The TAS5622A has a two-level temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125°C (typical). If the device junction temperature exceeds 155°C (typical) the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the highimpedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation. OVERTEMPERATURE WARNING, OTW The over temperature warning OTW asserts when the junction temperature has exceeded recommended operating temperature. Operation at junction temperatures above OTW threshold is exceeding recommended operation conditions and is strongly advised to avoid. If OTW asserts, action should be taken to reduce power dissipation to allow junction temperature to decrease until it gets below the OTW hysteresis threshold. This action can be decreasing audio volume or turning on a system cooling fan. 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A TAS5622A www.ti.com SLAS845 – MAY 2012 UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR) The UVP and POR circuits of the TAS5622A fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold. ERROR REPORTING Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI recommends monitoring the OTW signal using the system micro controller and responding to an overtemperature warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown (OTE). To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT, CLIP, and OTW outputs. See ELECTRICAL CHARACTERISTICS TABLE for actual values. The FAULT, OTW, pins are active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. Any fault resulting in device shutdown is signaled by the FAULT pin going low. Likewise, OTW goes low when the device junction temperature exceeds 125°C (see the following table). Table 4. Error Reporting FAULT OTW 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) DESCRIPTION 0 1 Overload (OLP) or undervoltage (UVP) 1 0 Junction temperature higher than 125°C (overtemperature warning) 1 1 Junction temperature lower than 125°C and no OLP or UVP faults (normal operation) FAULT HANDLING If a fault situation occurs while in operation, the device will act accordingly to the fault being a global or a channel fault. A global fault is a chip-wide fault situation and will cause all PWM activity of the device to be shut down, and will assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires resetting the device by toggling RESET. Toggling RESET should never be allowed with excessive system temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET (RESET high) if the OTW signal is cleared (high). A channel fault will result in shutdown of the PWM activity of the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI recommends monitoring the OTW signal using the system micro controller and responding to an over temperature warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown (OTE). Table 5. Fault Handling Fault/Event Description Global or Channel Reporting Method Latched/Self Clearing Action needed to Clear Output FETs Voltage Fault Global FAULT Pin Self Clearing Increase affected supply voltage Hi-Z POR (DVDD UVP) Power On Reset Global FAULT Pin Self Clearing Allow DVDD to rise H-Z BST UVP Voltage Fault Channel (half bridge) None Self Clearing Allow BST cap to recharge (lowside on, VDD 12V) HighSide Off OTW Thermal Warning Global OTW Pin Self Clearing Cool below lower OTW threshold Normal operation Fault/Event PVDD_X UVP VDD UVP GVDD_X UVP AVDD UVP Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A 17 TAS5622A SLAS845 – MAY 2012 www.ti.com Table 5. Fault Handling (continued) Fault/Event Fault/Event Description Global or Channel Reporting Method Latched/Self Clearing Action needed to Clear Output FETs OTE (OTSD) Thermal Shutdown Global FAULT Pin Latched Toggle RESET Hi-Z OLP (CBC >2.6ms) OC shutdown Channel FAULT Pin Latched Toggle RESET Hi-Z Latched OC (ROC >47k) OC shutdown Channel FAULT Pin Latched Toggle RESET Hi-Z Flip state, cycle by cycle at fs/2 CBC (24k<ROC<33k) OC Limiting Channel None Self Clearing reduce signal level or remove short Stuck at Fault (1) (1 to 3 channels) No PWM Channel None Self Clearing resume PWM Hi-Z Stuck at Fault (1) (All channels) No PWM Global None Self Clearing resume PWM Hi-Z (1) Stuck at Fault occurs when input PWM drops below minimum PWM frame rate given in RECOMENDED OPERATING CONDITIONS DEVICE RESET When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance (Hi-Z) state. In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the FAULT output, i.e., FAULT is forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure thermal reliability, the rising edge of RESET must occur no sooner than 4 ms after the falling edge of FAULT. SYSTEM DESIGN CONSIDERATION A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching. Apply audio only according to the timing information for startup and shutdown sequence. That will start and stop the amplifier without audible artifacts in the output transducers. The CLIP signal indicates that the output is approaching clipping (when output PWM starts skipping pulses due to loop filter saturation). The signal can be used to initiate an audio volume decrease or to adjust the power supply rail. The device inverts the audio signal from input to output. The DVDD and AVDD pins are not recommended to be used as a voltage source for external circuitry. 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A TAS5622A www.ti.com SLAS845 – MAY 2012 APPLICATION INFORMATION PCB MATERIAL RECOMMENDATION FR-4 Glass Epoxy material with 1 oz. (35 μm) is recommended for use with the TAS5622A. The use of this material can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB trace inductance. PVDD CAPACITOR RECOMMENDATION The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These capacitors should be selected for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well designed system power supply, 1000 μF, 50 V should support most applications. The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed switching. DECOUPLING CAPACITOR RECOMMENDATION To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio performance, good quality decoupling capacitors should be used. In practice, X5R or better should be used in this application. The voltage of the decoupling capacitors should be selected in accordance with good design practices. Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the selection of the close decoupling capacitor that is placed on the power supply to each half-bridge. It must withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple current created by high power output. A minimum voltage rating of 50V is required for use with a 32.5 V power supply. See the TAS5624ADDVEVM User's Guide for more details including layout and Bill-of-Materials. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A 19 20 13 AVDD 12 GND 11 GND Submit Documentation Feedback Product Folder Link(s): TAS5622A PVDD_CD 29 17 /OTW /OTW GND 26 GND 25 BST_C 24 BST_D 23 19 M1 20 M2 21 M3 22 GVDD_CD OUT_D 27 OUT_D 28 PVDD_CD 30 15 INPUT_D 16 /FAULT 100 nF 10 µH 470 nF 100 nF 100 nF 1nF 1 nF 10nF 10nF 3R3 3R3 10nF 33nF 33nF 10 µH 470 nF 10 µH 100 nF 1nF 10nF 3R3 3R3 GND 470 uF 470 uF 100 nF 1nF GND 33 OUT_C 32 /FAULT 18 /CLIP 220 nF 220 nF 220 nF 220 nF 10 µH PVDD PWM_D /CLIP 33nF 33nF GND 34 OUT_B 35 PVDD_AB 36 PVDD_CD 31 3.3R 9 GND 10 GND PVDD_AB 37 PVDD_AB 38 OUT_A 39 OUT_A 40 GND 41 GND 42 BST_B 43 BST_A 44 14 INPUT_C 1uF 1uF 8 DVDD TAS5622A PWM_C 100 nF 6 INPUT_B PWM_B 7 C_START 5 INPUT_A 3 OC A _ DJ 2 VDD 1 GVDD_AB PWM_A ROC-ADJUST 100 nF 100 nF 4 /RESET 10uF 3.3R /RESET GND +12V TAS5622A SLAS845 – MAY 2012 www.ti.com TYPICAL BTL APPLICATION Figure 13. Typical Differential (2N) BTL Application with AD Modulation Filters Copyright © 2012, Texas Instruments Incorporated 3 .3R 1 uF GND PVDD_CD 29 16 /FAULT /FAULT Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A GND 26 GND 25 BST _C 24 BST _D 23 20 M 2 21 M 3 22 GVDD_ CD OUT_D 27 18 /CLIP /CLIP 19 M 1 OUT_D 28 17 /OTW /OTW 100 nF PVDD_CD 30 15 INPUT_ D PWM_ D PVDD_CD 31 OUT_C 32 GND 33 GND 34 OUT_ B 35 PVDD_AB 36 PVDD_AB 37 PVDD_AB 38 OUT_ A 39 OUT_ A 40 GND 41 GND 42 BST_ B 43 BST_ A 44 14 INPUT_ C 13 AVDD 12 GND 11 GND 10 GND 9 DVDD TAS5622A PWM_C 1 uF C_START 7 8 INPUT_ B 6 PWM _B INPUT_ A 5 /RESET OC_ ADJ VDD 2 3 GVDD_ AB 1 PWM_ A ROC -ADJUST 100 nF 100nF 4 1µF 10uF 3 .3R /RESET GND +12V 33nF 33nF 33nF 220 nF 220nF 220 nF 220nF 33nF 470uF 470uF 10 uH 10 uH 1 0uH 1 0uH 470uF 1nF 1nF 470uF 1nF 1nF * 85°C, Low ESR 1µF 1µF 470uF * 85°C, Low ESR * 85°C, Low ESR 1 µF 1 µF 470 uF * 85°C, Low ESR 10nF 3R3 3R3 10nF 10nF 3R3 3R3 10nF GND PVDD TAS5622A www.ti.com SLAS845 – MAY 2012 TYPICAL SE CONFIGURATION Figure 14. Typical (1N) SE Application Submit Documentation Feedback 21 22 Submit Documentation Feedback Product Folder Link(s): TAS5622A 3.3R GND 26 GND 25 BST_C 24 BST_D 23 20 M2 21 M3 22 GVDD_CD OUT_D 27 18 /CLIP /CLIP 19 M1 OUT_D 28 PVDD_CD 29 /OTW PVDD_CD 30 15 INPUT_D 16 /FAULT PVDD_CD 31 OUT_C 32 33nF 33nF 10 µH 10 µH GND 10 µH GND 33 470 uF 470 uF 10µH PVDD 17 /OTW 100 nF 220 nF 33 nF 220 nF 220 nF 220 nF 33 nF GND 34 OUT_B 35 PVDD_AB 36 PVDD_AB 37 PVDD_AB 38 OUT_A 39 OUT_A 40 GND 41 GND 42 BST_B 43 BST_A 44 14 INPUT_C 13 AVDD 12 GND TAS5622A /FAULT 1uF 11 GND 10 GND GND 8 9 DVDD 7 1uF C_START 6 PWM_B 100nF INPUT_A INPUT_B 4 5 /RESET VDD PWM_A GVDD_AB 1 2 /RESET R OC-ADJUST 100 nF 100 nF OC_ADJ 10uF 3.3R 3 GND +12V 470 nF 100 nF 100 nF 1 nF 1 nF 10nF 3R 3 3R 3 10nF TAS5622A SLAS845 – MAY 2012 www.ti.com TYPICAL PBTL CONFIGURATION Figure 15. Typical Differential (2N) PBTL Application with AD Modulation Filter Copyright © 2012, Texas Instruments Incorporated TAS5622A www.ti.com SLAS845 – MAY 2012 CIRCUIT COMPONENT AND PRINTED CIRCUIT BOARD RECOMMENDATION These requirements must be followed to achieve best performance and reliability and minimum ground bounce at rated output power of TAS5622A. CIRCUIT COMPONENT REQUIREMENTS A number of circuit components are critical to performance and reliability. They include LC filter inductors and capacitors, decoupling capacitors and the heatsink. The best detailed reference for these is the TAS5622A EVM BOM in the User's Guide, which includes components that meet all the following requirements. • High frequency decoupling capacitors: small high frequency decoupling capacitors are placed next to the IC to control switching spikes and keep high frequency currents in a tight loop to achieve best performance and reliability and EMC. They must be high quality ceramic parts with material like X7R or X5R and voltage ratings at least 30% greater than PVDD, to minimize loss of capacitance caused by applied DC voltage. (Capacitors made of materials like Y5V or Z5U should never be used in decoupling circuits or audio circuits because their capacitance falls dramatically with applied DC and AC voltage, often to 20% of rated value or less.) • Bulk decoupling capacitors: large bulk decoupling capacitors are placed as close as possible to the IC to stabilize the power supply at lower frequencies. They must be high quality aluminum parts with low ESR and ESL and voltage ratings at least 25% more than PVDD to handle power supply ripple currents and voltages. • LC filter inductors: to maintain high efficiency, short circuit protection and low distortion, LC filter inductors must be linear to at least the OCP limit and must have low DC resistance and core losses. For SCP, minimum working inductance, including all variations of tolerance, temperature and current level, must be 5µH. Inductance variation of more than 1% over the output current range can cause increased distortion. • LC filter capacitors: to maintain low distortion and reliable operation, LC filter capacitors must be linear to twice the peak output voltage. For reliability, capacitors must be rated to handle the audio current generated in them by the maximum expected audio output voltage at the highest audio frequency. • Heatsink: The heatsink must be fabricated with the PowerPAD™ contact area spaced 1.0mm +/-0.01mm above mounting areas that contact the PCB surface. It must be supported mechanically at each end of the IC. This mounting ensures the correct pressure to provide good mechanical, thermal and electrical contact with TAS5622A PowerPAD™. The PowerPAD™ contact area must be bare and must be interfaced to the PowerPAD™ with a thin layer (about 1mil) of a thermal compound with high thermal conductivity. PRINTED CIRCUIT BOARD REQUIREMENTS PCB layout, audio performance, EMC and reliability are linked closely together, and solid grounding improves results in all these areas. The circuit produces high, fast-switching currents, and care must be taken to control current flow and minimize voltage spikes and ground bounce at IC ground pins. Critical components must be placed for best performance and PCB traces must be sized for the high audio currents that the IC circuit produces. Grounding: ground planes must be used to provide the lowest impedance and inductance for power and audio signal currents between the IC and its decoupling capacitors, LC filters and power supply connection. The area directly under the IC should be treated as central ground area for the device, and all IC grounds must be connected directly to that area. A matrix of vias must be used to connect that area to the ground plane. Ground planes can be interrupted by radial traces (traces pointing away from the IC), but they must never be interrupted by circular traces, which disconnect copper outside the circular trace from copper between it and the IC. Top and bottom areas that do not contain any power or signal traces should be flooded and connected with vias to the ground plane. Decoupling capacitors: high frequency decoupling capacitors must be located within 2mm of the IC and connected directly to PVDD and GND pins with solid traces. Vias must not be used to complete these connections, but several vias must be used at each capacitor location to connect top ground directly to the ground plane. Placement of bulk decoupling capacitors is less critical, but they still must be placed as close as possible to the IC with strong ground return paths. Typically the heatsink sets the distance. LC filters: LC filters must be placed as close as possible to the IC after the decoupling capacitors. The capacitors must have strong ground returns to the IC through top and bottom grounds for effective operation. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A 23 TAS5622A SLAS845 – MAY 2012 www.ti.com PCB copper must be at least 1 ounce thickness. PVDD and output traces must be wide enough to carry expected average currents without excessive temperature rise. PWM input traces must be kept short and close together on the input side of the IC and must be shielded with ground flood to avoid interference from high power switching signals. The heatsink must be grounded well to the PCB near the IC, and a thin layer of highly conductive thermal compound (about 1mil) must be used to connect the heatsink to the PowerPAD™. T5 T1 T2 T3 T4 T5 Note T1: Bottom and top layer ground plane areas are used to provide strong ground connections. The area under the IC must be treated as central ground, with IC grounds connected there and a strong via matrix connecting the area to bottom ground plane. The ground path from the IC to the power supply ground through top and bottom layers must be strong to provide very low impedance to high power and audio currents. Note T2: Low impedance X7R or X5R ceramic high frequency decoupling capacitors must be placed within 2mm of PVDD and GND pins and connected directly to them and to top ground plane to provide good decoupling of high frequency currents for best performance and reliability. Their DC voltage rating must be 2 times PVDD. Note T3: Low impedance electrolytic bulk decoupling capacitors must be placed as close as possible to the IC. Typically the heat sink sets the distance. Wide PVDD traces are routed on the top layer with direct connections to the pins, without going through vias. Note T4: LC filter inductors and capacitors must be placed as close as possible to the IC after decoupling capacitors. Inductors must have low DC resistance and switching losses and must be linear to at least the OCP (over current protection) limit. Capacitors must be linear to at least twice the maximum output voltage and must be capable of conducting currents generated by the maximum expected high frequency output. Note T5: Bulk decoupling capacitors and LC filter capacitors must have strong ground return paths through ground plane to the central ground area under the IC. Note T6: The heat sink must have a good thermal and electrical connection to PCB ground and to the IC PowerPAD™. It must be connected to the PowerPAD™ through a thin layer, about 1 mil, of highly conductive thermal compound. Figure 16. Printed Circuit Board - Top Layer 24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A TAS5622A www.ti.com SLAS845 – MAY 2012 B1 B1 B2 Note B1: A wide PVDD bus and a wide ground path must be used to provide very low impedance to high power and audio currents to the power supply. Top and bottom ground planes must be connected with vias at many points to reinforce the ground connections. Note B2: Wide output traces can be routed on the bottom layer and connected to output pins with strong via arrays. Figure 17. Printed Circuit Board - Bottom Layer Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TAS5622A 25 PACKAGE OPTION ADDENDUM www.ti.com 1-Jun-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TAS5622ADDV ACTIVE HTSSOP DDV 44 35 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5622ADDVR ACTIVE HTSSOP DDV 44 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Jun-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5622ADDVR Package Package Pins Type Drawing SPQ HTSSOP 2000 DDV 44 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Jun-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5622ADDVR HTSSOP DDV 44 2000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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