PT5810 Series 20-A 3.3-V Input Adjustable Integrated Switching Regulator SLTS174 - JANUARY 2003 - REVISED APRIL 2003 Features • • • • • • • • 3.3 V Input 20 A Output Current DSP Compatible Low-Profile (8 mm) >90 % Efficiency Output Margin Control (±5 %) Adjustable Output Voltage Pre-Bias Startup Capability Description Ordering Information The PT5810 Excalibur™ series of integrated switching regulators (ISRs) combines outstanding power density with a comprehensive list of features. They are an ideal choice for applications where board space is a premium and performance cannot be compromised. These modules provide a full 20 A of output current, yet are housed in a low-profile, 18-pin, package that is almost half the size of the previous product generation. The integral copper case construction requires no heatsink, and offers the advantages of solderability and a small footprint (0.736 in² for suffix ‘N’). Both through-hole and surface mount pin configurations are available. The PT5810 series operates from a 3.3-V input bus to provide a convenient point-of-load power source for the industry’s latest high-performance DSPs and microprocessors. The series includes output voltage options as low as 1.0 VDC. Other features include external output voltage adjustment, a ±5 % margin control, on/off inhibit, short circuit protection, thermal shutdown, and a differential remote sense. PT5812H PT5813H PT5814H PT5815H PT5816H • • • • On/Off Inhibit Function Over-Current Protection Thermal Shutdown Small Footprint (0.736 in², Suffix ‘N’) • Surface Mount Compatible • IPC Lead Free 2 Pin-Out Information Pin Function = 2.5 Volts = 1.8 Volts = 1.5 Volts = 1.2 Volts = 1.0 Volts 1 Vo Adjust 2 3 Inhibit* Margin Dn* 4 Margin Up* 5 Vin 6 7 Vin Vin 8 Sense(–) 9 GND Package Code 10 11 GND GND (EPP) (EPQ) (EPS) 12 GND 13 GND 14 15 Vout Vout 16 Vout 17 Vout 18 Sense(+) PT Series Suffix (PT1234 x ) Case/Pin Configuration Order Suffix N A C Vertical Horizontal SMD (Reference the applicable package code drawing for the dimensions and PC board layout) * Denotes negative logic: Open = Normal operation Ground = Function active Standard Application Margin Dn Margin Up Sense(+) Vo Adjust 5, 6, 7 CIN 1,000 µF (Required) + VIN 4 3 18 2 9–13 Inhibit VOUT 14–17 PT5800 8 COUT 330 µF (Required) + 1 L O A D Sense(–) GND GND For technical support and more information, see inside back cover or visit www.ti.com Cin = Required 1,000 µF Cout = Required 330 µF PT5810 Series 20-A 3.3-V Input Adjustable Integrated Switching Regulator Specifications (Unless otherwise stated, T a =25 °C, Vin =3.3 V, Vout =1.8 V, C in =1,000 µF, Cout =330 µF, and I o =Io max) Characteristics Symbols Output Current Input Voltage Range Set-Point Voltage Tolerance Temperature Variation Line Regulation Load Regulation Total Output Variation Io Vin Vo tol ∆Regtemp ∆Regline ∆Regload ∆Regtot Efficiency η Vo Ripple (pk-pk) Transient Response Over-Current Threshold Output Voltage Adjust Vr ttr ∆Vtr ITRIP Vo adj Switching Frequency Inhibit Control (pin 2) Input High Voltage Input Low Voltage Input Low Current ƒs Standby Input Current External Input Capacitance External Output Capacitance Operating Temperature Range Over-Temperature Protection Solder Reflow Temperature Storage Temperature Reliability Iin standby Cin Cout Ta OTP Treflow Ts MTBF VIH VIL IIL Mechanical Shock Mechanical Vibration Weight Flammability SLTS174 - JANUARY 2003 - REVISED APRIL 2003 — — Conditions Min Over Io range –40°C <Ta < +85 °C Over Vin range Over Io range Includes set-point, line, load, –40°C ≤ T a ≤ +85 °C PT5812 (2.5 V) Io =12 A PT5813 (1.8 V) PT5814 (1.5 V) PT5815 (1.2 V) PT5816 (1.0 V) 20 MHz bandwidth 1 A/µs load step, 50 to 100 % I omax, Recovery Time Vo over/undershoot Reset, followed by auto-recovery With Vo Adjust With Margin Up/Dn Over Vin and Io ranges Referenced to GND (pins 9–13) Pin 2 to GND Pin 2 to GND Over Vin range Measured at center of case, auto-reset Surface temprature of module pins or case — Per Bellcore TR-332 50% stress, Ta =40°C, ground benign Mil-STD-883D, Method 2002.3 Half Sine, mounted to a fixture Mil-STD-883D, Method 2007.2, 20-2000 Hz, PCB mounted — Materials meet UL 94V-0 PT5810 SERIES Typ Max Units 0 2.95 (1) — — — — — — — ±0.5 ±4 ±2 20 3.65 ±2 — — — A V %Vo %Vo mV mV — — ±3 %Vo — — — — — — 93 90 89 87 84 20 — — — — — — — — — — — 250 50 120 30 ±15 (2) ±5 300 — — — — — 350 µSec mV A Vin –0.5 –0.2 — — 1,000 (4) 330 (5) –40 (5) — — -40 — — –0.2 5 — — — 110 — — Open (3) 0.6 — — — 5,000 +85 (6) — 215 (7) +125 V mA mA µF µF °C °C °C °C 5.8 — — 106 Hrs — 500 — G’s — 20 (8) — G’s — 20 — grams % mVpp % kHz Notes: (1) The minimum input voltage is equal to 2.95 V or Vout + 0.75 V, whichever is greater. (2) This is a typical value. For the adjustment limits of a specific model consult the related application note on output voltage adjustment. (3) The Inhibit control (pin 2) has an internal pull-upto Vin, and if left open-circuit the module will operate when input power is applied. A small lowleakage (<100nA) MOSFET is recommended to control this input. See application notes for more information. (4) A 1,000 µF electrolytic input capacitor is required for proper operation. This capacitor must be rated for a minimumm of 0.7 Arms of ripple current. (5) For operation below 0 °C, COUT must have stable characteristics. Use either low-ESR tantalum or Oscon® type capacitors. (6) See SOA curves or consult factory for the appropriate derating. (7) During solder reflow of SMD package version do not elevate the module case, pins, or internal component temperatures above a peak of 215 °C. For further guidance refer to the application note, “Reflow Soldering Requirements for Plug-in Power Surface Mount Products,” (SLTA051) (8) The case pins on the through-hole package types (suffixes N & A) must be soldered. For more information see the applicable package outline drawing. For technical support and more information, see inside back cover or visit www.ti.com PT5810 Series 20-A 3.3-V Input Adjustable Integrated Switching Regulator SLTS174 - JANUARY 2003 - REVISED APRIL 2003 Pin Descriptions Vin: The positive supply voltage input for the module with respect to the common ground (GND). Vout: This is the regulated output voltage from the module with respect to the common ground (GND). GND: The common node to which the input, output, and external control signals are referenced. Sense(–): Provides the regulator with the ability to sense the set-point voltage directly across the load. For optimum output voltage accuracy this pin should always be connected to GND, even for applications that demand a relatively light load. Sense(+): When used with Sense(–), the regulation circuitry will compensate for voltage drop between the converter and the load. The pin may be left open circuit, but connecting it to Vout will optimize load regulation. Inhibit*: This is an open-collector (open-drain) negative logic input that is referenced to GND. Pulling this pin to GND disables the module’s output voltage. If Inhibit* is left open-circuit, the output will be active whenever a valid input source is applied. Vo Adjust: This pin is used to trim the output voltage to a value within the range of ±10 % of nominal. The adjustment method uses an external resistor. The resistor is connected from Vo Adjust to either the (-)Sense or (+)Sense, in order to adjust the output up or down, respectively. Margin Dn*: When this open-collector (open-drain) input is asserted to GND, the output voltage is automatically decreased by 5 % from the nominal. This feature is used in applications where the load circuit must be tested for operation at the extreme values of its supply voltage tolerance. Margin Up*: This is an open-collector (open-drain) input. When this is asserted to GND, the output voltage is automatically increased by 5 % from the nominal. Typical Characteristics Performance Data; Vin =3.3 V (See Note A) Efficiency vs Output Current Power Dissipation vs Output Current 100 6 5 PT5812 PT5813 PT5814 PT5815 PT5816 80 70 4 Pd - Watts Efficiency - % 90 3 2 60 1 50 0 0 4 8 12 16 20 0 4 8 Iout - Amps 16 20 Safe Operating Curves; Vin =3.3 V (See Note B) Output Ripple vs Output Current 90 50 80 PT5814 PT5812 PT5813 PT5816 PT5815 30 20 10 Ambient Temperature (°C) 60 40 Ripple - mV 12 Iout - Amps Airflow 70 200LFM 120LFM 60LFM Nat Conv 60 50 40 30 0 20 0 5 10 15 20 0 Iout - Amps 4 8 12 16 20 Iout (A) Note A: Characteristic data has been developed from actual products tested at 25 °C. This data is considered typical data for the ISR. Note B: SOA curves represent operating conditions at which internal components are at or below manufacturer’s maximum rated operating temperatures. For technical support and more information, see inside back cover or visit www.ti.com Application Notes PT5800 & PT5810 Series Operating Features and System Considerations for the PT5800 & PT5810 Regulator Series The PT5800 (5-V input) and the PT5810 (3.3-V input) series of integrated switching regulators (ISRs) provide step-down voltage conversion for output loads of up to 20 A. Power up & Soft-Start Timing Following either the application of a valid input source voltage, or the removal of a ground signal to the Inhihit* control pin (with input power applied), the regulator will initiate a soft-start power up. The soft start slows the rate at which the output voltage rises, and also introduces a short time delay, td (approx. 2 ms). Figure 1-1 shows the power-up characteristic of a PT5801 (3.3 V) with a 10-A load. Figure 1-1 Vo (2V/Div) Vin (2V/Div) td HORIZ SCALE: 5ms/Div Differential Remote Sense Connecting the Sense(+) and Sense(-) pins to the load circuit allows the regulator to compensate for limited amounts of ‘IR’ voltage drop. This voltage drop is caused by current flowing through the connection resistance between the regulator and the ‘point of regulation’ some distance away. Leaving the sense pins disconnected will not damage the regulator or load circuitry. An internal 15 Ω resistor, connected between each sense pin and its corresponding output node, keeps the output voltage in regulation. However, it is important to connect Sense(–) to GND locally, as this provides a return path for the regulator’s internal bias currents. With the sense leads connected, the difference between the voltage measured at Vout and GND pins, and that measured from Sense(+) to Sense(–), is the amount of IR drop being compensated by the regulator. This should be limited to 0.6 V. (0.3 V maximum between pins 17 & 18, and also between pins 8 & 9). Note: The remote sense feature is not designed to compensate for the forward drop of non-linear or frequency dependent components that may be placed in series with the converter output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When these components are enclosed by the remote sense connections they are effectively placed inside the regulation control loop, which can adversely affect the stability of the regulator. Over-Current Protection To protect against load faults, the regulators incorporate output over-current protection. Applying a load that exceeds the regulator’s over-current threshold (see data sheet specifications) will cause the regulated output to shut down. Following shutdown the ISR will periodically attempt to recover by initiating a soft-start power-up. This is often described as a “hiccup” mode of operation, whereby the module continues in the cycle of successive shutdown and power up until the load fault is removed. During this period, the average current flowing into the fault is significantly reduced. Once the fault is removed, the converter automatically recovers and returns to normal operation. Over-Temperature Protection An on-board temperature sensor protects the module’s internal circuitry against excessively high temperatures. A rise in the internal temperature may be the result of a drop in airflow, or a high ambient temperature. If the internal temperature exceeds the OTP threshold (see data sheet specifications), the regulator’s Inhibit* control is automatically pulled low. This disables the regulator, allowing the output voltage to drop to zero as the external output capacitors are discharged by the load circuit. The recovery is automatic, and begins with a soft-start power up. It occurs when the the sensed temperature decreases by about 10 °C below the trip point. Note: The over-temperature protection is a last resort mechanism to prevent thermal stress to the regulator. Operation at or close to the thermal shutdown temperature is not recommended and will reduce the long-term reliability of the module. Always operate the regulator within the specified Safe Operating Area (SOA) limits for the worst-case conditions of ambient temperature and airflow. For technical support and more information, see inside back cover or visit www.ti.com Application Notes PT5800 & PT5810 Series Startup of the PT5800 & PT5810 Series ISRs with Back-Feeding Source (Pre-Bias Capability) In complex digital systems an external voltage can sometimes be present at the output of the regulator during power up. For example, this voltage may be backfed through a dual-supply logic component such as an FPGA or ASIC. Another path might be via a clamp diode (to a lower supply voltage) as part of a power-up sequencing implementation. 2. To ensure that the regulator does not sink current, the input voltage must always be greater or equal to the output voltage throughout the power-up and power-down sequence. 3. If an external source backfeeding the regulator’s output is greater than the nominal regulation voltage, the output will begin sinking current at the end of its soft-start power-up sequence. If this current exceeds the rated output, the module could be overstressed. Although the PT5800 (5-V input) and PT5810 (3.3-V input) series of regulators will sink current under steadystate operating conditions, they will not do so during startup 1 as long as certain conditions are maintained 2. This feature allows these regulators to start up while an external voltage is simultaneously applied to the output. Figure 2-1 is an application schematic that demonstrates this capability. The waveforms in Figure 2-2 show the behavior of the circuit as input power is applied. Note that the plot of the regulator output current (Io) is approximately zero up to the timestamp ‘A’, even though a voltage is initially backfed to the output via the 3.3-V input supply and diodes D1 & D2. The regulator sources current 3 when it begins raising the output above the back-fed voltage to its nominal regulation value. Figure 2-2; Power-up Waveforms with Back-Feeding Source Vin (1V/Div) Vo (1V/Div) Io (5A/Div) Notes 1. Startup includes both the application of a valid input source voltage, or the removal of a ground signal from the Inhibit* control (pin 2) with a valid input source applied. The output of the regulator is effectively off (tri-state), during the period that the Inhibit* control is held low. HORIZ SCALE 5ms/Div A Figure 2-1; Schematic Demonstrating Startup into Pre-Bias Capability (3.3 VDC) VIN D1 D2 18 Sense(+) 5–7 VIN PT5812 VOUT VO (2.5 V) 14–17 GND + COM Sense(–) 9–13 8 + CIN Io Cout COM For technical support and more information, see inside back cover or visit www.ti.com Application Notes PT5800/5810 Series Capacitor Recommendations for the PT5800 & PT5810 Step-Down Regulator Series Tantalum Capacitors (Optional Output Capacitors) Tantalum type capacitors can be used for the output but only the AVX TPS series, Sprague 593D/594/595 series, or Kemet T495/T510 series. These capacitors are recommended over many other tantalum types due to their higher rated surge, power dissipation, and ripple current capability. As a caution the TAJ series by AVX is not recommended. This series has considerably higher ESR, reduced power dissipation, and lower ripple current capability. The TAJ series is less reliable than the AVX TPS series when determining power dissipation capability. Tantalum or Oscon® types are recommended for applications where ambient temperatures fall below 0°C. Input Capacitor: The recommended input capacitance is determined by a 700-mA ripple current rating and the following minimum capacitance requirements. • PT5800 = 820 µF minimum capacitance • PT5810 = 1000 µF minimum capacitance Ripple current and <100 mΩ equivalent series resistance (ESR) values are the major considerations, along with temperature, when designing with different types of capacitors. Tantalum capacitors have a recommended minimum voltage rating of twice the maximum DC voltage + AC ripple. This is necessary to ensure reliability for input voltage bus applications Capacitor Table Table 2-1 identifies the characteristics of capacitors from a number of vendors with acceptable ESR and ripple current (rms) ratings. The number of capacitors required at both the input and output buses is identified for each capacitor type. Output Capacitors The ESR of the capacitors is less than 100mΩ. Electrolytic capacitors have marginal ripple performance at frequencies greater than 400 kHz, but excellent low frequency transient response. Above the ripple frequency ceramic capacitors are necessary. Ceramic capacitors improve the transient response and reduce any high frequency noise components apparent during high current excursions. Preferred low-ESR electrolytic capacitor part numbers are identified in Table 3-1. This is not an extensive capacitor list. Capacitors from other vendors are available with comparable specifications. Those listed are for guidance. The RMS ripple current rating and ESR (Equivalent Series Resistance) at 100 kHz are critical parameters necessary to insure both optimum regulator performance and long capacitor life. Table 3-1; Input/Output Capacitors Capacitor Vendor/Series Capacitor Characteristics Quantity Working Voltage Value (µF) (ESR) Equivalent Series Resistance Ripple Current I(rms)max @105°C Physical Size (mm) Input Bus Output Bus Panasonic FC (Radial) 10V 10V 1000 560 0.068Ω 0.090Ω 1050mA 755mA 10×16 10×12.5 1 2 1 1 EEUFC1C102 EEUFC1A561 FK (SMT) 10V 35V 1000 470 0080Ω 0.060Ω 850mA 1100mA 10×10.2 12.5×13.5 1 2 1 1 EEVFK1A102P EEVFK1V471Q 16V 10V 10V 470 1000 680 0.090Ω 0.068Ω 0.015Ω 760mA 1050mA 4735mA 10×12.5 10×16 10×10.5 2 1 2 1 1 1 LXZ16VB471M10X12LL LXZ10VB102M10X16LL 10FX680M NX Series (SMT) 10V 16V 10V 1000 560 330 0.065Ω 0.080Ω 0.024Ω 1040mA 920mA 3770mA 12.5×15 12.5×15 10×8 1 2 3 1 1 1 UPM1A102MHH6 UPM1C 561MHH6 PNX1A330MCR1GS Sanyo Os-con: SP SVP (SMT) 10V 10V 470 560 0.015Ω 0.013Ω >4500mA >5200mA 10×10.5 11×12.7 2 2 1 1 10SP470M 10SVP560M AVX Tantalum TPS (SMT) 10V 10V 470 470 0.045Ω 0.060Ω 1723mA 1826mA 7.3L ×5.7W ×4.1H 2 2 1 1 TPSE477M010R0045 TPSV477M010R0060 Kemet Polymer Tantalum T520/T530Series (SMT) 10V 10V 330 330 0.040Ω 0.015Ω 1800mA >3800mA 7.3×4.3×4 3 3 1 1 T520X337M010AS T530X337M010AS Sprague Tantalum 594D Series (SMT) 10V 680 0.090Ω 1660mA 7.2×6×4.1 2 1 595D687X0010R2T United Chemi-con LXZ/LXV Series FX Series Nichicon PL/PM Series For technical support and more information, see inside back cover or visit www.ti.com Vendor Part Number Application Notes PT5800 & PT5810 Series Using the Inhibit Control of the PT5800 & PT5810 Series of Step-Down ISRs For applications requiring output voltage On/Off control, the PT5800 & PT5810 series of ISRs incorporate an inhibit function. This function can be used wherever there is a requirement for the output voltage from the ISR to be turned off. The On/Off function is provided by the Inhibit* control (pin 2). The ISR functions normally with pin 2 open-circuit, providing a regulated output whenever a valid source voltage is applied between Vin (pins 5–7) and GND (pins 9–13). When a low-level ground signal is applied to pin 2, the regulator output is turned off 2. Figure 4-1 shows the typical application of the Inhibit* function. Note the discrete transistor (Q1). The Inhibit* control has its own internal pull-up to +Vin potential. An open-collector or open-drain device is recommended to control this input 1. The voltage thresholds are given in Table 4-1. Turn-On Time: In the circuit of Figure 4-1, turning Q1 on applies a low-voltage to the Inhibit* control (pin 2) and disables the output of the regulator 2. If Q1 is then turned off, the ISR executes a soft-start power up. Power up consists of a short delay (approx. 2msec), followed by a period in which the output voltage rises to its full regulation voltage. The module produces a regulated output voltage within 10msec. Figure 4-2 shows the typical rise in both the output voltage and input current for a PT5812 (2.5 V), following the turn-off of Q1. The turn off of Q1 corresponds to the rise in the waveform, Q 1 Vds. The waveforms were measured with a 3.3 VDC input voltage, and 10-A load. Figure 4-2 Table 4-1; Inhibit Control Requirements Vo (1V/Div) Parameter Enable (VIH) Disable (VIL) Min Typ Vin – 0.5 V –0.2 V — Open — +0.6 V — –0.2 mA — I IL Max Iin (5A/Div) Q1 Vds (2V/Div) Figure 4-1 HORIZ SCALE: 2ms/Div Output Sense (+) VIN 5, 6, 7 4 + 1 =Inhibit 18 9–13 VOUT 14–17 PT5812 2 CIN 1,000 µF 3 8 COUT 330 µF + 1 Q1 BSS138 Output Sense (–) GND GND Notes: 1. Use an open-collector device with a breakdown voltage of at least 10 V (preferably a discrete transistor) for the Inhibit* input. A pull-up resistor is not necessary. To disable the output voltage the control pin should be pulled low to less than +0.8 VDC. 2. When a ground signal is applied to the Inhibit* control (pin 2) the module output is turned off (tri-state). The output voltage decays to zero as the load impedance discharges the output capacitors. For technical support and more information, see inside back cover or visit www.ti.com Application Notes PT5800 & PT5810 Series Adjusting the Output Voltage of the PT5800 & PT5810 Step-Down Series of Regulators The Margin Up* (pin 4) and Margin Dn* (pin 3) control inputs allow the output voltage to be easily adjusted by up to ±5 % of the nominal set-point voltage. To activate, simply connect the appropriate control input to the Sense(–) (pin 8), or the local starpoint ground. Either a logic level MOSFET or a p-channel JFET is recommended for this purpose. For further information see the related application note on this feature. Using the ‘Vo Adjust’ Control For a more permanent and precise adjustment, use the Vo Adjust control (pin 1). The Vo Adjust control allows adjustment in any increment by up to ±10% of the setpoint. The adjustment method requires the addition of a single external resistor. Table 5-1 gives the allowable adjustment range for each model of the series as Va (min) and Va (max). The value of the external resistor can either be calculated using the formulas given below, or simply selected from the range of values provided in Table 5-2. Refer to Figure 5-1 for the placement of the required resistor. Use the resistor R1 to adjust up, and the resistor (R2) to adjust down. Adjust Up: An increase in the output voltage is obtained by adding a resistor R1, between Vo Adjust (pin 1) and Sense(–) (pin 8). See Figure 5-1. 4. The PT5812 may not be adjusted higher than the nominal output voltage of 2.5 V. There is insufficient input voltage between V in and Vout to accommodate an increase in the output voltage. Vo Adjust Resistor Calculations The values of R1 [adjust up] and (R2) [adjust down] can also be calculated using the following formulas. Again, use Figure 5-1for the placement of the required resistor; either R1 or (R2) as appropriate. R1 (R2) Ro (Va – Vr) = Where: Vo Va Vr Ro = = = = Sense (+) [Note 3] (R2) Adj Down 18 Sense(+) PT5800/5810 GND 9–13 Sense(–) VOUT 14–17 1 COUT 330 µF R1 Adjust Up Sense (–) GND PT5805 PT5815 PT5806 PT5816 3.3 V 2.5 V 1.8 V 1.5 V 1.2 V 1.0 V Va (min) 2.6 V 2.0 V 1.52 V 1.31 V 1.1 V 0.94 V Va (max) 3.63 V 2.8 V # 2.1 V 1.82 V 1.52 V 1.32 V Vr Ω) Ro (kΩ 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V 9.76 VOUT VO Adj 8 Vo (nom) 10.2 kΩ Figure 5-1; Vo Adjust Resistor Placement Table 5-1 10.7 – 24.9 Original output voltage Adjusted output voltage The reference voltage in Table 5-1 The resistance constant in Table 5-1 3. If the remote sense feature is not being used, the adjust resistor (R2) can be connected to Vout, (pins 14-17) instead of Sense (+). 10.2 kΩ Vo – Va 2. Never connect capacitors from Vo Adjust to either GND or Vout. Any capacitance added to the Vo Adjust pin will affect the stability of the ISR. ISR OUTPUT VOLTAGE ADJUSTMENT RANGE AND FORMULA PARAMETERS Series Pt. No. 5.0V Bus PT5801 PT5802 PT5803 PT5804 3.3V Bus N/A PT5812 4 PT5813 PT5814 – 24.9 Va – Vo Adjust Down: Add a resistor (R2), between Vo Adjust (pin 1) and Sense(+) (pin 18). See Figure 5-1. Notes: 1. Use a 1% (or better) tolerance resistor in either the R1 or (R2) location. Place the resistor as close to the ISR as possible. Vr · Ro = + Using Margin Up/ Margin Down 10.0 # The PT5812 should not be adjusted higher than its nominal output voltage of 2.5 V. See note 4. For technical support and more information, see inside back cover or visit www.ti.com 10.2 Application Notes continued PT5800 & PT5810 Series Table 5-2 ISR ADJUSTMENT RESISTOR VALUES Series Pt. No. 5.0V Bus PT5801 PT5802 3.3V Bus N/A PT5812 Vo (nom) 3.3 V 2.5 V Va (req.d) PT5803 PT5813 1.8 V PT5804 PT5814 1.5 V PT5805 PT5815 1.2 V PT5806 PT5816 1.0V Va (req.d) 3.60 2.3 kΩ 2.100 3.55 7.7 kΩ 2.050 7.7 kΩ 3.50 15.9 kΩ 2.000 15.9 kΩ 3.45 29.5 kΩ 1.950 29.5 kΩ 3.40 56.7 kΩ 1.900 56.7 kΩ 3.35 138.0 kΩ 1.850 138.0 kΩ 3.30 2.3 kΩ 1.800 1.1 kΩ 3.25 (475.0) kΩ 1.750 (169.0) kΩ 6.3 kΩ 3.20 (220.0) kΩ 1.700 (66.9) kΩ 14.1 kΩ 3.15 (135.0) kΩ 1.650 (32.9) kΩ 27.2 kΩ 3.10 (92.4) kΩ 1.600 (15.9) kΩ 53.2 kΩ 3.05 (66.9) kΩ 1.550 (5.7) kΩ 131.0 kΩ 3.00 (49.9) kΩ 1.500 2.95 (37.5) kΩ 1.475 (239.0) kΩ 2.90 (28.6) kΩ 1.450 (102.0) kΩ 7.1 kΩ 2.85 (21.6) kΩ 1.425 (56.4) kΩ 10.7 kΩ 2.80 (15.9) kΩ 3.6 kΩ 1.400 (33.7) kΩ 15.1 kΩ 2.75 (11.3) kΩ 9.3 kΩ 1.375 (20.0) kΩ 20.8 kΩ 2.70 (7.4) kΩ 17.9 kΩ 1.350 (10.9) kΩ 28.4 kΩ 2.65 (4.1) kΩ 32.2 kΩ 1.325 (4.4) kΩ 39.1 kΩ 2.60 (1.3) kΩ 60.7 kΩ 1.300 55.1 kΩ 2.3 kΩ [Note 4] 146.0 kΩ 1.275 81.8 kΩ 4.8 kΩ 1.250 135.0 kΩ 7.7 kΩ 295.0 kΩ 11.4 kΩ 2.550 2.500 1.8 kΩ 4.2 kΩ 2.450 (321.0) kΩ 1.225 2.400 (146.0) kΩ 1.200 2.350 (85.7) kΩ 1.175 (125.0) kΩ 21.7 kΩ 2.300 (55.3) kΩ 1.150 (45.1) kΩ 29.5 kΩ 2.250 (37.2) kΩ 1.125 (18.4) kΩ 40.4 kΩ 2.200 (25.0) kΩ 1.100 (5.1) kΩ 56.7 kΩ 2.150 (16.4) kΩ 1.075 83.9 kΩ 2.100 (9.9) kΩ 1.050 138.0 kΩ 2.050 (4.8) kΩ 1.025 302.0 kΩ 2.000 (0.8) kΩ 1.000 R1 = Black 15.9 kΩ 0.975 (46.5) kΩ 0.950 (5.7) kΩ R2 = (Blue) For technical support and more information, see inside back cover or visit www.ti.com Application Notes PT5800 & PT5810 Series Using the Margin Up/Down Controls on the PT5800 & PT5810 Regulator Series The PT5800 & PT5810 series of integrated switching regulator modules incorporate Margin Up* (pin 4) and Margin Dn* (pin 3) control inputs. These controls allow the output voltage set point to be momentarily adjusted 1, either up or down, by a nominal 5 %. This provides a convenient method for dynamically testing the load circuit’s power supply voltage over its operating margin or range. Note that the ±5 % change is also applied to any adjustment of the output voltage, if made, using the Vo Adjust (pin 1). Notes: 1. The Margin Up* and Margin Dn* controls were not intended to be activated simultaneously. If they are their affects on the output voltage may not completely cancel, resulting in a slight shift in the output voltage set point. 2. When possible use the Sense(-) (pin 8) as the ground reference. This will produce a more accurate adjustment of the output voltage at the load circuit terminals. GND (pins 9-13) can be used if the Sense(-) pin is connected to GND near the regulator. The 5 % adjustment is made by driving the appropriate margin control input directly to the ground reference at Sense(-) (pin 8) 2. An low-leakage open-drain device, such as a MOSFET or a p-channel JFET is recommended for this purpose. Adjustments of less than 5 % can also be accommodated by adding series resistors to the control inputs (See Figure 6-1). The value of the resistor can be selected from Table 6-1, or calculated using the following formula. Table 6-1; Margin Up/Down Resistor Values PADDING RESISTOR VALUES % Adjust Resistor Value Calculation To reduce the margin adjustment to something less than 5 %, series padding resistors are required (See RD and RU in Figure 6-1). For the same amount of adjustment, the resistor value calculated for RU and RD will be the same. The formulas is as follows. RU/RD = 499 ∆% – 99.8 RU / RD 5 4 3 2 1 0.0 kΩ 24.9 kΩ 66.5 kΩ 150.0 kΩ 397.0 kΩ kΩ Where ∆% = The desired amount of margin adjust in percent. Figure 6-1; Margin Up/Down Application Schematic +V o +5 V 5, 6, 7 4 3 18 MARG UP* MARG DN* SNS(+) PT5800 VIN INHIBIT* 2 RD GND 9–13 0V +VOUT 14–17 V OUT SNS(–) 8 RU + + C in C out L O A D Q1 MargDn Q2 MargUp Sense(–) GND For technical support and more information, see inside back cover or visit www.ti.com GND 0V IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated