KIC7SZ38FU SEMICONDUCTOR SILICON MONOLITHIC CMOS DIGITAL INTEGRATED CIRCUIT TECHNICAL DATA 2 INPUT NAND GATE (Open Drain Output) FEATURES ・Open Drain Output Stage for OR tied application. ・Super High Speed : 2.4ns(Typ.) 50pF at VCC=5V. B ・High Output Sink Drive : 24mA at VCC=3V. B1 ・Operating Voltage Range : VCC(opr)=1.65~5.5V. 1 5 2 C A A1 C ・Power Down High Impedance Inputs/Outputs. 4 H 3 T MILLIMETERS _ 0.20 2.00 + _ 0.1 1.3 + _ 0.1 2.1 + _ 0.1 1.25 + 0.65 0.2+0.10/-0.05 0-0.1 _ 0.1 0.9 + 0.15+0.1/-0.05 G MAXIMUM RATINGS (Ta=25℃) CHARACTERISTIC D DIM A A1 B B1 C D G H T SYMBOL RATING UNIT Power Supply Voltage Range VCC -0.5~6 V DC Input Voltage VIN -0.5~6 V DC Output Voltage VOUT -0.5~6 V Input Diode Current IIK -50~20 mA Output Diode Current IOK -50~20 mA DC Output Current IOUT 50 mA DC VCC/Ground Current ICC ±50 mA Power Dissipation PD 200 mW Storage Temperature Range Tstg -65～150 ℃ Lead Temperature (10s) TL 260 ℃ USV MARKING Type Name T N PIN CONNECTION(TOP VIEW) 2002. 5. 13 Revision No : 0 IN B 1 IN A 2 GND 3 5 4 VCC OUT Y 1/3 KIC7SZ38FU Logic Diagram IN B IN A (1) & (2) (4) OUT Y ELECTRICAL CHARACTERISTICS DC Characteristics CHARACTERISTIC High Level TEST CONDITION SYMBOL VIH - Low Level High Level VIL ILKG MIN. TYP. MAX. MIN. MAX. 1.65~1.95 0.75× VCC - - 0.75× VCC - - - 0.7×VCC - 1.65~1.95 - - 0.25× VCC - 0.25× VCC 2.3~5.5 - - 0.3×VCC - 0.3×VCC 5.5 - - ±5 - ±10 1.65 - 0 0.1 - 0.1 1.8 - 0 0.1 - 0.1 2.3 - 0 0.1 - 0.1 3.0 - 0 0.1 - 0.1 4.5 - 0 0.1 - 0.1 IOL=4mA 1.65 - 0.08 0.24 - 0.24 IOL=8mA 2.3 - 0.10 0.3 - 0.3 IOL=16mA 3.0 - 0.15 0.4 - 0.4 IOL=24mA 3.0 - 0.22 0.55 - 0.55 IOL=32mA 4.5 - 0.22 0.55 - 0.55 VIN=VIL VOUT = VCC or GND IOL=100μA Low Level VOL VIN=VIH Ta=-40~85℃ VCC(V) 2.3~5.5 0.7×VCC Input Voltage Output Leakage Voltage Ta=25℃ UNIT V μA V Input Leakage Current IIN VIN=5.5V or GND 0~5.5 - - ±1 - ±10 μA Power Off Leakage Current IOFF VIN or VOUT=5.5V 0.0 - - 1 - 10 μA Quiescent Supply Current ICC VIN=5.5V or GND 5.5 - - 2.0 - 20 μA 2002. 5. 13 Revision No : 0 2/3 KIC7SZ38FU AC Characteristics (unless otherwise specified, Input : tr=tf=3ns) CHARACTERISTIC TEST CONDITION SYMBOL tPZL CL=50pF, RU=500Ω RD=500Ω VI=2×VCC (Figures 1,3) Propagation delay time tPLZ CL=50pF, RU=500Ω RD=500Ω VI=2×VCC (Figures 1,3) Ta=25℃ Ta=-40~85℃ VCC(V) MIN. TYP. MAX. MIN. MAX. 1.65 1.5 6.5 12.7 1.5 13.2 1.8 1.5 5.4 10.5 1.5 11.0 2.5±0.2 0.8 3.5 7.0 0.8 7.5 3.3±0.3 0.8 2.8 5.0 0.8 5.2 5.0±0.5 0.5 2.2 4.3 0.5 4.5 1.65 1.5 5.5 12.7 1.5 13.2 1.8 1.5 4.6 10.5 1.5 11.0 2.5±0.2 0.8 3.0 7.0 0.8 7.5 3.3±0.3 0.8 2.1 5.0 0.8 5.2 5.0±0.5 0.5 1.3 4.3 0.5 4.5 UNIT ns ns CIN - 0 - 4 - - - pF Output Capacitance COUT - 0 - 5 - - - pF Power Dissipation Capacitance CPD 3.3 - 5.1 - - - 5.0 - 7.3 - - - Input Capacitance (Note) (Figures 2) pF Note : CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output loading and operating at 50% duty cycle. (See Figure2.) CPD is related to ICCD dynamic operating current by the expression : ICCD=CPD・VCC・fIN+ICC Static AC Loading and Waveforms VCC VCC A RU OUTPUT INPUT INPUT RD CL CL includes load and stray capacitance Input PRR=1.0MHz ; t w =500ns Input=AC Waveform ; t r =tf =1.8ns PRR=10MHz ; Duty Cycle=50% FIGURE 1. AC Test Circuit t r =3ns FIGURE 2. ICCD Test Circuit t f =3ns INPUT tw 90% 50% 10% VCC GND t PLZ t PZL VOH OUTPUT 50% VOL +0.3V VOL FIGURE 3. AC Waveforms 2002. 5. 13 Revision No : 0 3/3