TPS657052 TPS657051 www.ti.com SLVSA08 – FEBRUARY 2010 PMU for Embedded Camera Module Check for Samples: TPS657052, TPS657051 FEATURES 1 • • • • • • • • • • • Two 400mA Step-Down Converters Up to 92% Efficiency VIN Range for DCDC Converter From 3.3V to 6V 2.25 MHz Fixed Frequency Operation Power Save Mode at Light Load Current Output Voltage Accuracy in PWM Mode ±1.5% 100% Duty Cycle for Lowest Dropout 180° Out of Phase Operation 1 General Purpose 200mA LDO VIN Range for LDO From 1.7V to 6.0V Available in a 16 Ball WCSP With 0.5mm Pitch APPLICATIONS • • • Digital Cameras Portable Media Players Handheld Equipment DESCRIPTION TPS657051/52 are small power management units targeted for embedded camera module or other portable low power consumer end equipments. It contains two high efficient step down converters, a low dropout linear regulator and additional supporting functions. The 2.25MHz step-down converter enters a low power mode at light load for maximum efficiency across the widest possible range of load currents. For low noise applications the devices can be forced into fixed frequency PWM mode using the MODE pin. The device allows the use of small inductors and capacitors to achieve a small sized solution. TPS657051/52 provides an output current of up to 400mA on both DCDC converters and integrates one 200mA LDO with different output settings. The LDO operates with an input voltage range between 1.7V and 6.0V allowing it to be supplied from the output of the step-down converter or directly from the system voltage. VCC TPS 657051/52 10 mF The TPS657051/52 comes in a small 16-ball wafer chip scale package (WCSP) with 0.5mm ball pitch. 2.2 μH L1 VIN1 MODE DCDC1 EN1 400 mA FB1 Vout1 10uF PGND CLK0° 2.25 MHz Oscillator VIN2 EN2 CLK180° L2 2.2 μH Vout2 DCDC2 400 mA FB2 10 mF PGND VLDO VINLDO ENLDO LDO 200 mA Vout3 2.2 mF AGND Figure 1. Application Circuit 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS657052 TPS657051 SLVSA08 – FEBRUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TA PART NO. (1) SIZE FOR WCSP VERSION OPTIONS PACKAGE CODE I2C PACKAGE PACKAGE MARKING –40°C to 85°C TPS657051 D = 2076 µm ± 25 µm E = 2076 µm ± 25 µm DCDC1 3.3V FIX, DCDC2 1.8 V FIX DCDC CONVERTERS 400mA, LDO VOUT 3.0V FIX, 200mA YZH N/A WCSP TPS657051 –40°C to 85°C TPS657052 D = 2076 µm ± 25 µm E = 2076 µm ± 25 µm DCDC1 3.3V FIX, DCDC2 1.8 V FIX DCDC CONVERTERS 400mA, LDO VOUT 2.8V FIX, 200mA YZH N/A WCSP TPS657052 (1) NO NOTE FOR PART NO IN SOURCE? FC ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE / UNIT Input voltage range on all pins except A/PGND pins with respect to AGND –0.3 to 7 V Voltage range on pin VLDO1 with respect to AGND –0.3 to 3.6 V Current at L1, VLDO1, VINLDO1, PGND 600 mA Current at AGND 20 mA Current at all other pins 3 mA Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature, TA –40°C to 85°C Maximum junction temperature, TJ 125°C Storage temperature, TST –65°C to 150°C DISSIPATION RATINGS DEVICE PACKAGE RqJA TA ≤ 25°C POWER RATI4NG TPS657051/52 (1) YZH 185 TPS657051/52 (2) YZH 75 (1) (2) 2 DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 540mW 5.4mW 297mW 216mW 1.3W 13.3mW 0.7W 0.5W The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board. The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 TPS657052 TPS657051 www.ti.com SLVSA08 – FEBRUARY 2010 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM 3.3 MAX UNIT VIN1/2 Input voltage range for step-down converter DCDC1and DCDC2 IOUTDCDC1/2 Output current at L L Inductor at L 1.5 VINLDO Input voltage range for LDO 1.7 ILDO Output current at LDO CINDCDC1/2 Input Capacitor at VIN1 and VIN2 4.7 COUTDCDC1/2 Output Capacitor at VOUT1, VOUT2 4.7 CINLDO Input Capacitor at VINLDO 2.2 µF COUTLDO Output Capacitor at VLDO 2.2 µF TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C 2.2 6.0 V 400 mA 4.7 µH 6.0 V 200 mA µF 10 22 µF ELECTRICAL CHARACTERISTICS Unless otherwise noted: VIN1=VIN2=VINLDO=3.6 V, L=LQMP21P 2.2µH, COUTDCDCx = 10µF, COUTLDO =2.2µF, TA = –40°C to +85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT DCDC1 and DCDC2 enabled, IOUT = 0 mA, MODE =0 (PFM mode), LDO disabled 40 µA DCDC1 or DCDC2 enabled, IOUT = 0 mA, MODE =0 (PFM mode), LDO disabled 25 µA DCDC1 or DCDC2 enabled, IOUT = 0 mA. MODE =1 (forced PWM mode), LDO disabled 4 mA Operating quiescent current LDO DCDC1 and DCDC2 disabled, LDO enabled. IOUT = 0mA 25 37 µA Shutdown current DCDC1, DCDC2, and LDO disable 5 12 µA VCC V 0.4 V 0.10 mA Operating quiescent current DCDCx IQ ISD DIGITAL PINS (EN1, EN2, ENLDO, MODE) VIH High level input voltage for EN1, EN2, ENLDO, MODE VIL Low level input voltage for EN1, EN2, ENLDO, MODE ILKG Input leakage current 1.2 EN1, EN2, ENLDO, MODE tied to GND or VIN = VIN2 0.01 STEP-DOWN CONVERTERS VIN1 Input voltage for DCDC1 3.3 6.0 V VIN2 Input voltage for DCDC2 3.3 6.0 V 2.25 V UVLO Internal undervoltage lockout threshold VIN1 = VIN2 falling Internal undervoltage lockout threshold hysteresis VIN1 = VIN2 rising 2.15 2.2 120 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 mV 3 TPS657052 TPS657051 SLVSA08 – FEBRUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted: VIN1=VIN2=VINLDO=3.6 V, L=LQMP21P 2.2µH, COUTDCDCx = 10µF, COUTLDO =2.2µF, TA = –40°C to +85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SWITCH High side MOSFET on-resistance VIN1 = VIN2 = 3.6 V 350 750 mΩ Low side MOSFET on-resistance VIN1 = VIN2 = 3.6 V 350 600 mΩ ILIMF Forward current limit 3.3V ≤ VIN1 = VIN2 ≤ 6.0 V 650 770 mA IOUTDCDC1/2 DCDC1/DCDC2 output current VIN1 = VIN2 > 3.3 V , L = 2.2 µH 400 mA 2.48 MHz RDS(ON) 550 OSCILLATOR fSW Oscillator frequency 2.03 2.25 OUTPUT VOUT1 DCDC1 default output voltage VIN1 = VIN2 ≥ 3.3 V 3.3 VOUT2 DCDC2 default output voltage VIN1 = VIN2 ≥ 3.3 V 1.8 IFB FB pin input current DCDC converter disabled DC output voltage accuracy (1) VIN1 = VIN2 = 3.3 V to 6.0 V, +1% voltage positioning active; PFM operation, 0 mA < IOUT < IOUTMAX DC output voltage accuracy VIN1 = VIN2 = 3.3 V to 6.0 V, PWM operation, 0 mA < IOUT < IOUTMAX VOUT V V 0.1 +1% –1.5% µA +3% +1.5% DC output voltage load regulation PWM operation 0.5 %/A tStart Start-up time Time from active EN to Start switching 200 µs tRamp VOUT ramp time Time to ramp from 5% to 95% of VOUT 250 µs RDIS Internal discharge resistor at L1 or L2 (TPS657051 Only) DCDC1 or DCDC2 disabled 250 400 600 Ω THERMAL PROTECTION SEPARATELY FOR DCDC1, DCDC2 AND LDO1 TSD Thermal shutdown Increasing junction temperature 150 °C Thermal shudown hysteresis Decreasing junction temperature 30 °C VLDO, LOW DROPOUT REGULATOR VINLDO Input voltage range for LDO VLDO TPS657051 LDO default output voltage (2) 3.0 V VLDO TPS657052 LDO default output voltage (3) 2.8 V IO Output current for LDO ISC LDO short circuit current limit VLDO = GND Dropout voltage at LDO IO = 200 mA Output voltage accuracy for LDO IO = 100 mA, VOUT = 2.8V –2% +2% Line regulation for LDO VINLDO = VLDO + 0.5V (min. 1.7 V) to 6 V, IO = 50 mA –1% 1% Load regulation for LDO IO = 1 mA to 200 mA for LDO –1% 1% PSRR Power supply rejection ratio fNOISE ≤ 10 kHz, COUT ≥ 2.2 µf Vin = 5.0 V, Vout = 2.8 V, IOUT = 100 mA Vn Ouput noise voltage tRamp RDIS (1) (2) (3) 4 1.7 340 6.0 400 V 200 mA 550 mA 200 mV 50 dB Vout = 2.8 V, BW = 10Hz to 100kHz 160 µV RMS VOUT ramp time Internal soft-start when LDO is enabled; Time to ramp from 5% to 95% of VOUT 200 µs Internal discharge resistor at VLDO LDO disabled 250 400 550 Ω In Power Save Mode (PFM), the internal reference voltage is 1.01 × Vref. VINLDO > 3.0V VINLDO > 2.8V Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 TPS657052 TPS657051 www.ti.com SLVSA08 – FEBRUARY 2010 Chip Scale Version (YFF Package): PIN ASSIGNMENT (Top View – preliminary) 2075um VLDO AGND VIN VIN LDO LDO VCC EN1 EN2 VIN2 EN LDO LDO MODE L2 VIN1 2075um A1 B1 L1 C1 PGND PGND 1 D1 FB1 FB2 D2 D3 PGND PGND 2 2 D4 Figure 2. Preliminay Pin Out – Top View Chip Scale Version (YFF Package): PIN ASSIGNMENT (Bottom View – preliminary) 2075um VIN2 VIN VIN LDO LDO AGND EN2 EN1 VLDO A1 VIN1 B1 L2 EN EN LDO LDO MODE 2075um VCC L1 C1 PGND PGND 2 2 D4 FB2 FB1 D3 D2 PGND PGND 11 D1 Figure 3. Preliminay Pin Out – Bottom View Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 5 TPS657052 TPS657051 SLVSA08 – FEBRUARY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM VCC TPS657051/52 VIN1 2. 2 mH L1 Vout1 10 mF MODE DCDC1 EN1 400 mA FB 1 10 mF PGND CLK 0° 2 .25 MHz Oscillator CLK 180 ° L2 2. 2 mH VIN2 EN2 Vout2 DCDC2 400 mA FB 2 10 mF PGND VLDO VINLDO ENLDO Vout3 LDO 2 .2 mF 200 mA AGND 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 TPS657052 TPS657051 www.ti.com SLVSA08 – FEBRUARY 2010 Pin Functions for Chip Scale Version Based on Topview (YFF Package) PIN NAME VCC NO. A4 (1) I/O I DESCRIPTION Supply Input for internal reference, has to be connected to VIN1/ VIN2 AGND A2 Analog ground PGND1 D1 Power ground PGND2 D4 VIN2 B4 (2) VIN1 (2) B1 Power ground I Input voltage pin for buck converter 2 I Input voltage pin for buck converter 1 L1 C1 O Switch output from buck converter 1 FB1 D2 I Feedback input from buck converter 1 EN1 B2 I Actively high enable input voltage for buck converter 1 L2 C4 O Switch output from buck converter 2 FB2 D3 I Feedback input from buck converter 2 EN2 B3 I Actively high enable input voltage for buck converter 2 ENLDO C2 I Actively high enable input voltage for LDO VINLDO A3 I Input voltage pin for LDO VLDO A1 O Output voltage from LDO MODE C3 I Set low to enable Power Save Mode. Pulling this PIN to high forces the device to operate in PWM mode over the whole load range. (1) (2) VCC has to be the highest input for device to function correctly. VIN1/VIN2 must be connected to VCC. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 7 TPS657052 TPS657051 SLVSA08 – FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE vs Load current / PFM mode Figure 4 Efficiency DCDC (VDCDC= 3.3V), L = BRC1608 1.5 µH vs Load current / PWM mode Figure 5 Efficiency DCDC (VDCDC= 1.8V), L = BRC1608 1.5 µH vs Load current / PFM mode Figure 6 Efficiency DCDC (VDCDC= 1.8V), L = BRC1608 1.5 µH vs Load current / PWM mode Figure 7 Line transient response DCDC 1.8V (PWM) Scope plot Figure 8 Line transient response DCDC 1.8V (PFM) Scope plot Figure 9 Line transient response LDO 2.8V Scope plot Figure 10 Load transient reponse DCDC 1.8V (PWM/PFM) 20mA to 180mA Scope plot Figure 11 Load transient reponse DCDC 1.8V (PWM) 20mA to 180mA Scope plot Figure 12 Load transient reponse DCDC 1.8V (PFM/PWM) 20mA to 360mA Scope plot Figure 13 Load transient response DCDC 1.8V (PWM) 20mA to 360mA Scope plot Figure 14 Load transient response LDO 2.8V Scope plot Figure 15 DCDC PFM to PWM mode transition Scope plot Figure 16 DCDC PWM to PFM mode transition Scope plot Figure 17 DCDC Output voltage ripple in PFM mode Scope plot Figure 18 DCDC Output voltage ripple in PWM mode Scope plot Figure 19 Startup timing DCDC 1.8V Scope plot Figure 20 Startup timing LDO 2.8V Scope plot Figure 21 LDO PSRR Scope plot Figure 22 DCDC Quiescent current vs VINDCDC Figure 23 LDO Quiescent current vs VINDCDC Figure 24 Shutdown current vs VINDCDC Figure 25 100 100 90 90 80 80 70 70 Efficiency - % Efficiency - % Efficiency DCDC (VDCDC= 3.3V), L = BRC1608 1.5 µH 60 3.5 3.6 3.8 4.0 4.2 4.5 4.8 5.0 5.5 6.0 50 40 30 20 10 VOUT = 3.3 V, TA = 25°C L = BRC1608 1.5μA 0 0.001 0.01 0.1 IO - Output Current - A 50 40 30 20 10 1 Figure 4. Efficiency DCDC (VDCDC=3.3V) vs Load Current PFM Mode 8 60 0 0.001 VOUT = 3.3 V, TA = 25°C L = BRC1608 1.5μA 0.01 0.1 IO - Output Current - A 3.5 3.6 3.8 4.0 4.2 4.5 4.8 5.0 5.2 5.5 6.0 1 Figure 5. Efficiency DCDC (VDCDC=3.3V) vs Load Current PWM Mode Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 TPS657052 TPS657051 www.ti.com SLVSA08 – FEBRUARY 2010 90 90 80 80 70 70 Efficiency - % 100 Efficiency - % 100 60 50 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 40 30 20 10 VOUT = 1.8 V, TA = 25°C L = BRC1608 1.5μA 0 0.001 0.01 0.1 IO - Output Current - A VOUT = 1.8 V, TA = 25°C L = BRC1608 1.5 μA 60 50 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 40 30 20 10 0 0.001 1 Figure 6. Efficiency DCDC (VDCDC=1.8V) vs Load Current PFM mode 0.01 0.1 IO - Output Current - A 1 Figure 7. Efficiency DCDC (VDCDC=1.8V) vs Load Current PWM mode VINDCDC = 3.6V to 4.2V to 3.6V Temperature = 25°C VINDCDC DCDC Load Current = 200mA VDCDC = 1.8V Mode = VINDCDC VINDCDC = 3.6V to 4.2V to 3.6V Temperature = 25°C VINDCDC VDCDC VDCDC DCDC Load Current = 75mA VDCDC = 1.8V Mode = GND DCDC Load DCDC Load Time - 100 ms/div Time - 100 ms/div Figure 8. Line transient response DCDC 1.8V (PWM) Figure 9. Line transient response DCDC 1.8V (PFM) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 9 TPS657052 TPS657051 SLVSA08 – FEBRUARY 2010 www.ti.com VINDCDC = 5.0V Temperature = 25°C VINDCDC = 5.0V VINLDO = 3.6V to 4.2V to 3.6V Temperature = 25°C DCDC Load Current = 20mA to 180mA VDCDC = 1.8V Mode = GND VINLDO LDO Load Current = 200mA VLDO = 2.8V VLDO VDCDC LDO Load DCDC Load Current Time - 100 ms/div Time - 100 ms/div Figure 10. Line Transient Response LDO 2.8V Figure 11. Load Transient Reponse DCDC 1.8V (PWM/PFM) 20mA to 180mA VINDCDC = 5.0V Temperature = 25°C VINDCDC = 5.0V Temperature = 25°C DCDC Load Current = 20mA to 360mA VDCDC = 1.8V Mode = GND VDCDC DCDC Load Current = 20mA to 180mA VDCDC = 1.8V Mode = VINDCDC VDCDC DCDC Load Current DCDC Load Current Time - 100 ms/div Time - 100 ms/div Figure 12. Load transient reponse DCDC 1.8V (PWM) 20mA to 180mA 10 Figure 13. Load transient reponse DCDC 1.8V (PFM/PWM) 20mA to 360mA Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 TPS657052 TPS657051 www.ti.com SLVSA08 – FEBRUARY 2010 VINDCDC = 5 V, VINLDO = 5 V Temperature = 25°C VINDCDC = 5.0V Temperature = 25°C LDO Load Current = 20 mA to 180 mA VLDO VINDCDC = 5.0 V VINLDO = 5.0 V Temperature = 25°C VDCDC DCDC Load Current = 20mA to 360mA VDCDC = 1.8V Mode = VINDCDC LDO Load Current = 20mA to 180mA VLDO = 2.8V VLDO = 2.8 V LDO Load Current DCDC Load Current Time - 100 ms/div Time - 100 ms/div Figure 14. Load transient reponse DCDC 1.8V (PWM) 20mA to 360mA Mode VINDCDC = 5.0V Temperature = 25°C VDCDC DCDC Load Current = 10mA VDCDC = 1.8V Mode = GND to VINDCDC Figure 15. Load Transient Reponse LDO Mode VINDCDC = 5.0V Temperature = 25°C VDCDC SW SW DCDC Load Current = 10mA VDCDC = 1.8V Mode = VINDCDC to GND DCDC Inductor Current DCDC Inductor Current Time - 10 ms/div Time - 10 ms/div Figure 16. DCDC PFM to PWM Mode Transition Figure 17. DCDC PWM to PFM Mode Transition Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 11 TPS657052 TPS657051 SLVSA08 – FEBRUARY 2010 www.ti.com VINDCDC = 5.0V Temperature = 25°C VINDCDC = 5.0V Temperature = 25°C DCDC Output DCDC Load Current = 200mA VDCDC = 1.8V Mode = GND DCDC Load Current = 60mA VDCDC = 1.8V Mode = GND DCDC Output SW SW DCDC Inductor Current DCDC Inductor Current Time - 2 ms/div Time - 1 ms/div Figure 18. DCDC Output Voltage Ripple in PFM Mode Figure 19. DCDC Output Voltage Ripple in PWM Mode VINDCDC = 5.0V Temperature = 25°C VDCDC = 1.8V EN EN VDCDC VINDCDC = 5.0V VINLDO = 5.0V Temperature = 25°C VLDO VLDO = 2.8V SW LDO Input Current DCDC Input Current Time - 80 ms/div Time - 80 ms/div Figure 20. Startup Timing DCDC 12 Figure 21. Startup Timing LDO Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 TPS657052 TPS657051 www.ti.com SLVSA08 – FEBRUARY 2010 100 LDO VO = 2.8 V, Load = 100 mA, VI = 5 V PSRR 90 Rejection Ratio - dB 80 70 60 IO = 100 mA 50 40 30 20 10 0 10 100 1k 10k 100k f - Frequency - Hz 1M 10M Figure 22. LDO PSRR 60 Quiescent Current - μA 50 Vout = 1.2V, Mode = GND ENDCDC1 = VINDCDC, no load ENDCDC2 = GND ENLDO = GND 25°C 85°C -40°C 40 30 20 10 0 2.5 3 3.5 4 4.5 5 VCC - Supply Voltage - V 5.5 6 Figure 23. DCDC Quiescent Current Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 13 TPS657052 TPS657051 SLVSA08 – FEBRUARY 2010 www.ti.com 100 Vout = 1.2V Mode = GND ENDCDC1 = GND ENDCDC2 = GND ENLDO =VINDCDC, no load 90 Quiescent Current - μA 80 70 60 50 85°C 25°C 40 30 20 -40°C 10 0 2.92 3.42 3.92 4.42 4.92 5.42 VCC - Supply Voltage - V 5.92 Figure 24. LDO Quiescent Current 30 Shutdown Current - μA 25 Vout = 1.2V Mode = GND ENDCDC1 = GND ENDCDC2 = GND ENLDO = GND 20 85°C 25°C -40°C 15 10 5 0 2.5 3 3.5 4 4.5 5 VCC - Supply Voltage - V 5.5 6 Figure 25. Shutdown Current 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 TPS657052 TPS657051 www.ti.com SLVSA08 – FEBRUARY 2010 DETAILED DESCRIPTION DCDC CONVERTER The TPS6570521/52 step down converter operates with typically 2.25 MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. With MODE pin set to low, at light load currents the converter can automatically enter Power Save Mode and operates then in PFM mode. During PWM operation the converter use a unique fast response voltage mode control scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the High Side MOSFET switch is turned on. The current flows now from the input capacitor via the High Side MOSFET switch through the inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the control logic will turn off the switch. The current limit comparator will also turn off the switch in case the current limit of the High Side MOSFET switch is exceeded. After an off time preventing shoot through current, the Low Side MOSFET rectifier is turned on and the inductor current will ramp down. The current flows now from the inductor to the output capacitor and to the load. It returns back to the inductor through the Low Side MOSFET rectifier. The next cycle will be initiated by the clock signal again turning off the Low Side MOSFET rectifier and turning on the on the High Side MOSFET switch. The DCDC1 converter output voltage is set to 3.3V and the DCDC2 converter output voltage is set to 1.8V per default. A 180° phase shift between DCDC1 and DCDC 2 decreases the input RMS current and synchronizes the operation of the two DCDC converts. The FB pin must be directly connected to the output voltage of DCDC and no external resistor network must be connected. POWER SAVE MODE The Power Save Mode is enabled with Mode Pin set to low. If the load current decreases, the converter will enter Power Save Mode operation automatically. During Power Save Mode the converter skips switching and operates with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The converter will position the output voltage typically +1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step. The transition from PWM mode to PFM mode occurs once the inductor current in the Low Side MOSFET switch becomes zero, which indicates discontinuous conduction mode. During the Power Save Mode the output voltage is monitored with a PFM comparator. As the output voltage falls below the PFM comparator threshold of VOUT nominal +1%, the device starts a PFM current pulse. The High Side MOSFET switch will turn on, and the inductor current ramps up. After the On-time expires, the switch is turned off and the Low Side MOSFET switch is turned on until the inductor current becomes zero. The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered current, the output voltage will rise. If the output voltage is equal or higher than the PFM comparator threshold, the device stops switching and enters a sleep mode with typical 25µA current consumption. If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses are generated until the PFM comparator threshold is reached. The converter starts switching again once the output voltage drops below the PFM comparator threshold. With a fast single threshold comparator, the output voltage ripple during PFM mode operation can be kept small. The PFM Pulse is time controlled, which allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value. Increasing output capacitor values and inductor values will minimize the output ripple. The PFM frequency decreases with smaller inductor values and increases with larger values. The PFM mode is left and PWM mode is entered in case the output current can not longer be supported in PFM mode. The Power Save Mode can be disabled by setting Mode pin to high. The converter will then operate in fixed frequency PWM mode. Dynamic Voltage Positioning This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is active in Power Save Mode and regulates the output voltage 1% higher than the nominal value. This provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 15 TPS657052 TPS657051 SLVSA08 – FEBRUARY 2010 www.ti.com Soft Start The step-down converter in TPS657051/52 has an internal soft start circuit that controls the ramp up of the output voltage. The output voltage ramps up from 5% to 95% of its nominal value within typical 250s. This limits the inrush current in the converter during ramp up and prevents possible input voltage drops when a battery or high impedance power source is used. EN 95% 5% VOUT tStart tRAMP Figure 26. Soft Start 100% Duty Cycle Low Dropout Operation The device starts to enter 100% duty cycle mode once the input voltage comes close to the nominal output voltage. In order to maintain the output voltage, the High Side MOSFET switch is turned on 100% for one or more cycles. With further decreasing VIN the High Side MOSFET switch is turned on completely. In this case the converter offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: VINmin = VOmax + IOmax (RDS(on)max + RL) With: IOmax = maximum output current plus inductor ripple current RDS(on)max = maximum high side switch RDSon. RL = DC resistance of the inductor VOmax = nominal output voltage plus maximum output voltage tolerance 180° OUT-OF-PHASE OPERATION In PWM Mode the converters operate with a 180° turn-on phase shift of the PMOS (high side) transistors. This prevents the high-side switches of both converters from being turned on simultaneously, and therefore smooths the input current. This feature reduces the surge current drawn from the supply. 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 TPS657052 TPS657051 www.ti.com SLVSA08 – FEBRUARY 2010 Under-Voltage Lockout The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery and disables the converters and LDOs. The under-voltage lockout threshold is typically 2.2V. SHORT-CIRCUIT PROTECTION All outputs are short circuit protected with a maximum output current as defined in the electrical specifications. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds typically 150°C for the DCDC converter or LDO, the device goes into thermal shutdown. In this mode, the low side and high side MOSFETs are turned-off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown for the LDO or the DCDC converter will disable both power supplies simultaneously. LDO The low dropout voltage regulator is designed to operate well with low value ceramic input and output capacitors. It operates with input voltages down to 1.7V. The LDO offers a maximum dropout voltage of 200mV at rated output current. The LDO supports a current limit feature. ENABLE FOR DCDC1, DCDC2 AND LDO Disabling the DCDC converter or LDO, forces the device into shutdown, with a shutdown quiescent current as defined in the electrical characteristics. In this mode, the power FETs are turned-off and the entire internal control circuitry is switched-off. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 17 TPS657052 TPS657051 SLVSA08 – FEBRUARY 2010 www.ti.com APPLICATION INFORMATION OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) Inductor selection The converter operates typically with 2.2µH output inductor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductor will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency. Equation 1 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 1. This is recommended because during heavy load transient the inductor current will rise above the calculated value. Vout 1Vin ΔIL = Vout ´ L ´ ¦ (1) ILmax =Ioutmax + DIL 2 (2) With: f = Switching Frequency (2.25MHz typical) L = Inductor Value ΔIL = Peak to Peak inductor ripple current ILmax = Maximum Inductor current The highest inductor current will occur at maximum Vin. Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. It must be considered, that the core material from inductor to inductor differs and will have an impact on the efficiency especially at high switching frequencies. Notice that the step down converter has internal loop compensation. As the internal loop compensation is designed to work with a certain output filter corner frequency calculated as follows: 1 ¦c = with L = 2.2 m H, Cout = 10 m F 2 p L ´ Cout (3) This leads to the fact the selection of external L-C filter has to be coped with the above formula. As a general rule of thumb the product of LxCout should be constant while selecting smaller inductor or increasing output capacitor value. Refer to Table 1 and the typical applications for possible inductors. Table 1. Tested Inductors 18 INDUCTOR TYPE INDUCTOR VALUE SUPPLIER BRC1608 1.5 µH Taiyo Yuden MLP2012 2.2 µH TDK MIPSA2520 2.2 µH FDK LPS3015 2.2 µH Coilcraft LQM21P 2.2 µH Murata Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 TPS657052 TPS657051 www.ti.com SLVSA08 – FEBRUARY 2010 Output Capacitor Selection The advanced Fast Response voltage mode control scheme of the step-down converter allows the use of small ceramic capacitors with a typical value of 10µF, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple and are therefore recommended. For an inductor value of 2.2µH, an output capacitor with 10µF can be used. Refer to recommended components. If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application requirements. Just for completeness the RMS ripple current is calculated as: Vout 11 Vin ´ IRMSCout = Vout ´ L ´ ¦ 2 ´ 3 (4) At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: Vout 1ö 1 Vin ´ æ DVout = Vout ´ + ESR ÷ ç L ´ ¦ è 8 ´ Cout ´ ¦ ø (5) Where the highest output voltage ripple occurs at the highest input voltage Vin. At light load currents the converter operates in Power Save Mode and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. The converters need a ceramic input capacitor of 10µF. The input capacitor can be increased without any limit for better input voltage filtering. Table 2. Tested Capacitors TYPE COMPONENT SUPPLIER VALUE VOLTAGE RATING SIZE MATERIAL DCDC Output Cap Murata GRM155R60G475ME47D 4.7 µF 4V 0402 Ceramic X5R LDO Input/Output Cap Murata GRM155R60J225ME15D 2.2 µF 6.3 V 0402 Ceramic X5R DCDC Output Cap Murata GRM188R60J475K 4.7 µF 6.3 V 0603 Ceramic X5R DCDC Input/Output Cap Murata GRM188R60J106M69D 10 µF 6.3 V 0603 Ceramic X5R Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 19 PACKAGE OPTION ADDENDUM www.ti.com 1-Mar-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS657051YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS657051YZHT ACTIVE DSBGA YZH 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS657052YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS657052YZHT ACTIVE DSBGA YZH 16 250 SNAGCU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS657051YZHR DSBGA YZH 16 3000 180.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.18 2.18 0.81 4.0 8.0 Q1 TPS657051YZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 TPS657052YZHR DSBGA YZH 16 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 TPS657052YZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS657051YZHR DSBGA YZH 16 3000 190.5 212.7 31.8 TPS657051YZHT DSBGA YZH 16 250 190.5 212.7 31.8 TPS657052YZHR DSBGA YZH 16 3000 190.5 212.7 31.8 TPS657052YZHT DSBGA YZH 16 250 190.5 212.7 31.8 Pack Materials-Page 2 X: Max = 2086 µm, Min = 1986 µm Y: Max = 2086 µm, Min = 1986 µm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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