DRV8835 www.ti.com SLVSB18A – MARCH 2012 – REVISED APRIL 2012 DUAL LOW VOLTAGE H-BRIDGE IC Check for Samples: DRV8835 FEATURES 1 • 2 • • • • • • • Dual-H-Bridge Motor Driver – Capable of Driving Two DC Motors or One Stepper Motor – Low MOSFET On-Resistance: HS + LS 305 mΩ 1.5-A Maximum Drive Current Per H-Bridge Bridges May Be Paralleled for 3-A Drive Current 2-V to 11-V Motor Operating Supply Voltage Range Separate Logic and Motor Power Supply Pins Flexible PWM or PHASE/ENABLE Interface Low-Power Sleep Mode With 95-nA Maximum Supply Current Tiny 2-mm x 3-mm WSON Package APPLICATIONS • Battery-Powered: – Cameras – DSLR Lenses – Consumer Products – Toys – Robotics – Medical Devices DESCRIPTION The DRV8835 provides an integrated motor driver solution for cameras, consumer products, toys, and other lowvoltage or battery-powered motion control applications. The device has two H-bridge drivers, and can drive two DC motors or one stepper motor, as well as other devices like solenoids. The output driver block for each consists of N-channel power MOSFET’s configured as an H-bridge to drive the motor winding. An internal charge pump generates needed gate drive voltages. The DRV8835 can supply up to 1.5-A of output current per H-bridge. It operates on a motor power supply voltage from 2 V to 11 V, and a device power supply voltage of 2 V to 7 V. PHASE/ENABLE and IN/IN interfaces can be selected which are compatible with industry-standard devices. Internal shutdown functions are provided for over current protection, short circuit protection, under voltage lockout and overtemperature. The DRV8835 is packaged in a tiny 12-pin WSON package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br). ORDERING INFORMATION (1) PACKAGE (2) PowerPAD™ (WSON) - DSS (1) (2) Reel of 3000 ORDERABLE PART NUMBER TOP-SIDE MARKING DRV8835DSSR 835 For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated DRV8835 SLVSB18A – MARCH 2012 – REVISED APRIL 2012 www.ti.com DEVICE INFORMATION Functional Block Diagram 2.0 to 11V VM VM VM Drives 2x DC motor or 1x Stepper Gate Drive Charge Pump OCP AOUT1 2.0 to 7 V Step Motor VCC DCM VCC VM AOUT2 Gate Drive OCP AIN1/APHASE AIN2/AENBL Logic VM BIN1/BPHASE Gate Drive BIN2/BENBL OCP BOUT1 DCM MODE VM OverTemp Gate Drive OCP BOUT2 Osc GND 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8835 DRV8835 www.ti.com SLVSB18A – MARCH 2012 – REVISED APRIL 2012 Table 1. TERMINAL FUNCTIONS NAME PIN I/O (1) EXTERNAL COMPONENTS OR CONNECTIONS DESCRIPTION POWER AND GROUND GND 6 - Device ground VM 1 - Motor supply Bypass to GND with a 0.1-μF (minimum) ceramic capacitor. VCC 12 - Device supply Bypass to GND with a 0.1-μF (minimum) ceramic capacitor. MODE 11 I Input mode select Logic low selects IN/IN mode. Logic high selects PH/EN mode. Internal pulldown resistor. AIN1/APHASE 10 I Bridge A input 1/PHASE input IN/IN mode: Logic high sets AOUT1 high. PH/EN mode: Sets direction of H-bridge A. Internal pulldown resistor. AIN2/AENBL 9 I Bridge A input 2/ENABLE input IN/IN mode: Logic high sets AOUT2 high. PH/EN mode: Logic high enables H-bridge A. Internal pulldown resistor. BIN1/BPHASE 8 I Bridge B input 1/PHASE input IN/IN mode: Logic high sets BOUT1 high. PH/EN mode: Sets direction of H-bridge B. Internal pulldown resistor. BIN2/BENBL 7 I Bridge B input 2/ENABLE input IN/IN mode: Logic high sets BOUT2 high. PH/EN mode: Logic high enables H-bridge B. Internal pulldown resistor. AOUT1 2 O Bridge A output 1 AOUT2 3 O Bridge A output 2 BOUT1 4 O Bridge B output 1 BOUT2 5 O Bridge B output 2 CONTROL OUTPUT (1) Connect to motor winding A Connect to motor winding B Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output DSS PACKAGE (TOP VIEW) VM AOUT1 AOUT2 BOUT1 BOUT2 GND 1 12 2 11 3 4 GND (PPAD ) 10 9 5 8 6 7 VCC MODE AIN1 / APHASE AIN2 / AENBL BIN1 / BPHASE BIN2 / BENBL Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8835 3 DRV8835 SLVSB18A – MARCH 2012 – REVISED APRIL 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) VALUE UNIT VM Power supply voltage range –0.3 to 12 V VCC Power supply voltage range -0.3 to 7 V –0.5 to VCC + 0.5 V Internally limited A Digital input pin voltage range Peak motor drive output current Continuous motor drive output current per H-bridge (3) 1.5 A TJ Operating junction temperature range –40 to 150 °C Tstg Storage temperature range –60 to 150 °C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Power dissipation and thermal limits must be observed. THERMAL INFORMATION DRV8835 THERMAL METRIC DSS UNITS 12 PINS θJA Junction-to-ambient thermal resistance (1) θJCtop Junction-to-case (top) thermal resistance (2) θJB Junction-to-board thermal resistance (3) 19.9 ψJT Junction-to-top characterization parameter (4) 0.9 ψJB Junction-to-board characterization parameter (5) 20 θJCbot Junction-to-case (bottom) thermal resistance (6) 6.9 50.4 58 °C/W xxx (1) (2) (3) (4) (5) (6) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. RECOMMENDED OPERATING CONDITIONS TA = 25°C (unless otherwise noted) MIN VCC Device power supply voltage range 2 VM Motor power supply voltage range IOUT H-bridge output current (1) fPWM VIN (1) 4 NOM MAX UNIT 7 V 2 11 V 0 1.5 A Externally applied PWM frequency 0 250 kHz Logic level input voltage 0 VCC V Power dissipation and thermal limits must be observed. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8835 DRV8835 www.ti.com SLVSB18A – MARCH 2012 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS TA = 25°C, VM = 5 V, VCC = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 85 200 µA 650 2000 µA POWER SUPPLY IVM VM operating supply current IVMQ VM sleep mode supply current IVCC VCC operating supply current VUVLO VCC undervoltage lockout voltage No PWM, no load 50 kHz PWM, no load VM = 2 V, VCC = 0 V, all inputs 0 V 5 VM = 5 V, VCC = 0 V, all inputs 0 V 10 95 450 2000 VCC rising 2 VCC falling 1.9 nA µA V LOGIC-LEVEL INPUTS VIL Input low voltage 0.25 x VCC 0.38 x VCC VIH Input high voltage 0.46 x VCC VHYS Input hysteresis 0.08 x VCC IIL Input low current VIN = 0 IIH Input high current VIN = 3.3 V RPD Pulldown resistance -5 V 0.5 x VCC V 5 μA 50 μA V 100 kΩ H-BRIDGE FETS RDS(ON) IOFF HS + LS FET on resistance VCC = 3 V, VM = 3 V, I O = 800 mA, TJ = 25°C 370 420 VCC = 5 V, VM = 5 V, I O = 800 mA, TJ = 25°C 305 355 mΩ Off-state leakage current ±200 nA PROTECTION CIRCUITS IOCP Overcurrent protection trip level tTSD Thermal shutdown temperature 1.6 Die temperature 150 160 3.5 A 180 °C Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8835 5 DRV8835 SLVSB18A – MARCH 2012 – REVISED APRIL 2012 www.ti.com TIMING REQUIREMENTS TA = 25°C, VM = 5 V, VCC = 3 V, RL = 20 Ω NO. PARAMETER CONDITIONS MIN MAX UNIT 1 t1 Delay time, xPHASE high to xOUT1 low 300 ns 2 t2 Delay time, xPHASE high to xOUT2 high 200 ns 3 t3 Delay time, xPHASE low to xOUT1 high 200 ns 4 t4 Delay time, xPHASE low to xOUT2 low 300 ns 5 t5 Delay time, xENBL high to xOUTx high 200 ns 6 t6 Delay time, xENBL high to xOUTx low 300 ns 7 t7 Output enable time 300 ns 8 t8 Output disable time 300 ns 9 t9 Delay time, xINx high to xOUTx high 160 ns 10 t10 Delay time, xINx low to xOUTx low 160 ns 11 tR Output rise time 30 188 ns 12 tF Output fall time 30 188 ns xENBL IN1 xPHASE IN2 7 9 8 3 5 OUT1 xOUT1 z z 10 1 xOUT2 6 5 2 4 6 OUT2 z z IN/IN mode PHASE/ENBL mode 80% 80% OUTx 20% 20% 11 6 Submit Documentation Feedback 12 Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8835 DRV8835 www.ti.com SLVSB18A – MARCH 2012 – REVISED APRIL 2012 FUNCTIONAL DESCRIPTION Bridge Control Two control modes are available in the DRV8835: IN/IN mode, and PHASE/ENABLE mode. IN/IN mode is selected if the MODE pin is driven low or left unconnected; PHASE/ENABLE mode is selected if the MODE pin is driven to logic high. The following tables show the logic for these modes. Table 2. IN/IN MODE MODE xIN1 xIN2 xOUT1 xOUT2 FUNCTION (DC MOTOR) 0 0 0 Z Z Coast 0 0 1 L H Reverse 0 1 0 H L Forward 0 1 1 L L Brake Table 3. PHASE/ENABLE MODE MODE xENABLE xPHASE xOUT1 xOUT2 FUNCTION (DC MOTOR) 1 0 X L L Brake 1 1 1 L H Reverse 1 1 0 H L Forward Sleep Mode If the VCC pin is brought to 0 volts, the DRV8835 will enter a low-power sleep mode. In this state all unnecessary internal circuitry is powered down. For minimum supply current, all inputs should be low (0 V) during sleep mode. Power Supplies and Input Pins There is a weak pulldown resistor (approximately 100 kΩ) to ground on the input pins. VCC and VM may be applied and removed in any order. When VCC is removed, the device will enter a low power state and draw very little current from VM. The input pins should be kept at 0 V during sleep mode to minimize current draw. Protection Circuits The DRV8835 is fully protected against undervoltage, overcurrent and overtemperature events. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled. After approximately 1 ms, the bridge will be re-enabled automatically. Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled . Once the die temperature has fallen to a safe level operation will automatically resume. Undervoltage Lockout (UVLO) If at any time the voltage on the VCC pins falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled, and internal logic will be reset. Operation will resume when VCC rises above the UVLO threshold. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8835 7 DRV8835 SLVSB18A – MARCH 2012 – REVISED APRIL 2012 www.ti.com APPLICATIONS INFORMATION Parallel Mode The two H-bridges in the DRV8835 can be connected in parallel for double the current of a single H-bridge. The drawing below shows the connections. Figure 1. Parallel Mode Connections 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8835 DRV8835 www.ti.com SLVSB18A – MARCH 2012 – REVISED APRIL 2012 THERMAL INFORMATION Thermal Protection The DRV8835 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation Power dissipation in the DRV8835 is dominated by the power dissipated in the output FET resistance, or RDS(ON). Average power dissipation when running both H-bridges can be roughly estimated by: PTOT = 2 x RDS(ON) x (IOUT(RMS))2 (1) Where PTOT is the total power dissipation, RDS(ON) is the resistance of the HS plus LS FETs, and IOUT(RMS) is the RMS output current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current setting. The factor of 2 comes from the fact that there are two H-bridges. The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8835 9 PACKAGE OPTION ADDENDUM www.ti.com 7-Apr-2012 PACKAGING INFORMATION Orderable Device DRV8835DSSR Status (1) ACTIVE Package Type Package Drawing SON DSS Pins Package Qty 12 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Apr-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8835DSSR Package Package Pins Type Drawing SON DSS 12 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 2.3 B0 (mm) K0 (mm) P1 (mm) 3.3 0.85 4.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Apr-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8835DSSR SON DSS 12 3000 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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