TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 • • • • • • • • • • High-Resolution, Solid-State Monochrome Image Sensor for Video or Still-Picture Photography Frame Transfer With Two Field Memories Allows Multimode Operation 1134 (H) x 486 (V) Active Elements in Image-Sensing Area 11-mm Image-Area Diagonal is Compatible With 2/3” Vidicon Optics Fast Clear Capability Electron-Hole Recombination Antiblooming Dynamic Range . . . More Than 60 dB High Photoresponse Uniformity On-Chip Cross-Coupled Resets for Easy Off-Chip Implementation of CCSH Video Signal Processing Solid-State Reliability With No Image Burn-in, Residual Imaging, Image Distortion, Image Lag, or Microphonics DUAL-IN-LINE PACKAGE (TOP VIEW) SUB 1 22 SUB ABG 2 21 TDB IAG 3 20 ABG SAG1 4 19 IAG ADB 5 18 TMG OUT3 6 17 SAG2 OUT2 7 16 SRG3 OUT1 8 15 SRG2 AMP GND 9 14 SRG1 CDB 10 13 TRG SUB 11 12 SUB description The TC217 is a frame-transfer charge-coupled-device (CCD) image sensor with two field memories. It is suitable for use in NTSC video or still-picture photography applications. Its image-sensing area is configured into 488 lines; 486 of these are active and the remaining two are used for dark reference. Each line is configured into 1158 pixels with 1134 active and 24 for dark reference. The TC217 has a standard aspect ratio of 4:3 and a standard 11-mm image-sensing-area diagonal. Its blooming protection, which is an integral part of each pixel, is based on electron-hole recombination and is activated by clocking the antiblooming gate. One important aspect of the TC217 high-resolution sensor is its ability to simultaneously capture both fields of a TV frame. Its two independently addressable memories allow separate storage of each field and operation in a variety of modes, including EIA-170 (formerly RS-170) with true interlace, EIA-170 with pseudointerlace, and nonstandard pseudointerlace with a resolution of 972 lines. A unique multiplexer section (see Figure 3) rearranges the horizontal pixels into vertical groups of three and separates and loads the image into the two field memories. The independent addressing of each field memory provides flexibility for different modes of operation. The interdigitated layout of the memories allows each memory to share the same bank of three serial registers and associated charge detection amplifiers (see Figure 4 and the functional block diagram). Each register and associated amplifier reads out every third column of the image area (see Figure 5). The three amplifiers are optimized dual source-followers that allow the use of off-chip double-correlated clamp-sample-and-hold amplifiers for removing KTC noise. The TC217 is built using TI-proprietary virtual-phase technology, which provides devices with high blue response, low dark signal, good uniformity, and single-phase clocking. The TC217 is characterized for operation from –10°C to 40°C. This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to SUB. Under no circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUTn to ADB during operation to prevent damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is allowed to flow. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 functional block diagram Top Drain 21 ABG 2 20 IAG 3 Image Area With Blooming Protection 19 TBD ABG IAG Dark Reference Elements 3:2 Multiplexer SAG1 ADB OUT3 18 5 Amplifiers 17 Storage Area 6 16 7 OUT2 15 14 OUT1 8 Transfer Gates and Serial Registers ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Clearing Drain 12 Dummy Elements 2 TMG 4 9 AMP GND 10 CDB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SAG2 SRG3 SRG2 SRG1 TRG TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 sensor topology diagram 1158 Pixels ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ 1134 Active Pixels 23 Dark Pixels 1/2 Dark Pixel 1/2 Dark Pixel 486 Active Lines 2 Dark Lines Multiplexer 732 Lines 12 386 12 386 12 386 Dummy Pixels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 Terminal Functions TERMINAL I/O DESCRIPTION NAME ABG† NO. 2 I Antiblooming gate ABG† 20 I Antiblooming gate ADB 5 I Supply voltage for amplifier drain bias AMP GND 9 CDB IAG† IAG† 10 I Supply voltage for clearing drain bias 3 I Image-area gate 19 I Image-area gate OUT1 8 O Output signal 1 OUT2 7 O Output signal 2 OUT3 6 O Output signal 3 SAG1 4 I Storage-area gate Amplifier ground SAG2 17 I Storage-area gate SRG1 14 I Serial-register gate 1 SRG2 15 I Serial-register gate 2 SRG3 SUB† 16 I Serial-register gate 3 1 Substrate and clock return SUB† SUB† 11 Substrate and clock return 12 Substrate and clock return SUB† 22 Substrate and clock return TDB 21 I Supply voltage for top drain bias TMG 18 I Transfer-multiplex gate TRG 13 I Transfer gate † All pins of the same name should be connected together externally (i.e., pin 2 to pin 20, pin 3 to pin 19, etc.). detailed description The TC217 consists of five basic functional blocks: (1) the image-sensing area, (2) the multiplexer block, (3) the image-storage area with dual field memories, (4) the serial register and transfer gates, and (5) the low-noise signal-processing amplifier block with charge-detection nodes. The location of each of these blocks is identified in the functional block diagram. image-sensing area Figure 1 and Figure 2 show cross sections with potential well diagrams and top views of image-sensing elements. As light enters the silicon in the image-sensing area, free electrons are generated and collected in the potential wells of the sensing elements. During this time, blooming protection is activated by applying a burst of pulses to the antiblooming gate inputs every horizontal blanking interval. This prevents blooming caused by the spilling of charge from overexposed elements into neighboring elements. There are 23 full columns and one half-column of elements at the right edge of the image-sensing area that are shielded from incident light; these elements provide the dark reference used in subsequent video processing circuits to restore the video black level. There are also one half-column of light-shielded elements at the left edge of the image-sensing area and two lines of light-shielded elements at the bottom of the image area immediately above the multiplexer (the latter prevent charge leakage from the image area into the multiplexer). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 multiplexer and storage area After integration, the multiplexer rearranges two horizontal lines into vertical groups of three and separates and loads the image into the storage area. Figure 3 shows the layout of the multiplexer gate and its interface to the two field memories. Figure 4 shows the interface region between the storage area and the three serial registers. A drain is also provided to clear the image-sensing and image-storage areas of unwanted charge. Such charge can accumulate in the imager during the startup of operation or under special circumstances when nonstandard TV operation is desired. The sensor’s independently addressable memories allow several different modes of sensor operation including (1) a normal-light mode, (2) a low-light mode, and (3) a still mode. The timing for these three modes is given in Figures 6, 7, and 8. The parallel-transfer timing is shown in Figure 9. serial registers and amplifiers After transfer to the serial registers (see Figure 10, which shows the horizontal timing that gives the necessary sequence of pulses for transfer from the storage area to the serial registers), the charge is converted to a signal voltage at the sense node and buffered with a dual-stage source follower. The three serial registers are typically clocked 120 degrees out of phase with each serial-gate pulse supplying a detection node reset signal for one of the other two serial gates. The readout timing, which includes the three serial pulses and the pixel clamp pulses used in an off-chip double-correlated sampling circuit, is shown in Figure 12. The detection nodes and amplifiers are located some distance away from the edge of the storage area. Therefore, 12 dummy elements are incorporated at the end of each serial register to span the distance. The location of the dummy elements, which are considered to be part of the amplifiers, is shown in the functional block diagram. A schematic of the detection node and amplifier is given in Figure 5. 7.8 µm(H) Light Clocked Barrier φ-IAG 13.6 µm(V) Virtual Barrier φ-ABG Antiblooming Clocking Levels Antiblooming Gate Virtual Well Clocked Well Accumulated Charge Figure 1. Charge-Accumulation Process φ-PS Clocked Phase Virtual Phase Channel Stops Figure 2. Charge-Transfer Process POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 7.8 µm Image Area 488 Lines Clocked Gate 13.6 µm Antiblooming Gate 5.8 µm Channel Stops Multiplexer Clocked Gate Clocked Wells Multiplexer Virtual Wells Clocked Gate Memory A Clocked Gate Memory B Metal Bus Lines for Memory A and B 9 µm 4.5 µm Memory Area 732 Lines 11.7 µm Figure 3. Layout of Multiplexing Gate 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 Contact Holes to Metal Bus Lines Memory Area 732 Lines Clocked Gates Memory A, B Channel Stop Channel Stop Common Virtual Well Clocked Gate Serial Register 1 Horizontal Register 1 Transfer Gate Clocked Gate Serial Register 2 Horizontal Register 2 Figure 4. Layout of the Interface Region Between the Memories and the Serial Registers POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 ADB VREF Q1 SRG1 Q2 Q3 q VO1 Q4 SRG2 Q5 Q6 q VO2 Q7 Q8 SRG3 Q9 q VO3 Figure 5. Circuit Diagram - Charge-Detection Amplifiers IAG TMG SAG1 SAG2 ABG TRG SRG1, SRG2, SRG3 Figure 6. Vertical Timing, Normal-Light Mode 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 IAG TMG SAG1 SAG2 ABG TRG SRG1, SRG2, SRG3 Figure 7. Vertical Timing, Low-Light Mode IAG TMG SAG1 SAG2 ABG TRG SRG1, SRG2, SRG3 Figure 8. Vertical Timing, Still Mode IAG TMG SAG1 SAG2 ABG TRG SRG1, SRG2, SRG3 Figure 9. Vertical Timing, Progressive-Scan Mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 ABG IAG TMG SAG1 SAG2 Figure 10. Parallel-Transfer Timing TRG SAG1, SAG2† SRG1, SRG2, SRG3 † These clocks are mode-dependent. Figure 11. Horizontal Timing Dummy Pixels 9 10 11 Image Pixels 12 375 376 377 Dark Pixels 378 5 SRG1 SRG2 SRG3 Figure 12. Start of Serial-Transfer Timing 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6 7 8 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 SRG1 OUT1 CL1 SH1 SRG2 OUT2 CL2 SH2 SRG3 OUT3 CL3 SH3 NOTES: A. The video-processing (off-chip) pulses are defined as follows: CL1 = Clamp pulse for video from OUT1 SH1 = Sample pulse for the sample-and-hold amplifier for video 1 CL2 = Clamp pulse for video from OUT2 SH2 = Sample pulse for the sample-and-hold amplifier for video 2 CL3 = Clamp pulse for video from OUT3 SH3 = Sample pulse for the sample-and-hold amplifier for video 3 B. The signals for channel (n +1) are phase shifted 120° from the signals for channel (n). For example, SRG2 is phase shifted 120° relative to SRG1, SRG3 is phase-shifted 120° relative to SRG2, OUT2 is phase shifted 120° relative to OUT1, OUT3 is phase shifted 120° relative to OUT2, and so forth. Figure 13. Video-Process Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 spurious nonuniformity specification The spurious nonuniformity specification of the TC217 CCD grades – 30 and – 40 is based on several sensor characteristics: • • • Amplitude of the nonuniform line or pixel Polarity of the nonuniform pixel – Black – White Column amplitude The CCD sensors are characterized in both an illuminated condition and a dark condition. In the dark condition, the nonuniformity is specified in terms of absolute amplitude as shown in Figure 14. In the illuminated condition, the nonuniformity is specified as a percentage of the total illumination as shown in Figure 15. The nonuniformity specification for the TC217 is as follows (CCD video-output signal is 50 mV ±10 mV): PIXEL NONUNIFORMITY PART NUMBER COLUMN NONUNIFORMITY DARK CONDITION ILLUMINATED CONDITION PIXEL AMPLITUDE, x (mV) % OF TOTAL ILLUMINATION TC217-30 x ≤ 12 mV x ≤ 10 x < 0.5 mV TC217-40 x ≤ 15 mV x ≤ 15 x ≤ 1 mV COLUMN AMPLITUDE, x (mV) mV Amplitude % of Total Illumination t Figure 14. Pixel Nonuniformity, Dark Condition 12 POST OFFICE BOX 655303 t Figure 15. Pixel Nonuniformity, Illuminated Condition • DALLAS, TEXAS 75265 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range for ADB, CDB, TDB (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 15 V Input voltage range for ABG, IAG, SAG1, SAG2, SRG1, SRG2, SRG3, TRG . . . . . . . . . . . . . –15 V to 15 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30°C to 85°C Storage temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30°C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the substrate terminal. recommended operating conditions Supply voltage for ADB, CDB, TDB MIN NOM MAX 11 12 13 Substrate bias voltage 0 IAG SAG1 SAG2 SAG1, SRG1 SRG2 SRG1, SRG2, SRG3 Input voltage, VI‡ TMG High level 2 Low level –11 High level 2 Low level –11 High level 2 Low level –11 High level 2 Low level –11 High level TRG Capacitive load 2.5 3 –9 2.5 3 –9 2.5 3 V –9 4.5 5 –2 – 1.55 –7.5 –7 – 6.5 High level 2 2.5 Low level –11 ABG Clock frequency, frequency fclock l k 3 –9 4 Low level V V – 2.85 Intermediate level§ ABG 2.5 UNIT 3 –9 1 IAG 1.2 SRG1, SRG2, SRG3, TRG 7.2 TMG, SAG1, SAG2 3.6 OUT1, OUT2, OUT3 8 MHz pF Operating free-air temperature, TA – 10 40 °C ‡ The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for clock voltage levels. § Adjustment is required for optimal performance. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 electrical characteristics over recommended operating ranges of supply voltage and free-air temperature PARAMETER Dynamic range (see Note 2) MIN TYP† 60 73 dB 6 µV/e Charge conversion factor Charge transfer efficiency (see Note 3) Signal response delay time, τ (see Note 4 and Figure 18) Gamma (see Note 5) Output resistance 1/f noise (5 kHz) Noise voltage MAX 0.9999 0.99995 18 20 0.89 0.94 0.99 600 1000 22 0.1 Random noise (f = 100 kHz) 15 Rejection ratio at 4.77 MHz ADB (see Note 6) 20 SRGn (see Note 7) 40 ABG (see Note 8) 30 Supply current 6 capacitance Ci Input capacitance, IAG 13000 SAG1, SAG2 11000 ABG 4100 TMG 150 TRG 200 ns Ω µV/√Hz 0.08 Noise equivalent signal UNIT electrons dB 9 mA pF SRG1, SRG2, SRG3 180 † All typical values are at TA = 25 °C NOTES: 2. Dynamic range is – 20 times the logarithm of the mean noise signal divided by the saturation output signal. It is measured using a correlated clamp-sample-and-hold circuit and with the image sensor’s antiblooming disabled. 3. Charge transfer efficiency is one minus the charge loss per transfer in the output register. The test is performed in the dark using an electrical input signal. 4. Signal-response delay time is the time between the falling edge of the SRG clock pulse and the output signal valid state. 5. Gamma (γ) is the value of the exponent in the equation below for two points on the linear portion of the transfer function curve: ǒ Ǔ +ǒ Exposure (2) Exposure (1) g Ǔ Output signal (2) Output signal (1) 6. ADB rejection ratio is – 20 times the logarithm of the ac amplitude on OUTn divided by the ac amplitude on ADB. 7. SRGn rejection ratio is – 20 times the logarithm of the ac amplitude on OUTn divided by the ac amplitude on SRGn. 8. ABG rejection ratio is – 20 times the logarithm of the ac amplitude on OUTn divided by the ac amplitude on ABG. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 optical characteristics, TA = 25°C, exposure time = 33 ms (unless otherwise noted) PARAMETER Sensitivity (see Notes 9 and 10) MIN 400 With IR filter 50 Saturation signal, Vsat (see Note 11) 320 Image-area well capacity Blooming overload ratio (see Note 12) TYP No IR filter Exposure time = 1/60 second 150 mV 60 x 103 electrons 200 VO = 1/2 VU (see Note 10) TA = 40°C TA = 40°C Dark signal uniformity NOTES: 9. 10. 11. 12. 13. 14. 15. mV/lx 0.0012 Dark signal (see Note 15) Dark current UNIT 410 Smear (see Notes 13 and 14) Output signal uniformity MAX 5 1 mV 6 mV 0.3 mV TA = 21°C 0.027 nA/cm2 Sensitivity is measured at any illumination level that gives an output voltage level less than VU. A CM-500 filter is used. VU is the output voltage that represents the threshold of operation of antiblooming. VU ≈ 1/2 saturation signal. Saturation is the condition in which further increase in exposure does not lead to further increase in output signal. Blooming is the condition in which charge is induced in an element by light incident on another element. Blooming overload ratio is the ratio of blooming exposure to saturation exposure. Smear is the measure of error induced by transferring charge through an illuminated pixel in shutterless operation. It is equivalent to the ratio of the single-pixel transfer time during a fast dump to the exposure time using an illuminated section that is 1/10 of the image area vertical height with recommended clock frequencies. The fast-dump clocking rate during vertical timing is 1.2 MHz, and the illuminated section is 1/10 of the height of the image section. Dark-signal level is measured from the dark dummy pixels. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 PARAMETER MEASUREMENT INFORMATION Blooming Point With Antiblooming Enabled VO Blooming Point With Antiblooming Disabled Dependent on Well Capacity Vsat (min) Level Dependent Upon Antiblooming Gate High Level Vuse (max) Vuse (typ) DR Vn Lux (light input) DR (dynamic range) + camera whiteVn clip voltage Vn = noise floor voltage Vsat (min) = minimum saturation voltage Vuse (max) = maximum usable voltage Vuse (typ) = typical user voltage (camera white clip) NOTES: A. Vuse (typ) is defined as the voltage determined to equal the camera white clip. This voltage must be less than Vuse (max). B. A system trade-off is necessary to determine the system light sensitivity versus the signal/noise ratio. By lowering the Vuse (typ), the light sensitivity of the camera is increased; however, this sacrifices the signal/noise ratio of the camera. Figure 16. Typical Vsat, Vuse Relationship 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 PARAMETER MEASUREMENT INFORMATION 100% VIH min 90% Intermediate Level 10% VIL max 0% tf tr Slew rate between 10% and 90% = 70 to 120 V/µs, tr = 150 ns, tf = 90 ns Figure 17. Typical Clock Waveform for ABG, IAG, SAG1, SAG2, AND TMG VIH min 100% 90% 10% VIL max 0% tf tr Slew rate between 10% and 90% = 300 V/µs, tr = tf = 15 ns Figure 18. Typical Clock Waveform for SRG1, SRG2, SRG3, and TRG 1.5 V to 2.5 V SRG –9V – 9 V to – 11 V 0% OUT 90% 100% CCD Delay τ 10 ns 15 ns Sample and Hold Figure 19. SRG and OUT Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 APPLICATION INFORMATION OUT GND VCC GND VCC VSS V TMS3473B Master Oscillator V CLK CBLNK PC3 PC2 PC1 CSYNC SH3 SH2 SH1 MEMB TMG CBLNK MEMA PC3 IAG PC2 ABG PC1 GT CSYNC SRG3 SH3 SRG2 SRG1 SH2 TRG SH1 VCC 1 2 3 4 5 6 7 8 9 10 VSS IASR ABSR VCC ABLVL IAOUT ABOUT SAOUT VCC VABG – IALVL I/N IAIN ABIN MIDSEL SAIN PD GND VABG+ VSS 20 47 kΩ 19 18 17 16 15 14 13 12 11 20 kΩ 12 V 100 Ω Parallel Driver OUT 3 2N3904 1 kΩ User-Defined Timer 12 V TMS3473B IALVL DC VOLTAGES VCC 5V VSS –10 V V 2V ABLVL –1.5 V VABG + 4V VABG – –6 V –5 V IALVL VCC 1 2 3 4 5 6 7 8 9 10 VSS IASR ABSR VCC ABLVL IAOUT ABOUT SAOUT VCC VABG – IALVL I/N IAIN ABIN MIDSEL SAIN PD GND VABG+ VSS 20 19 18 17 16 15 14 13 12 11 47 kΩ 100 Ω 20 kΩ 2N3904 TC217 VABG – VABG + SN28846 VCC SEL0OUT GND PD SRG3IN SRG2IN SRG1IN TRGIN NC SEL1OUT VSS VSS SEL0 NC VCC SRG3OUT SRG2OUT SRG1OUT TRGOUT VCC SEL1 1 kΩ ABLVL Parallel Driver 1 2 3 4 5 6 7 8 9 10 OUT 2 20 19 18 17 16 15 14 13 12 11 12 V 1 2 3 4 5 6 7 8 9 10 11 SUB ABG IAG SAG1 ADB OUT3 OUT2 OUT1 AMP GND CDB SUB SUB TDB ABG IAG TMG SAG2 SRG3 SRG2 SRG1 TRG SUB 22 21 20 19 18 17 16 15 14 13 12 Image Sensor 12 V Serial Driver 100 Ω 2N3904 OUT 1 1 kΩ SUPPORT CIRCUITS DEVICE PACKAGE SN28846DW 20 pin small outline APPLICATION Serial driver Driver for SRG1, SRG2, SRG3, and TRG FUNCTION TMS3473BDW 20 pin small outline Parallel driver Driver for IAG, SAG1, SAG2, ABG, and TMG Figure 20. Typical Application Circuit Diagram 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12 V TC217 1158- × 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 MECHANICAL DATA The package for the TC217 consists of a ceramic base, a glass window, and a 22-lead frame. The package leads are configured in a dual in-line organization and fit into mounting holes with 2.54 mm (0.10 inch) center-to-center spacings. The glass window is sealed to the package by an epoxy adhesive. It can be cleaned by any standard procedure for cleaning optical assemblies or by wiping the surface with a cotton swab moistened with alcohol. 23,39 (0.921) Optical Center 2,01 x 2,39 (0.079 x 0.094) 2,01 (0.079) Optical C L (see Note B) 18,24 (0.718) 9,35 (0.368) REF 8,00 (0.315) Index Dot 27,81 (1.095) MAX 18,54 MAX (0.730) 3,86 (0.152) MAX 0,25 (0.010) 2,21 (0.087) 0,46 (0.018) 10,16 (0.400) TYP 2,54 (0.100) 5,50 ± 0,76 (0.217 ± 0.030) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES 7/94 NOTES: A. Single dimensions are nominal. B. The center of the package and the center of the image area are not coincident. C. The distance from the top of the glass to the image sensor surface is typically 1,46 mm (0.057 inch). The glass is 0,95 ±0,08 mm and has an index of refraction of 1.53. D. Each pin centerline is located within 0,25 mm (0.010 inch) of its true longitudinal position. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 488-PIXEL CCD IMAGE SENSOR SOCS015C – OCTOBER 1989 – REVISED JUNE 1996 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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