TI SN65HVD251

SN65HVD251
www.ti.com
SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
CAN TRANSCEIVER
FEATURES
•
•
•
•
•
•
•
•
•
Drop-In Improved Replacement for the
PCA82C250 and PCA82C251
Bus-Fault Protection of ±36 V
Meets or Exceeds ISO 11898
Signaling Rates(1) up to 1 Mbps
High Input Impedance Allows up to 120
SN65HVD251 Nodes on a Bus
Bus Pin ESD Protection Exceeds 14 kV HBM
Unpowered Node Does Not Disturb the Bus
Low Current Standby Mode . . . 200 µA Typical
Thermal Shutdown Protection
•
•
Glitch-Free Power-Up and Power-Down Bus
Protection For Hot-Plugging
DeviceNet Vendor ID # 806
APPLICATIONS
•
•
•
•
•
CAN Data Buses
Industrial Automation
– DeviceNet™ Data Buses
– Smart Distributed Systems (SDS™)
SAE J1939 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
ISO 11783 Standard Data Bus Interface
DESCRIPTION
The SN65HVD251 is intended for use in applications employing the Controller Area Network (CAN) serial
communication physical layer in accordance with the ISO 11898 Standard. The SN65HVD251 provides
differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1
megabits per second (Mbps).
Designed for operation in harsh environments, the device features cross-wire, over-voltage and loss of ground
protection to ±36 V. Also featured are over-temperature protection as well as -7 V to 12 V common-mode range,
and tolerance to transients of ± 200 V. The transceiver interfaces the single-ended CAN controller with the
differential CAN bus found in industrial, building automation, and automotive applications.
Rs, pin 8, provides for three different modes of operation: high-speed, slope control, or low-power mode. The
high-speed mode of operation is selected by connecting pin 8 to ground, allowing the transmitter output
transistors to switch as fast as possible with no limitation on the rise and fall slope. The rise and fall slope can be
adjusted by connecting a resistor to ground at pin 8; the slope is proportional to the pin's output current. Slope
control with an external resistor value of 10 kΩ gives ~ 15 V/us slew rate; 100 kΩ gives ~ 2 V/us slew rate.
If a high logic level is applied to the Rs pin 8, the device enters a low-current standby mode during which the
driver is switched off and the receiver remains active . The local protocol controller reverses this low-current
standby mode when it needs to transmit to the bus.
The SN65HVD251 may be used in CAN, DeviceNet™ or SDS™ applications with the Texas Instruments'
TMS320F241 and TMS320F243 DSPs with CAN 2.0B controllers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DeviceNet is a trademark of Allen-Bradley.
SDS is a trademark of Honeywell.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2003, Texas Instruments Incorporated
SN65HVD251
www.ti.com
SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
function diagram
(positive logic)
VCC
D
GND
1
8
Rs
2
7
Vcc
3
4
6
5
CANH
CANL
Vref
R
(1)
(1)The
5 V
ref
1
D
RS 8
R
(1)
3
7
CANH
6 CANL
4
ORDERING INFORMATION
PART NUMBER
PACKAGE
MARKED AS
SN65HVD251D
8-pin SOIC (Tube)
VP251
SN65HVD251DR
8-pin SOIC (Tape & Reel)
VP251
SN65HVD251P
8-pin DIP
65HVD251
signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
ABSOLUTE MAXIMUM RATINGS (1), (2)
SN65HVD251
Supply voltage range, VCC
-0.3 V to 7V
Voltage range at any bus terminal (CANH or CANL)
-36 V to 36 V
Transient voltage per ISO 7637, pulse 1, 2, 3a, 3b
±200 V
CANH, CANL
Input voltage range, VI (D, Rs, or R)
-0.3 V to VCC + 0.5
Human Body Model
Electrostatic discharge
(3)
Charged-Device Model
(4)
CANH, CANL and GND
14 kV
All pins
6 kV
All pins
1 kV
Continuous total power dissipation
(see Dissipation Rating
Table)
Storage temperature range, Tstg
-65C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
(3)
(4)
260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
ABSOLUTE MAXIMUM POWER DISSIPATION RATINGS
PACKAGE
SOIC (D)
PDIP (P)
(1)
(2)
(3)
CIRCUIT BOARD
MODEL
TA = 25°C
POWER RATING
Low-K (2)
600 mW
High-K (3)
963 mW
DERATING FACTOR
ABOVE TA = 25°C
(1)
TA = 85°C POWER
RATING
TA = 125°C POWER
RATING
4.4 mW/°C
312 mW
120 mW
7.7 mW/°C
501 mW
193 mW
Low-K (2)
984 mW
7.8 mW/°C
512 mW
197 mW
High-K (3)
1344 mW
10.8 mW/°C
699 mW
269 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
VALUE
MIN
Θ JB
2
Junction-to-board thermal resistance
TYP
D
78.7
P
56.5
UNITS
MAX
°C/W
SN65HVD251
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SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
THERMAL CHARACTERISTICS (continued)
PARAMETER
TEST CONDITIONS
VALUE
MIN
Θ JC
Junction-to-board thermal resistance
PD
Device power dissipation
TSD
Thermal shutdown junction temperature
UNITS
TYP
D
44.6
P
54.5
MAX
°C/W
VCC = 5 V, Tj = 27 °C, RL = 60Ω,
RS at 0 V, Input to D a 500-kHz
50% duty cycle square wave
97.7
mW
VCC = 5.5 V, Tj = 130°C, RL = 60Ω,
RS at 0 V, Input to D a 500-kHz 50%
duty cycle square wave
142
mW
°C
165
RECOMMENDED OPERATING CONDITIONS
over recommended operating conditions (unless otherwise noted).
PARAMETER
MIN
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode) VI or VIC
High-level input voltage, VIH
D input
Low-level input voltage, VIL
D input
NOM
V
-7 (1)
12
V
0.7 VCC
Input voltage at Rs for standby, VI(Rs)
0.3 VCC
V
6
V
0
VCC
V
0.75 VCC
VCC
V
0
100
kΩ
Rs wave-shaping resistance
Driver
-50
Receiver
mA
-4
Driver
50
Receiver
Operating free-air temperature, TA
4
-40
Junction temperature, Tj
(1)
V
-6
Input voltage to Rs, VI(Rs)
Low-level output current, IOL
UNIT
5.5
Differential input voltage, VID
High-level output current, IOH
MAX
4.5
125
PDIP Package
145
SOIC Package
150
mA
°C
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
CANH
Figure 1 & Figure 2 ,
D at 0 V Rs at 0 V
TYP (1)
MIN
2.75
3.5
MAX
UNIT
4.5
VO(D)
Bus output voltage (Dominant)
VO(R)
Bus output voltage
(Recessive)
VOD(D)
Differential output voltage (Dominant)
Figure 1 , D at 0 V, Rs at 0 V
VOD(D)
Differential output voltage (Dominant)
Figure 2 & Figure 3 , D at 0 V,
Rs at 0 V
1.2
VOD(R)
Differential output voltage (Recessive)
Figure 1 & Figure 2 , D at 0.7
VCC
-120
VOD(R)
Differential output voltage (Recessive)
D at 0.7 VCC, no load
-0.5
VOC(pp)
Peak-to-peak common-mode output voltage
Figure 9, Rs at 0 V
IIH
High-level input current, D Input
D at 0.7 VCC
-40
0
µA
IIL
Low-level input current, D Input
D at 0.3 VCC
-60
0
µA
(1)
CANL
CANH
CANL
Figure 1 & Figure 2 , D at
0.7VCC , Rs at 0 V
0.5
2
V
2
2.5
3
2
2.5
3
1.5
2
3
V
2
3.1
V
12
mV
0.05
600
V
mV
All typical values are at 25°C and with a 5-V supply.
3
SN65HVD251
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SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
DRIVER ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
Figure 11, VCANH at -7 V,
CANL Open
IOS(SS)
TYP (1)
MIN
MAX
Figure 11, VCANH at 12 V,
CANL Open
Short-circuit steady-state output current
2.5
Figure 11, VCANL at -7 V,
CANH Open
mA
-2
Figure 11, VCANL at 12 V,
CANH Open
200
CO
Output capacitance
See receiver input capacitance
IOZ
High-impedance output current
See receiver input current
IIRs(s)
Rs input current for standby
Rs at 0.75 VCC
IIRs(f)
Rs input current for full speed operation
ICC
Supply current
UNIT
-200
-10
Rs at 0 V
µA
-550
0
µA
275
µA
Standby
Rs at VCC, D at VCC
Dominant
D at 0 V, 60Ω load, Rs at 0 V
65
Recessive
D at VCC, no load, Rs at 0 V
14
mA
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
tpLH
TEST CONDITIONS
Propagation delay time, low-to-high-level output
TYP
MAX
Figure 4, Rs at 0 V
MIN
40
70
Figure 4, Rs with 10 kΩ to ground
90
125
Figure 4, Rs with 100 kΩ to ground
500
800
85
125
Figure 4, Rs with 10 kΩ to ground
200
260
Figure 4, Rs with 100 kΩ to ground
1150
1450
Figure 4, Rs at 0 V
tpHL
Propagation delay time, high-to-low-level output
Figure 4, Rs at 0 V
tsk(p)
Pulse skew (|tpHL - tpLH|)
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
ten
Enable time from standby to dominant
Figure 4, Rs with 10 kΩ to ground
Figure 4, Rs with 100 kΩ to ground
Figure 4, Rs at 0 V
Figure 4, Rs with 10 kΩ to ground
Figure 4, Rs with 100 kΩ to ground
45
85
110
180
650
900
35
100
35
100
100
250
100
250
600
1550
600
1550
Figure 8
0.5
UNIT
ns
µs
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT-
Negative-going input threshold voltage
Vhys
Hysteresis voltage (VIT+ - VIT-)
VOH
High-level output voltage
Figure 6, IO = -4mA
VOL
Low-level output voltage
Figure 6, IO = 4mA
4
Rs at 0 V, (See Table 1)
MIN
500
TYP
MAX
750
900
650
UNIT
mV
100
0.8 Vcc
V
0.2 Vcc
V
SN65HVD251
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SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
RECEIVER ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
CANH or CANL at 12
V
II
CANH or CANL at 12
V, VCC at 0 V
Other bus pin at
0 V, Rs at 0 V, D
CANH or CANL at -7 V at 0.7 VCC
Bus input current
CANH or CANL at -7
V, VCC at 0 V
715
-340
Input capacitance, (CANH or CANL)
Pin-to-ground, VI = 0.4 sin (4E6πt) + 0.5 V,
D at 0.7 VCC
20
CID
Differential input capacitance
Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5 V, D
at 0.7 VCC
10
RID
Differential input resistance
D at 0.7 VCC, Rs at 0 V
40
RIN
Input resistance, (CANH or CANL)
D at 0.7 VCC, Rs at 0 V
20
Supply current
µA
-460
CI
ICC
UNIT
600
pF
pF
100
kΩ
50
kΩ
275
µA
Standby
Rs at VCC, D at VCC
Dominant
D at 0 V, 60Ω Load, Rs at 0 V
65
Recessive
D at VCC, No Load, Rs at 0 V
14
mA
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-level output
tpHL
Propagation delay time, high-to-low-level output
tsk(p)
Pulse skew (|tpHL - tpLH|)
tr
Output signal rise time
tf
Output signal fall time
tp(sb)
Propagation delay time in standby
MIN
TYP
MAX
35
50
35
50
Figure 6
20
2
2
Figure 12, Rs at VCC
4
UNIT
ns
4
500
VREF-PIN CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
VO
Reference output voltage
TEST CONDITIONS
-5 µA < IO < 5 µA
-50 µA < IO < 50 µA
MIN
TYP
MAX
0.45 VCC
0.55 VCC
0.4 VCC
0.6 VCC
UNIT
V
5
SN65HVD251
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SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
DEVICE SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
Figure 10, Rs at 0 V
tloop1
tloop2
tloop2
Total loop delay, driver input to receiver
output, recessive to dominant
Total loop delay, driver input to receiver
output, dominant to recessive
Total loop delay, driver input to receiver
output, dominant to recessive
60
100
Figure 10, Rs with 10 kΩ to ground
100
150
Figure 10, Rs with 100 kΩ to ground
440
800
Figure 10, Rs at 0 V
115
150
Figure 10, Rs with 10 kΩ to ground
235
290
Figure 10, Rs with 100 kΩ to ground
1070
1450
105
145
Figure 10, Rs at 0 V, VCC from 4.5 V to 5.1
V,
PARAMETER MEASUREMENT INFORMATION
IO(CANH)
VO(CANH)
D
VOD
II
60 1%
IIRs
Rs
VI
+
VO(CANH) + VO(CANL)
2
VOC
IO(CANL)
VI(Rs)
_
VO(CANL)
Figure 1. Driver Voltage, Current, and Test Definition
Dominant
Recessive
3.5 V
VO(CANH)
2.5 V
1.5 V
VO(CANL)
Figure 2. Bus Logic State Voltage Definitions
CANH
VI
D
VOD
330 1%
60 1%
+
_
RS
CANL
330 1%
Figure 3. Driver VOD
6
MAX
–7 V VTEST 12 V
UNIT
ns
ns
ns
SN65HVD251
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SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION (continued)
CANH
D
VI
RL =
60 1%
+
VI(Rs)
_
Rs
(see Note A)
CL =
50 pF 20%
(see Note B)
VO
CANH
VCC
VCC/2
VI
VCC/2
0V
tPHL
tPLH
0.9V
VO
90%
10%
tr
VO(D)
0.5V
VO(R)
tf
Figure 4. Driver Test Circuit and Voltage Waveforms
CANH
R
VI(CANH)
VI(CANH) + VI(CANL)
VIC =
2
VI(CANL)
IO
VID
VO
CANL
Figure 5. Receiver Voltage and Current Definitions
CANH
R
VI
CANL
(see Note A)
1.5 V
IO
CL = 15 pF
20% (see Note B)
VO
3.5 V
VI
2.4 V
2V
1.5 V
tPLH
VO
tPHL
0.7 VCC
10%
90%
tr
VOH
0.3 VCC
10%
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr≤
6ns, tf≤ 6ns, ZO = 50Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 6. Receiver Test Circuit and Voltage Waveforms
7
SN65HVD251
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SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION (continued)
CANH
R
CANL
100 Pulse Generator
15 s Duration
1% Duty Cycle
tr, tr 100 ns
D at 0 V
or VCC
RS at 0 V or VCC
A.
This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 7. Test Circuit, Transient Over-Voltage Test
Table 1. Receiver Characteristics Over Common Mode Voltage
INPUT
MEASURED
OUTPUT
VCANH
VCANL
|VID|
12 V
11.1 V
900 mV
L
R
-6.1 V
-7 V
900 mV
L
-1 V
-7 V
6V
L
12 V
6V
6V
L
-6.5 V
-7 V
500 mV
H
12 V
11.5 V
500 mV
H
-7 V
-1 V
6V
H
6V
12 V
6V
H
open
open
X
H
DUT
CANH
0V
VI
D
60 1%
Rs
CANL
R
+
VO
_
15 pF 20%
VCC
0.7 VCC
VI
0V
VOH
0.3 VCC
VO
ten
0.3 VCC
VOL
Figure 8. ten Test Circuit and Voltage Waveforms
8
VOL
VOH
SN65HVD251
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SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
CANH
27 1%
D
VI
CANL
27 1%
RS
VOC
50 pF 20%
VOC(PP)
VOC
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr≤
6ns, tf≤ 6ns, ZO = 50Ω.
Figure 9. Peak-to-Peak Common Mode Output Voltage
DUT
CANH
VI
D
60 1%
10 k or 100 k 5%
_
RS
CANL
VRs +
R
+
VO
_
15 pF 20%
VCC
50%
D Input
0V
tLoop2
tLoop1
VOH
0.7 Vcc
R Output
0.3 Vcc
VOL
Figure 10. tLOOP Test Circuit and Voltage Waveforms
9
SN65HVD251
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SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
IOS
CANH
D
0 V or VCC
CANL
Rs
Vin –7 V or 12 V
IOS(SS)
IOS(P)
15 s
0V
12 V
Vin
0V
10 s
or
0V
Vin
–7 V
Figure 11. Driver Short-Circuit Test
CANH
R
VI
(see Note A)
CANL
CL = 15 pF
1.5 V
VO
(see Note B)
3.5 V
2.4 V
VI
1.5 V
tp(sb)
VOH
VO
0.3 VCC
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr≤
6ns, tf≤ 6ns, ZO = 50Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 12. Receiver Propagation Delay in Standby Test Circuit and Waveform
10
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SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
DEVICE INFORMATION
5V
R21%
R11%
CANH
+
R
VID
–
CANL
Vac
R11%
VI
R21%
VID
R1
R2
500 mV
50 450 900 mV
50 227 12 V
VI
–7 V
A.
All input pulses are supplied by a generator having the following characteristics: f < 1.5 MHz, TA = 25oC, VCC = 5.0 V.
Figure 13. Common-Mode Input Voltage Rejection Test
FUNCTION TABLES
Table 2. DRIVER
INPUTS
D
Voltage at Rs, VRs
OUTPUTS
CANH
BUS STATE
CANL
L
VRs < 1.2 V
H
L
Dominant
H
VRs < 1.2 V
Z
Z
Recessive
Open
X
Z
Z
Recessive
X
VRs > 0.75 VCC
Z
Z
Recessive
Table 3. RECEIVER
(1)
DIFFERENTIAL INPUTS [VID = V(CANH) - V(CANL)]
OUTPUT R (1)
VID≥ 0.9 V
L
0.5V < VID < 0.9 V
?
VID ≤ 0.5 V
H
Open
H
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
11
SN65HVD251
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SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
D Input
R Output
VCC
VCC
100 k
5
1 k
Input
Output
9V
9V
CANH Input
CANL Input
VCC
VCC
110 k
110 k
9 k
45 k
9 k
45 k
Input
Input
40 V
40 V
9 k
CANH and CANL Outputs
9 k
Rs Input
VCC
VCC
Output
40 V
+_
Input
Figure 14. Equivalent Input and Output Schematic Diagrams
12
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TYPICAL CHARACTERISTICS
tLOOP1-LOOP TIME
vs
FREE-AIR TEMPERATURE
tLOOP2-LOOP TIME
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT (RMS)
vs
SIGNALING RATE
150
33
72
tLOOP2 – Loop Time – ns
VCC = 4.5 V
VCC = 5 V
70
68
66
VCC = 5.5 V
VCC = 5.5 V
VCC = 5 V
140
135
130
VCC = 4.5 V
64
125
62
–40 –25 –10 5
120
–40 –25 –10 5
20 35 50 65 80 95 110 125
32
31
30
29
28
27
26
25
0
35 50 65 80 95 110 125
VCC = 5 V,
TA = 25°C,
RS = 0 V,
RL = 60 Ω,
CL = 50 pF
250 500 750 1000 1250 1500 1750 2000
TA – Free-Air Temperature – C
Signaling Rate – kbps
Figure 15.
Figure 16.
Figure 17.
DRIVER LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
DRIVER HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
DOMINANT DIFFERENTIAL
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
140
IOH – Driver High-Level Output Current – mA
IOL – Driver Low-Level Output Current – mA
TA – Free-Air Temperature – C
20
VCC = 5 V,
TA = 25°C,
RS = 0 V,
D at 0V
120
100
80
60
40
20
0
0
1
2
3
4
VOCANL – Low-Level Output Voltage – V
5
80
VCC = 5 V,
TA = 25°C,
RS = 0 V,
D at 0V
70
60
50
40
30
20
10
0
0
1
2
3
4
VOCANH – High-Level Output Voltage – V
5
VOD(D) – Dominant Differential Output Voltage – V
tLOOP1 – Loop Time – ns
145
ICC – RMS Supply Current – mA
RS = 0 V
RS = 0 V
74
3
VCC = 5.5 V
2.5
2
VCC = 4.5 V
VCC = 5 V
1.5
1
RS = 0 V,
D at 0V,
RL = 60 Ω
0.5
0
–55
–40
0
25
70
85
125
TA – Free-Air Temperature – C
Figure 18.
Figure 19.
Figure 20.
13
SN65HVD251
www.ti.com
SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
DIFFERENTIAL OUTPUT
FALL TIME
vs
SLOPE RESISTANCE (Rs)
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
50
40
30
20
10
0
TA = 25°C
900
800
VCC = 5.5 V
VCC = 5 V
700
600
VCC = 4.5 V
500
400
300
200
2
3
4
VCC – Supply Voltage – V
Figure 21.
5
6
−0.50
VCC = 5.5 V
−1
−1.50
VCC = 5 V
−2
VCC = 4.5 V
−2.50
100
−3
0
1
Input Resistance Matching − %
TA = 25°C,
RS = 0 V,
D at 0V,
RL = 60 Ω
tf - Differential Output Fall Time - ns
IO – Driver Output Current – mA
0
1000
60
14
INPUT RESISTANCE MATCHING
vs
FREE-AIR TEMPERATURE
0
10 20 30 40 50 60 70 80 90 100
RS - Slope Resistance - k
Figure 22.
−50
0
50
100
TA − Free-Air Temperature − °C
Figure 23.
150
SN65HVD251
www.ti.com
SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
APPLICATION INFORMATION
The basics of arbitration require that the receiver at
the sending node designate the first bit as dominant
or recessive after the initial wave of the first bit of a
message travels to the most remote node on a
network and back again. Typically, this sample is
made at 75% of the bit width, and within this
limitation, the maximum allowable signal distortion in
a CAN network is determined by network electrical
parameters.
Factors to be considered in network design include
the ≈ 5 ns/m propagation delay of typical twisted-pair
bus cable; signal amplitude loss due to the loss
mechanisms of the cable; and the number, length,
and spacing of drop-lines (stubs) on a network. Under
strict analysis, variations among the different oscil-
lators in a system also need to be accounted for with
adjustments in signaling rate and stub & bus length.
Table 2 lists the maximum signaling rates achieved
with the SN65HVD251 in high-speed mode with
several bus lengths of category 5, shielded twisted
pair (CAT 5 STP) cable.
Table 4. Maximum Signaling Rates for Various
Cable Lengths
BUS LENGTH (m)
SIGNALING RATE (kbps)
30
1000
100
500
250
250
500
125
1000
62.5
The ISO 11898 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a
maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and
many more nodes on a bus. (Note: Non-standard application may come with a trade-off in signaling rate.) A large
number of nodes requires a transceiver with high input impedance such as the HVD251.
The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120Ω
characteristic impedance (Zo). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as
short as possible to minimize signal reflections.
Connectors, while not specified by the Standard should have as little effect as possible on standard operating
parameters such as capacitive loading. Although unshielded cable is used in many applications, data
transmission circuits employing CAN transceivers are usually used in applications requiring a rugged
interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these
electronically harsh environments, and when coupled with the Standard's –2-V to 7-V common-mode range of
tolerable ground noise, helps to ensure data integrity. The HVD251 enhances the Standard's insurance of data
integrity with an extended –7-V to 12-V range of common-mode operation.
NOISE MARGIN
900 mV Threshold
RECEIVER DETECTION WINDOW
75% SAMPLE POINT
500 mV Threshold
NOISE MARGIN
ALLOWABLE JITTER
Figure 24. Typical CAN Differential Signal Eye-Pattern
15
SN65HVD251
www.ti.com
SLLS545B – NOVEMBER 2002 – REVISED SEPTEMBER 2003
An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure 24, the differential
signal changes logic states in two places on the display, producing an eye. Instead of viewing only one logic
crossing on the scope, an entire bit of data is brought into view. The resulting eye pattern includes all of the
effects of systemic and random distortion, and displays the time during which a signal may be considered valid.
The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise
margin of the system. Jitter is typically measured at the differential voltage zero-crossing during the logic state
transition of a signal. Note that jitter present at the receiver threshold voltage level is considered by some to be a
more effective representation of the jitter at the input of a receiver.
As the sum of skew and noise increases, the eye closes and data is corrupted. Closing the width decreases the
time available for accurate sampling, and lowering the height enters the 900 mV or 500 mV threshold of a
receiver.
Different sources induce noise onto a signal. The more obvious noise sources are the components of a
transmission circuit themselves; the signal transmitter, traces & cables, connectors, and the receiver. Beyond
that, there is a termination dependency, cross-talk from clock traces and other proximity effects, VCC & ground
bounce, and electromagnetic interference from near-by electrical equipment.
The balanced receiver inputs of the HVD251 mitigate most all sources of signal corruption, and when used with a
quality shielded twisted-pair cable, help insure data integrity.
Typical Application
Bus Lines – 40 m max
CANH
120 120 Stub Lines –– 0.3 m max
CANL
Vref
RS
VCC
5V
SN65HVD251
0.1 F
Vref
RS
VCC
CANTX
R
CANRX
0.1 F
SN65HVD251
GND
D
5V
RS
VCC
SN65HVD230
GND
D
CANTX
R
CANRX
GND
D
CANTX
R
CANRX
TMS320F243
TMS320F243
TMS320LF2407A
Sensor, Actuator, or
Control Equipment
Sensor, Actuator, or
Control Equipment
Sensor, Actuator, or
Control Equipment
Figure 25. Typical HVD251 Application
16
Vref
3.3 V
0.1 F
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
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