SN75DP118 www.ti.com..................................................................................................................................... SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008 DisplayPort 1:1 Repeater FEATURES APPLICATIONS • • • • 1 • • • Supports Data Rates up to 2.7 Gbps Supports Dual-Mode DisplayPort Output Waveform Mimics Input Waveform Characteristics Enhanced ESD: 12 KV on all pins Enhanced Commercial Temperature Range: 0°C to 85°C 36 Pin 6 × 6 QFN Package Personal Computer Market – Desktop PC – Notebook PC – Docking Station – Standalone Video Card DESCRIPTION The SN75DP118 is a one Dual-Mode DisplayPort input to one Dual-Mode DisplayPort output. The output follows the input signal in a manner that provides the highest level of signal integrity while supporting the EMI benefits of spread spectrum clocking. The SN75DP118 data rates of up to 2.7 Gbps through each link for a total throughput of up to 10.8 Gbps can be realized. In addition to the DisplayPort high speed signal lines, the SN75DP118 also supports the Hot Plug Detect (HPD) and Cable Adapter Detect (CAD) channels. The SN75DP118 is characterized for operation over ambient air temperature of 0°C to 85°C. TYPICAL APPLICATION GPU DP++ SN75DP118 DP++ DisplayPort DVI HDMI Enabled Monitor or HDTV Computer/Notebook/Docking Station 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated SN75DP118 SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008..................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ML_OUT 3(n) ML_OUT 3(p) GND ML_OUT 2(n) VCC ML_OUT 2(p) ML_OUT 1(n) ML_OUT 1(p) SN75DP118 GND DATA FLOW BLOCK DIAGRAM VCC NC ML_OUT 0(n) DPadj ML_OUT 0(p) VCC CAD_INV HPD_IN GND CAD_IN GND LP ML_IN 0(p) CAD_OUT ML_IN 0(n) HPD_OUT VCC ML_IN 3(n) ML_IN 3(p) GND ML_IN 2(n) VCC ML_IN 1(n) ML_IN 2(p) ML_IN 1(p) ML_OUT 1(p) ML_OUT 1(n) GND VDD ML_OUT 3(n) ML_OUT 3(p) ML_OUT 2(n) GND VCC ML_OUT 2(p) GND PACKAGE 27 26 25 24 23 22 21 20 19 VCC 28 18 NC ML_OUT 0(n) 29 17 DPadj ML_OUT 0(p) 30 16 VCC CAD_INV 31 15 HPD_IN GND 32 14 CAD_IN LP 33 13 GND ML_IN 0(p) 34 12 CAD_OUT ML_IN 0(n) 35 11 HPD_OUT VCC 36 10 VDD 2 2 3 4 5 6 7 8 9 ML_IN 1(p) VCC ML_IN 2(p) ML_IN 2(n) GND ML_IN 3(p) ML_IN 3(n) GND 1 ML_IN 1(n) SN75DP118 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP118 SN75DP118 www.ti.com..................................................................................................................................... SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008 PIN FUNCTIONS PIN SIGNAL I/O NO. DESCRIPTION MAIN LINK INPUT PINS ML_IN 0 34, 35 I DisplayPort Main Link Channel 0 Differential Input ML_IN 1 2, 3 I DisplayPort Main Link Channel 1 Differential Input ML_IN 2 5, 6 I DisplayPort Main Link Channel 2 Differential Input ML_IN 3 8, 9 I DisplayPort Main Link Channel 3 Differential Input MAIN LINK OUTPUT PINS ML_OUT 0 30, 29 O DisplayPort Main Link Port A Channel 0 Differential Output ML_OUT 1 26, 25 O DisplayPort Main Link Port A Channel 1 Differential Output ML_OUT 2 23, 22 O DisplayPort Main Link Port A Channel 2 Differential Output ML_OUT 3 20, 19 O DisplayPort Main Link Port A Channel 3 Differential Output HOT PLUG DETECT PINS0 HPD_OUT 11 O Hot Plug Detect Output to the DisplayPort Source HPD_ IN 15 I Hot Plug Detect Input from the DisplayPort Connector CABLE ADAPTER DETECT PINS CAD _OUT 12 O Cable Adapter Detect Output to the DisplayPort Source CAD _ IN 14 I Cable Adapter Detect Input from the DisplayPort Connector LP 33 I Low Power Select Bar CAD_INV 31 I Output Port Priority selection DPadj 17 I DisplayPort Main Link Output Gain Adjustment NC 16 CONTROL PINS Not Connected SUPPLY AND GROUND PINS VCC 4, 16, 24, 28, 36 VDD 10 GND 1, 7, 13, 21, 27, 32 Primary Supply Voltage HPD and CAD Output Voltage Ground Table 1. Control Pin Lookup SIGNAL LP CAD_INV DPadj (1) LEVEL (1) STATE H Normal Mode L Low Power Mode H CAD Inverted L CAD not Inverted 4.53 kΩ Increased Gain 6.49 kΩ Nominal Gain 10 kΩ Decreased Gain DESCRIPTION Normal operational mode for device Device is forced into a Low Power state causing the outputs to go to a high impedance state, All other inputs are ignored. The CAD output logic is inverted from the CAD input The CAD output logic follows the CAD input Main Link DisplayPort Output will have an increased voltage swing Main Link DisplayPort Output will have a nominal voltage swing Main Link DisplayPort Output will have a decreased voltage swing (H) Logic High; (L) Logic Low Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP118 3 SN75DP118 SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008..................................................................................................................................... www.ti.com ORDERING INFORMATION (1) PACKAGE (1) PART NUMBER PART MARKING SN75DP118RHHR DP118 36-pin QFN Reel (large) SN75DP118RHHT DP118 36-pin QFN Reel (small) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Supply Voltage Range (2) (1) VALUE UNIT –0.3 to 5.5 V 1.5 V HPD and CAD I/O –0.3 to VCC + 0.3 V Control I/O –0.3 to VCC + 0.3 V VCC, VDD Main Link I/O (ML_IN x, ML_OUT x) Differential Voltage Voltage Range Human body model Electrostatic discharge (3) ±12000 V Charged-device model (4) ±1000 V Machine model (5) ±200 V Continuous power dissipation (1) See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B. Tested in accordance with JEDEC Standard 22, Test Method C101-A. Tested in accordance with JEDEC Standard 22, Test Method A115-A. (2) (3) (4) (5) DISSIPATION RATINGS PACKAGE PCB JEDEC STANDARD TA < 25°C DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING Low-K 759 mW 7.5 mW/°C 303 mW High-K 2127 mW 21.2 mW/°C 851 mW 36-pin QFN (RHH) (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER RθJB Junction-to-board thermal resistance RθJC Junction-to-case thermal resistance TEST CONDITIONS 4x4 Thermal vias under powerpad PD Device power dissipation LP = 5.5 V; ML: VPP = 1200 mV, 2.7 Gbps, PRBS; HPD_IN/CAD_IN/CAD_INV = 5.5 V; VCC = 5.5 V, VDD = 5.25 V; Temp = 85°C; DPadj = 6.49 kΩ PSD Device power dissipation under low power LP = 0V; HPD_IN/CAD_IN/CAD_INV = 5.5V ; VCC = 5.5V , VDD = 5.2 V; Temp = 85°C; DPadj = 6.49 kΩ (1) 4 MIN TYP MAX (1) UNIT 28.11 °C/W 32.77 °C/W 240 280 mW 40 µW Maximum Rating is simulated under worse case condition. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP118 SN75DP118 www.ti.com..................................................................................................................................... SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VCC Supply Voltage VDD HPD and CAD Output reference voltage TA Operating free-air temperature MIN NOM MAX 4.5 5 5.5 UNIT V 1.62 5.25 V 0 85 °C 0.15 1.40 V 2.7 Gbps 55 Ω 0 2 V MAIN LINK DIFFERENTIAL PINS VID Peak-to-peak input differential voltage dR Data rate Rt Termination resistance VO(term) Output termination voltage 45 50 HPD, CAD, AND CONTROL PINS VIH High-level input voltage 2 5.5 V VIL Low-level input Voltage 0 0.8 V DEVICE POWER The SN75DP118 is designed to operate off of a single 5V supply. ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ICC Supply current LP = 5.5 V; ML: VPP = 1200 mV, 2.7 Gbps, PRBS; HPD_IN/CAD_IN/CAD_INV = 5.5 V; VCC = 5.5 V, VDD = 5.25 V; Temp = 85°C; DPadj = 6.49 kΩ IDD Supply current VDD = 5.5 V ISD Shutdown current LP = 0 V; HPD_IN/CAD_IN/CAD_INV = 5.5 V; VCC = 5.5 V, VDD = 5.25 V; Temp = 85°C; DPadj = 6.49 kΩ MIN TYP MAX UNIT 50 55 mA 0.1 2 mA 4 10 µA HOT PLUG AND CABLE ADAPTER DETECT The SN75DP118 has a built in level shifter for the HPD and CAD outputs. The output voltage level of the HPD and CAD pins is defined by the voltage level of the VDD pin. The state of the HPD pin will also set the active state of the device. If HPD is low the device will enter low power mode. Once HPD goes high, the device will come out of low power mode and enter active mode. If HPD goes LOW for a period of time exceeding tT(HPD), the device will enter the low power mode. ELECTRICAL CHARACTERISTICS over recommended operating (unless otherwise noted) PARAMETER VOH3.3 VOH2.5 TEST CONDITIONS IOH = –100 µA, VDD = 5V VOH5 High-level output voltage VOH1.8 MIN TYP MAX UNIT 4.5 5 V IOH = –100 µA, VDD = 3.3 V 3 3.3 V IOH = –100 µA, VDD = 2.5 V 2.25 2.5 V IOH = –100 µA, VDD = 1.8 V 1.62 1.8 V 0 0.4 V VOL Low-level output voltage IOH = 100 µA IH High-level input current VIH = 2 V, VCC = 5.5 V –10 10 µA IL Low-level input current VIL = 0.8 V, VCC = 5.5 V –10 10 µA Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP118 5 SN75DP118 SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008..................................................................................................................................... www.ti.com SWITCHING CHARACTERISTICS over recommended operating (unless otherwise noted) TYP MAX tPD(CAD) Propagation delay PARAMETER VDD = 5 V 20 30 ns tPD(HPD) Propagation delay VDD = 5 V 70 110 ns tT(HPD) HPD logic switch time VDD = 5 V 200 400 ms tM(HPD) Minimum output pulse duration VDD = 5 V 100 tZ(HPD) Low power to high-level propagation delay VDD = 5 V HPD Input TEST CONDITIONS 100 kW UNIT ns 70 110 ns HPD_IN VCC HPD Output DP118 MIN Sink Hot Plug Detect Pulse Duration 50 % 100 kW 0V tPD(HPD) VDD Minimum Hot Plug Detect Output Pulse Duration tm(HPD) HPD_OUT 0V Figure 1. HPD Test Circuit Figure 2. HPD Timing Diagram #1 CAD_IN VCC 50% 0V tPD(CAD) CAD_OUT VDD 50% 0V Figure 3. CAD Timing Diagram VCC HPD_IN 0V Sink Hot Plug Detect Timeout VDD HPD_OUT tT(HPD) HI-z 0V Active Low Power Figure 4. HPD Timing Diagram Number 2 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP118 SN75DP118 www.ti.com..................................................................................................................................... SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008 HPD_IN = VCC VCC LP = High 50% 0V 0V tZ(HPD) VDD HPD_OUT = VDD 50% 0V Figure 5. HPD Timing Diagram Number 3 MAIN LINK PINS The main link I/O of the SN75DP118 is designed to track the magnitude and frequency characteristics of the input waveform and replicate them on the output. A feature has also been incorporated in the SN75DP118 to either increase of decrease the output amplitude via the resistor connected between the DPadj pin and ground. ELECTRICAL CHARACTERISTICS over recommended operating (unless otherwise noted) PARAMETER ΔVI/O(2) ΔVI/O(3) ΔVI/O(4) Difference between input and output voltages (VOD – VID) ΔVI/O(6) RINT Input termination impedance VIterm Input termination voltage TEST CONDITIONS MIN TYP MAX UNIT VID = 200 mV, DPadj = 6.5 kΩ 0 30 60 VID = 300 mV, DPadj = 6.5 kΩ –24 11 36 VID = 400 mV, DPadj = 6.5 kΩ -45 -15 15 VID = 600 mV, DPadj = 6.5 kΩ -87 -47 -22 45 50 55 Ω 2 V 0 mV SWITCHING CHARACTERISTICS over recommended operating (unless otherwise noted) PARAMETER TEST CONDITIONS tR/F(DP) Output edge rate (20% - 80%) Input edge rate = 80 ps (20% – 80%) tPD Propagation delay time F = 1MHz, VID = 400 mV tSK(1) Intra-pair skew F = 1MHz, VID = 400 mV tSK(2) Inter-pair skew F = 1MHz, VID = 400 mV tDPJIT(PP) Peak-to-peak output residual jitter dR = 2.7Gbps, VID = 400 mV, PRBS7 MIN TYP MAX 115 200 240 25 ps 280 ps 20 ps 40 ps 35 ps Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP118 UNIT 7 SN75DP118 SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008..................................................................................................................................... www.ti.com Vlterm 0 V to 2 V 50 W 50 W 50 W 50 W 0.5 pF Y VD+ VD+ VID Receiver Driver VY Z VD- 100 pF 100 pF VZ VOD = VY - VX VO(PP) = 2* (max (|VY - VZ|) VOC = (VY + VZ) 2 VID = VD+ - VD- ; VPP = 2*(max (|VD+ - VD-|) VICM = (VD+ + VD-) 2 Figure 6. Main Link Test Circuit tR/FDP DVI/O Input Output Input Edge Rate 20% to 80% 80 ps DVI/O Figure 7. Main Link ΔVI/O and Edge Rate Measurements ML_INx+ ML_INxMain Link Input 0V tPD(ML) Main Link Output tPD(ML) 0V Figure 8. Main Link Delay Measurements 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP118 SN75DP118 www.ti.com..................................................................................................................................... SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008 2.2 V ML x+ 50% ML x- 1.8 V tsk1 tsk2 ML y+ 2.2 V 50% ML ytsk1 1.8 V Figure 9. Main Link Skew Measurements Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP118 9 SN75DP118 SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008..................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS INPUT/OUTPUT VOLTAGE vs RESISTANCE INPUT/OUTPUT VOLTAGE vs SUPPLY VOLTAGE 40 150 200 mV 200 mV 100 300 mV 50 400 mV 600 mV 0 -50 -100 DVI/O - Input/Output Voltage - mV DVI/O - Input/Output Voltage - mV 30 20 10 300 mV 0 -10 400 mV -20 -30 -40 -50 600 mV -60 -150 0 2 4 6 8 DPVadj - Resistance - W 10 -70 4.4 12 5 5.2 5.4 5.6 Figure 10. Figure 11. INPUT EDGE RATE vs OUTPUT EDGE RATE POWER DISSIPATION vs DATA RATE 2.5G 3G 200 198 180 5.5 V VDD 160 5 V VDD PD - Power Dissipation - mW Output Edge Rate (20% - 80%) - ps 4.8 VDD - Supply Voltage - V 200 140 120 100 4.5 V VDD 80 60 196 TA = 25°C 194 TA = 85°C 192 190 188 TA = 0°C 186 40 184 20 182 0 180 0 150 50 100 Input Edge Rate (20% - 80%) - ps 200 0 Figure 12. 10 4.6 500M 1G 1.5G 2G Data Rate - Bps Figure 13. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP118 SN75DP118 www.ti.com..................................................................................................................................... SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008 APPLICATION INFORMATION Power Logic The power logic of the SN75DP118 is tied to the state of the HPD input pin as well as the low power pin. When HPD_IN is LOW the SN75DP118 enters the low power state. In this state the outputs are high impedance and the device shuts down to optimize power conservation. When HPD_IN goes high the device enters the normal operational state. Several key factors were taken into consideration with this digital logic implementation of channel selection, as well as HPD repeating. This logic is described in the following scenarios. Scenario 1. Low Power State to Active State: • There are two possible cases for this scenario depending on the state of the low power pin. – Case one: In this case HPD_IN is initially LOW and the low power pin is also LOW. In this initial state the device is in a low power mode. Once the HPD input goes to a HIGH state the device remains in the low power mode, with both the main link and auxiliary I/O in a high impedance state (Figure 14). – Case two: In this case HPD_IN is initially LOW and the low power pin is HIGH. In this initial state the device is in a low power mode. Once the HPD input goes to a HIGH state the device comes out of the low power mode and enters active mode, enabling the main link and auxiliary I/O. The HPD output to the source is enabled and follows the logic state of the input HPD (Figure 15). This is specified as tZ(HPD). Figure 14. Figure 15. Scenario 2. HPD Changes: • In this case the HPD input is initially HIGH. The HPD output logic state follows the state of the HPD input. If the HPD input pulses LOW, as may be the case if the sink device is requesting an interrupt, the HPD output to the source will also pulse Low for the same duration of time with a slight delay (Figure 16). The delay of this signal through the SN75DP118 is specified as tPD(HPD). If the duration of the LOW pulse is less then tM(HPD) it may not be accurately repeated to the source. If the duration of the LOW pulse exceeds tT(HPD) the device determines that an unplug event has occurred and enters the low power state (Figure 17). Once the HPD input goes high again the device returns to the active state as indicated in scenario 1. Figure 16. Figure 17. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP118 11 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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