TI SN74LVC2G17QDCKRQ1

SCES618 − OCTOBER 2004
D Qualification in Accordance With
D
D
D
D
D
D
D
D
D
D Ioff Supports Partial-Power-Down Mode
AEC-Q100†
Qualified for Automotive Applications
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5.4 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
D
D
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 1000-V Charged-Device Model (C101)
DBV OR DCK PACKAGE
(TOP VIEW)
1A
GND
2A
1
6
2
5
3
4
1Y
VCC
2Y
† Contact factory for details. Q100 qualification data available on
request.
description/ordering information
This dual Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G17 contains two buffers and performs the Boolean function Y = A. The device functions as two
independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going
(VT+) and negative-going (VT−) signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
−40°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
SOT (SOT-23) − DBV
Reel of 3000
SN74LVC2G17QDBVRQ1
C17_
SOT (SC-70) − DCK
Reel of 3000
SN74LVC2G17QDCKRQ1
C7_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
H
L
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCES618 − OCTOBER 2004
logic diagram (positive logic)
1A
2A
1
6
3
4
1Y
2Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
VCC
VI
Supply voltage
Input voltage
VO
Output voltage
Operating
VCC = 1.65 V
VCC = 2.3 V
IOH
MAX
5.5
V
0
5.5
V
0
VCC
−4
V
VCC = 3 V
VCC = 2.3 V
VCC = 3 V
mA
−24
−32
4
8
16
Low-level output current
UNIT
−8
−16
High-level output current
VCC = 4.5 V
VCC = 1.65 V
IOL
MIN
1.65
mA
24
VCC = 4.5 V
32
TA
Operating free-air temperature
−40
125
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
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SCES618 − OCTOBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VT+
Positive-going input
threshold voltage
VT−
Negative-going input
threshold voltage
∆VT
Hysteresis
(VT+ − VT−)
MIN
1.65 V
0.7
1.4
2.3 V
1
1.7
3V
1.3
2.2
1.9
3.1
5.5 V
2.2
3.7
1.65 V
0.3
0.7
2.3 V
0.4
1
3V
0.6
1.3
4.5 V
1.1
2
5.5 V
1.4
2.5
1.65 V
0.3
0.8
2.3 V
0.4
0.9
3V
0.4
1.1
4.5 V
0.6
1.3
0.7
1.4
IOH = −100 µA
IOH = −4 mA
1.65 V to 5.5 V
IOH = −8 mA
IOH = −16 mA
2.3 V
1.65 V
4.5 V
II
Ioff
ICC
∆ICC
A input
3.8
1.65 V
0.45
IOL = 8 mA
IOL = 16 mA
2.3 V
0.3
0.4
3V
0.55
0 to 5.5 V
0
Ci
VI = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
POST OFFICE BOX 655303
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
• DALLAS, TEXAS 75265
V
0.55
4.5 V
IO = 0
Other inputs at VCC or GND
V
2.3
0.1
VI = 5.5 V or GND,
One input at VCC − 0.6 V,
V
V
1.65 V to 5.5 V
VI = 5.5 V or GND
VI or VO = 5.5 V
V
1.9
IOL = 100 µA
IOL = 4 mA
IOL = 24 mA
IOL = 32 mA
UNIT
VCC − 0.1
1.2
2.4
3V
IOH = −24 mA
IOH = −32 mA
VOL
MAX
4.5 V
5.5 V
VOH
TYP†
VCC
4
±5
µA
±10
µA
10
µA
500
µA
pF
3
SCES618 − OCTOBER 2004
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.9
9.3
1.9
5.7
2.2
5.4
1.5
4.3
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
17
• DALLAS, TEXAS 75265
18
VCC = 3.3 V
TYP
19
VCC = 5 V
TYP
21
UNIT
pF
SCES618 − OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
CL
(see Note A)
VLOAD
Open
S1
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPZL
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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5
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
6
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-3/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
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