TI TS5A6542YZPR

TS5A6542
0.75-Ω SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS230 – APRIL 2006
FEATURES
•
•
•
•
•
•
•
•
•
•
Specified Break-Before-Make Switching
Low ON-State Resistance (0.75 Ω Max)
Control Inputs Referenced to VIO
Low Charge Injection
Excellent ON-State Resistance Matching
Low Total Harmonic Distortion (THD)
2.25-V to 5.5-V Power Supply (V+)
1.65-V to 1.95-V Logic Supply (VIO)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 4000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
– 400-V Machine Model (A115-A)
•
COM Port to GND
– 8000-V Human-Body Model
(A114-B, Class II)
– ±15-kV Contact Discharge (IEC 61000-4-2)
APPLICATIONS
•
•
•
Cell Phones
PDAs
Portable Instrumentation
YZT PACKAGE
(BOTTOM VIEW)
VIO
NC
GND
NO
D1
4 5
D2
C1
3
C2
B1
2 7
B2
A1
1 8
A2
6
V+
IN
COM
GND
DESCRIPTION/ORDERING INFORMATION
The TS5A6542 is a single-pole double-throw (SPDT) analog switch that is designed to operate from 2.25 V to
5.5 V. The device offers a low ON-state resistance with an excellent channel-to-channel ON-state resistance
matching, and the break-before-make feature to prevent signal distorion during the transferring of a signal from
one path to another. The device has excellent total harmonic distortion (THD) performance and consumes very
low power. These features make this device suitable for portable audio applications.
The TS5A6542 has a separate logic supply pin (VIO) operates from 1.65 V to 1.95 V. VIO powers the control
circuitry, which allows the TS5A6542 to be controlled by 1.8-V signals.
ORDERING INFORMATION
TA
–40°C to 85°C
(1)
(2)
PACKAGE (1)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZT
(Pb-free) 0.625-mm max height
ORDERABLE PART NUMBER
Tape and reel
TS5A6542YZTR
TOP-SIDE MARKING (2)
_ _ _ JH7
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
YZT: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
TS5A6542
0.75-Ω SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS230 – APRIL 2006
SUMMARY OF CHARACTERISTICS (1)
2:1 Multiplexer/Demultiplexer
(1 × SPDT)
Configuration
Number of channels
1
ON-state resistance (ron)
0.75 Ω max
ON-state resistance match (∆ron)
0.1 Ω max
ON-state resistance flatness [(ron(flat)]
0.1 Ω max
Turn-on/turn-off time (tON/tOFF)
25 ns/20 ns
Charge injection (QC)
15 pC
Bandwidth (BW)
43 MHz
OFF isolation (OISO)
–63 dB at 1 MHz
Crosstalk (XTALK)
–63 dB at 1 MHz
Total harmonic distortion (THD)
0.004%
Leakage current [INO(OFF)/INC(OFF)]
20 nA
Package option
(1)
8-pin WCSP
V+ = 5 V, TA = 25°C
FUNCTION TABLE
NC TO COM,
COM TO NC
NO TO COM,
COM TO NO
L
ON
OFF
H
OFF
ON
IN
Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
MAX
UNIT
V+
VIO
Supply voltage range (3)
–0.5
6.5
V
VNC
VNO
VCOM
Analog voltage range (3) (4) (5)
–0.5
V+ + 0.5
V
II/OK
Analog port diode current (6)
INC
INO
ICOM
On-state switch current
VI
Digital input voltage range (3) (4)
IIK
Digital input clamp current
I+
IGND
Continuous current through V+ or GND
θJA
Package thermal impedance (8)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
2
MIN
VNO, VCOM < 0 or VNO, VCOM > V+
VNO, VCOM = 0 to V+
On-state peak switch current (7)
VI < 0
–50
50
–200
200
–400
400
–0.5
6.5
–50
–100
–65
mA
mA
V
mA
100
mA
102
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 5.5 V maximum.
Requires clamp diodes on analog port to V+
Pulse at 1-ms duration <10% duty cycle
The package thermal impedance is calculated in accordance with JESD 51-7.
Submit Documentation Feedback
TS5A6542
0.75-Ω SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS230 – APRIL 2006
Electrical Characteristics for 5-V Supply (1)
V+ = 4.5 V to 5.5 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
TA
V+
MIN
TYP MAX
0
V+
UNIT
Analog Switch
Analog signal range
VCOM,
VNO
ON-state resistance
ron
VNO or VNC = 2.5 V,
ICOM = –100 mA,
Switch ON,
See Figure 14
ON-state resistance
match between
channels
∆ron
VNO or VNC = 2.5 V,
ICOM = –100 mA,
Switch ON,
See Figure 14
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –100 mA,
Switch ON,
See Figure 14
ON-state resistance
flatness
NO, NC
OFF leakage current
NC, NO
ON leakage current
COM
ON leakage current
ron(flat)
25°C
Full
Full
25°C
INO(OFF),
INC(OFF)
VNO = 1 V, 4.5 V,
VCOM = 4.5 V, 1 V,
VNC = Open,
or
VNO = 1 V, 4.5 V,
VCOM = 4.5 V, 1 V,
VNO = Open,
Switch OFF,
See Figure 15
INO(ON)
VNO = 1 V, 4.5 V,
VCOM, VNC = Open,
or
VNC = 1 V, 4.5 V,
VCOM, VNO = Open,
Switch ON,
See Figure 16
ICOM(ON)
0.05
4.5 V
4.5 V
0.1
–20
5.5 V
5.5 V
Full
0.25
Ω
20
100
2
–200
–20
5.5 V
2
–100
–20
25°C
See Figure 16
Ω
0.25
25°C
Full
Ω
0.1
Full
Full
0.1
0.1
25°C
25°C
0.75
0.8
25°C
VNO or VNC = 1 V, 1.5 V,
Switch ON,
2.5 V,
See Figure 14
ICOM = –100 mA,
VCOM = 1 V, 4.5 V,
VNO and VNC = Open,
or
VCOM = 1 V, 4.5 V,
VNO or VNC = Open,
0.5
4.5 V
V
20
200
2
nA
nA
20
–200
200
nA
Digital Control Input (IN) (2)
Input logic high
VIH
VIO = 1.65 V to 1.95 V
Full
0.65
× VIO
VIO
V
Input logic low
VIL
VIO = 1.65 V to 1.95 V
Full
0
0.35
× VIO
V
Input leakage current
(1)
(2)
IIH, IIL
VI = VIO or 0
25°C
Full
5.5 V
–2
2
–20
20
nA
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
All unused digital inputs of the device must be held at VIO or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Submit Documentation Feedback
3
TS5A6542
0.75-Ω SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS230 – APRIL 2006
Electrical Characteristics for 5-V Supply (1) (continued)
V+ = 4.5 V to 5.5 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
TA
V+
MIN
1
TYP MAX
UNIT
Dynamic
Turn-on time
tON
VCOM = V+,
RL = 50 Ω,
CL= 35 pF,
See Figure 18
25°C
5V
Full
4.5 V
Turn-off time
tOFF
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 18
25°C
5V
Full
4.5 V
Break-before-make
time
tBBM
VNC = VNO = V+/2,
RL = 50 Ω,
CL = 35 pF,
See Figure 19
25°C
5V
1
Full
4.5 V
1
Charge injection
QC
VGEN = 0,
RGEN = 0,
CL = 1 nF,
See Figure 23
25°C
5V
15
pC
NO
OFF capacitance
CNO(OFF)
VNO = V+ or GND,
Switch OFF,
See Figure 17
25°C
5V
37
pF
NC, NO
ON capacitance
CNC(ON),
CNO(ON)
VNC or VNO = V+ or
GND,
Switch ON,
See Figure 17
25°C
5V
130
pF
COM
ON capacitance
CCOM(ON)
VCOM = V+ or GND,
Switch ON,
See Figure 17
25°C
5V
130
pF
VI = VIO or GND,
See Figure 17
25°C
5V
6.5
pF
Digital input
capacitance
CI
12.5
25
30
1
9.5
20
25
5
10
12
ns
ns
ns
Bandwidth
BW
RL = 50 Ω,
Switch ON,
See Figure 20
25°C
5V
43
MHz
OFF isolation
OISO
RL = 50 Ω,
f = 1 MHz,
See Figure 21
25°C
5V
–63
dB
Crosstalk
XTALK
RL = 50 Ω,
f = 1 MHz,
See Figure 22
25°C
5V
–63
dB
Total harmonic
distortion
THD
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20 kHz,
See Figure 24
25°C
5V
0.004
%
Supply
Positive supply
current
(1)
4
I+
25°C
VI = VIO or GND
Full
5.5 V
5.5
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
Submit Documentation Feedback
100
750
nA
TS5A6542
0.75-Ω SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS230 – APRIL 2006
Electrical Characteristics for 3.3-V Supply
(1)
V+ = 3 V to 3.6 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
TA
V+
MIN
TYP MAX
0
V+
UNIT
Analog Switch
Analog signal range
VCOM,
VNO
ON-state resistance
ron
ON-state resistance
match between
channels
∆ron
ON-state resistance
flatness
NO, NC
OFF leakage current
NC, NO
ON leakage current
COM
ON leakage current
ron(flat)
INO(OFF),
INC(OFF)
INO(ON)
ICOM(ON)
VNO or VNC = 2 V,
ICOM = –100 mA,
Switch ON,
See Figure 14
VNO or VNC = 2 V, 0.8 V, Switch ON,
ICOM = –100 mA,
See Figure 14
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –100 mA,
Switch ON,
See Figure 14
25°C
Full
Full
VNO = 1 V, 3 V,
VCOM = 3 V, 1 V,
VNC = Open,
or
VNC = 1 V, 3 V,
VCOM = 3V, 1 V,
VNO = Open,
25°C
VNO = 1 V, 3 V,
VNC and VCOM = Open,
or
VNC = 1 V, 3 V,
VNO and VCOM = Open,
VCOM = 1 V,
VNO and VNC = Open,
or
VCOM = 3 V,
VNO and VNC = Open,
0.1
3V
3V
Full
0.1
–20
3.6 V
3.6 V
Full
0.3
Ω
20
50
2
–30
–10
3.6 V
2
–50
–10
25°C
See Figure 16
Ω
0.3
25°C
Switch ON,
See Figure 16
Ω
0.2
Full
Full
0.15
0.15
25°C
25°C
0.9
1.2
25°C
VNO or VNC = 0.8 V, 2 V, Switch ON,
ICOM = –100 mA,
See Figure 14
Switch OFF,
See Figure 15
0.75
3V
V
10
30
2
nA
nA
10
–30
30
nA
Digital Control Input (IN) (2)
Input logic high
VIH
VIO = 1.65 V to 1.95 V
Full
0.65
× VIO
VIO
V
Input logic low
VIL
VIO = 1.65 V to 1.95 V
Full
0
0.35
× VIO
V
–2
2
–20
20
Input leakage current
(1)
(2)
IIH, IIL
VI = VIO or 0
25°C
Full
3.6 V
nA
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
All unused digital inputs of the device must be held at VIO or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Submit Documentation Feedback
5
TS5A6542
0.75-Ω SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS230 – APRIL 2006
Electrical Characteristics for 3.3-V Supply (1) (continued)
V+ = 3 V to 3.6 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
TA
V+
MIN
TYP MAX
UNIT
Dynamic
Turn-on time
tON
VCOM = V+,
RL = 50 Ω,
CL= 35 pF,
See Figure 18
25°C
3.3 V
5
Full
3V
3
Turn-off time
tOFF
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 18
25°C
3.3 V
1
Full
3V
1
Break-before-make
time
tBBM
VNC = VNO = V+/2,
RL = 50 Ω,
CL = 35 pF,
See Figure 19
25°C
3.3 V
1
Full
3V
1
Charge injection
QC
VGEN = 0,
RGEN = 0,
CL = 1 nF,
See Figure 23
25°C
3.3V
6.5
pC
NO
OFF capacitance
CNO(OFF)
VNO = V+ or GND,
Switch OFF,
See Figure 17
25°C
3.3 V
38
pF
NC, NO
ON capacitance
CNC(ON),
CNO(ON)
VNC or VNO = V+ or
GND,
Switch ON,
See Figure 17
25°C
3.3 V
133
pF
COM
ON capacitance
CCOM(ON)
VCOM = V+ or GND,
Switch ON,
See Figure 17
25°C
3.3 V
133
pF
VI = VIO or GND,
See Figure 17
25°C
3.3 V
6.5
pF
Digital input
capacitance
CI
15
30
35
9
20
25
8
13
15
ns
ns
ns
Bandwidth
BW
RL = 50 Ω,
Switch ON,
See Figure 20
25°C
3.3 V
42
MHz
OFF isolation
OISO
RL = 50 Ω,
f = 1 MHz,
See Figure 21
25°C
3.3 V
–63
dB
Crosstalk
XTALK
RL = 50 Ω,
f = 1 MHz,
See Figure 22
25°C
3.3 V
–63
dB
Total harmonic
distortion
THD
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20 kHz,
See Figure 24
25°C
3.3 V
0.004
%
Supply
Positive supply
current
(1)
6
I+
25°C
VI = VIO or GND
Full
3.6 V
10
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
Submit Documentation Feedback
50
300
nA
TS5A6542
0.75-Ω SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS230 – APRIL 2006
Electrical Characteristics for 2.5-V Supply
(1)
V+ = 2.25 V to 2.75 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
TA
V+
MIN
TYP MAX
0
V+
UNIT
Analog Switch
Analog signal range
VCOM,
VNO
ON-state resistance
ron
VNO or VNC = 1.8 V,
ICOM = –100 mA,
Switch ON,
See Figure 14
ON-state resistance
match between
channels
∆ron
VNO or VNC = 1.8 V,
0.8 V,
ICOM = –100 mA,
Switch ON,
See Figure 14
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –100 mA,
Switch ON,
See Figure 14
ON-state resistance
flatness
NO, NC
OFF leakage current
NC, NO
ON leakage current
COM
ON leakage current
ron(flat)
INO(OFF),
INC(OFF)
INO(ON)
ICOM(ON)
25°C
Full
1
2.25 V
1.6
25°C
Full
0.15
2.25 V
25°C
VNO = 0.5 V, 2.2 V,
VCOM = 2.2 V, 0.5 V,
VNC = Open,
or
VNC = 0.5 V, 2.2 V,
VCOM = 2.2 V, 0.5 V,
VNO = Open,
25°C
Switch OFF,
See Figure 15
VNO = 0.5 V, 2.2 V,
VNC and VCOM = Open,
or
VNC = 2.2 V, 0.5 V,
VNO and VCOM = Open,
Switch ON,
See Figure 16
VCOM = 0.5 V,
VNO and VNC = Open,
or
VCOM = 2.2 V,
VNO and VNC = Open,
Switch ON,
See Figure 16
2.25 V
0.25
–20
2.75 V
2.75 V
0.5
Ω
20
50
2
–20
–10
2.75 V
2
–50
–10
25°C
Full
Ω
0.6
25°C
Full
Ω
0.5
Full
Full
0.2
0.2
25°C
VNO or VNC = 0.8 V, 1 V,
Switch ON,
1.8 V,
See Figure 14
ICOM = –100 mA,
1.3
V
10
20
2
nA
nA
10
–20
20
nA
Digital Control Input (IN) (2)
Input logic high
VIH
VIO = 1.65 V to 1.95 V
Full
0.65
× VIO
VIO
V
Input logic low
VIL
VIO = 1.65 V to 1.95 V
Full
0
0.35
× VIO
V
Input leakage current
(1)
(2)
IIH, IIL
VI = VIO or 0
25°C
Full
2.75 V
–2
2
–20
20
nA
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
All unused digital inputs of the device must be held at VIO or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Submit Documentation Feedback
7
TS5A6542
0.75-Ω SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS230 – APRIL 2006
Electrical Characteristics for 2.5-V Supply (1) (continued)
V+ = 2.25 V to 2.75 V, VIO = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
TA
V+
MIN
TYP MAX
UNIT
Dynamic
Turn-on time
tON
VCOM = V+,
RL = 50 Ω,
CL= 35 pF,
See Figure 18
25°C
2.5 V
5
Full
2.25 V
5
Turn-off time
tOFF
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 18
25°C
2.5 V
2
Full
2.25 V
2
Break-before-make
time
tBBM
VNC = VNO = V+/2,
RL = 50 Ω,
CL = 35 pF,
See Figure 19
25°C
2.5 V
1
Full
2.25 V
1
Charge injection
QC
VGEN = 0,
RGEN = 0,
CL = 1 nF,
See Figure 23
25°C
2.5 V
5
pC
NO
OFF capacitance
CNO(OFF)
VNO = V+ or GND,
Switch OFF,
See Figure 17
25°C
2.5 V
38
pF
NC, NO
ON capacitance
CNC(ON),
CNO(ON)
VNC or VNO = V+ or
GND,
Switch ON,
See Figure 17
25°C
2.5 V
135
pF
COM
ON capacitance
CCOM(ON)
VCOM = V+ or GND,
Switch ON,
See Figure 17
25°C
2.5 V
135
pF
VI = VIO or GND,
See Figure 17
25°C
2.5 V
6.5
pF
Digital input
capacitance
CI
20
35
40
10
20
25
11
20
25
ns
ns
ns
Bandwidth
BW
RL = 50 Ω,
Switch ON,
See Figure 20
25°C
2.5 V
40
MHz
OFF isolation
OISO
RL = 50 Ω,
f = 1 MHz,
See Figure 21
25°C
2.5 V
–63
dB
Crosstalk
XTALK
RL = 50 Ω,
f = 1 MHz,
See Figure 22
25°C
2.5 V
–63
dB
Total harmonic
distortion
THD
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20 kHz,
See Figure 24
25°C
2.5 V
0.008
%
Supply
Positive supply
current
(1)
8
I+
25°C
VI = VIO or GND
Full
2.75 V
10
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
Submit Documentation Feedback
25
100
nA
TS5A6542
0.75-Ω SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS230 – APRIL 2006
TYPICAL PERFORMANCE
1.6
1.0
1.4
0.8
1.2
rON (Ω)
rON (Ω)
1.0
0.8
0.6
0.4
0.6
0.4
0.2
0.2
0.0
0.0
0.5
1.0
1.5
2.0
0.0
0.0
2.5
0.5
1.0
1.5
2.0
2.5
VIN (V)
VIN (V)
Figure 1. ron vs VCOM (V+ = 2.5 V)
Figure 2. ron vs VCOM (V+ = 3.3 V)
3.0
60
1.0
50
0.8
Leakage (nA)
rON (Ω)
COM (ON)
0.6
0.4
0.2
0.0
0.0
30
20
10
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
NC (OFF)
0
−60
5.0
−40
−20
0
20
40
60
80
100
VIN (V)
TA (5C)
Figure 3. ron vs VCOM (V+ = 5 V)
Figure 4. Leakage Current vs Temperature (V+ = 5 V)
60
20
10
50
0
−10
40
QC (pC)
Positive Supply Current − I+ (nA)
40
30
20
−20
V+ = 2.5 V
−30
−40
−50
−60
10
V+ = 5 V
−70
0
−60
V+ = 3.3 V
−80
−40
−20
0
20
40
60
80
100
0
1
2
3
4
5
TA (°C)
VCOM (V)
Figure 5. I+ vs Temperature (V+ = 5 V)
Figure 6. Charge Injection (QC) vs VCOM
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6
9
TS5A6542
0.75-Ω SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS230 – APRIL 2006
25
16
20
14
tON/tOFF (ns)
tON/tOFF (ns)
TYPICAL PERFORMANCE (continued)
tON
15
10
tOFF
tON
12
tOFF
10
8
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6
−60
−40
−20
0
20
40
60
80
100
V+ (V)
TA – Temperature 5C
Figure 7. tON/tOFF vs Supply Voltage
Figure 8. tON/tOFF vs Temperature (V+ = 5 V)
0
0
−10
−20
Attenuation (dB)
Gain (dB)
−5
−10
−15
−30
−40
−50
−60
−70
−20
−80
−25
0.01
1
10
100
−90
0.01
1000
Frequency (MHz)
1
10
100
1000
Frequency (MHz)
Figure 9. Gain vs Frequency (V+ = 5 V)
Figure 10. Crosstalk vs Frequency (V+ = 5 V)
0
0.006
−10
−20
THD (%)
Attenuation (dB)
0.005
−30
−40
−50
0.004
−60
−70
0.003
−80
−90
−100
0.01
1
10
100
0.002
10
1000
Frequency (MHz)
10k
100k
1M
Frequency (MHz)
Figure 11. OFF Isolation vs Frequency (V+ = 5 V)
10
1k
Figure 12. Total Harmonic Distortion vs Frequency
(V+ = 2.5 V)
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0.75-Ω SPDT ANALOG SWITCH
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SCDS230 – APRIL 2006
TYPICAL PERFORMANCE (continued)
6
VIO = 1.65 V, V+ = 5.5 V
5
VIO = 1.95 V, V+ = 5.5 V
VOUT (V)
4
VIO = 1.65 V, V+ = 3.6 V
3
VIO = 1.95 V, V+ = 3.6 V
VIO = 1.65 V, V+ = 2.25 V
2
VIO = 1.95 V, V+ = 2.25 V
1
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VIN (V)
Figure 13. VIO Thresholds
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0.75-Ω SPDT ANALOG SWITCH
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SCDS230 – APRIL 2006
PARAMETER MEASUREMENT INFORMATION
V+
VNO NO
COM
+
VCOM
Channel ON
r on +
VI
ICOM
IN
VCOM * VNO
W
I COM
VI = VIH or VIL
+
GND
Figure 14. ON-State Resistance (ron)
V+
VNO NO
COM
+
VCOM
+
VI
OFF-State Leakage Current
Channel OFF
VI = VIH or VIL
IN
+
GND
Figure 15. OFF-State Leakage Current (ICOM(OFF), INC(OFF), ICOM(PWROFF), INC(PWR(FF))
V+
VNO NO
COM
+
VI
VCOM
ON-State Leakage Current
Channel ON
VI = VIH or VIL
IN
+
GND
Figure 16. ON-State Leakage Current (ICOM(ON), INC(ON))
12
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0.75-Ω SPDT ANALOG SWITCH
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SCDS230 – APRIL 2006
PARAMETER MEASUREMENT INFORMATION (continued)
V+
VNO
NO
Capacitance
Meter
VBIAS = V+, VIO, or GND and
VI = VIO or GND
COM
COM
VI
IN
Capacitance is measured at NO,
COM, and IN inputs during ON
and OFF conditions.
VBIAS
GND
Figure 17. Capacitance (CI, CCOM(OFF), CCOM(ON), CNC(OFF), CNC(ON))
V+
NO
VCOM
VI
Logic
Input(1)
VNO
TEST
RL
CL
tON
50 Ω
35 pF
V+
tOFF
50 Ω
35 pF
V+
COM
CL(2)
IN
GND
RL
VIO
Logic
Input
(VI)
50%
50%
0
tON
Switch
Output
(VNO)
(1)
(2)
VCOM
tOFF
90%
90%
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns, tf < 5 ns.
CL includes probe and jig capacitance.
Figure 18. Turn-On (tON) and Turn-Off Time (tOFF)
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0.75-Ω SPDT ANALOG SWITCH
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SCDS230 – APRIL 2006
PARAMETER MEASUREMENT INFORMATION (continued)
V+
Logic
Input
(VI)
VNC or VNO
NC or NO
VCOM
VIO
50%
0
COM
NC or NO
CL(2)
VI
IN
(2)
90%
90%
tBBM
Logic
Input(1)
(1)
Switch
Output
(VCOM)
RL
VNC or VNO = V+/2
RL = 50 Ω
CL = 35 pF
GND
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns, tf < 5 ns.
CL includes probe and jig capacitance.
Figure 19. Break-Before-Make Time (tBBM)
V+
Network Analyzer
50 W
VNO
NO
Channel ON: NO to COM
COM
VCOM
VI = VIH or VIL
Source
Signal
Network Analyzer Setup
50 W
VI
+
IN
Source Power = 0 dBm
(632-mV P-P at 50-W load)
GND
Figure 20. Bandwidth (BW)
14
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DC Bias = 350 mV
TS5A6542
0.75-Ω SPDT ANALOG SWITCH
WITH INPUT LOGIC TRANSLATION
www.ti.com
SCDS230 – APRIL 2006
PARAMETER MEASUREMENT INFORMATION (continued)
V+
Network Analyzer
Channel OFF: NO to COM
50 W
VNO NO
VI = VIO or GND
COM
Source
Signal
VCOM
50 W
Network Analyzer Setup
VI
50 W
Source Power = 0 dBm
(632-mV P-P at 50-W load)
IN
+
GND
DC Bias = 350 mV
Figure 21. OFF Isolation (OISO)
V+
Network Analyzer
50 W
VNO1
Source
Signal
VNO2
NO1
NO2
COM2
50 W
VI
Channel ON: NO to COM
COM1
50 W
Network Analyzer Setup
Source Power = 0 dBm
(632 mV P-P at 50 W load)
IN
+
GND
DC Bias = 350 mV
Figure 22. Crosstalk (XTALK)
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TS5A6542
0.75-Ω SPDT ANALOG SWITCH
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SCDS230 – APRIL 2006
PARAMETER MEASUREMENT INFORMATION (continued)
V+
RGEN
VGEN
Logic
Input
(VI)
VIH
OFF
ON
OFF V
IL
NO
COM
+
VCOM
∆VCOM
VCOM
CL(1)
VI
VGEN = 0 to V+
IN
Logic
Input(2)
(1)
(2)
RGEN = 0
CL = 1 nF
QC = CL × ∆VCOM
VI = VIH or VIL
GND
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns, tf < 5 ns.
Figure 23. Charge Injection (QC)
Channel ON: COM to NO
VSOURCE = V+ P-P
VI = (VIO – V+/2) or −V+/2
RL = 600 Ω
fSOURCE = 20 Hz to 20 kHz
CL = 50 pF
V+/2
Audio Analyzer
NO
Source
Signal
COM
CL(1)
600 W
VI
IN
600 W
−V+/2
(1)
CL includes probe and jig capacitance.
Figure 24. Total Harmonic Distortion (THD)
16
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TS5A6542YZPR
ACTIVE
WCSP
YZP
Pins Package Eco Plan (2)
Qty
8
3000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
SNAGCU
MSL Peak Temp (3)
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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