TPS54226 www.ti.com SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 4.5V to 18V Input, 2-A Synchronous Step-Down SWIFTTM Converter with Light Load Efficiency Check for Samples: TPS54226 FEATURES 1 • 23 • • • • • • • • • • • • • D-CAP2™ Mode Enables Fast Transient Response Low Output Ripple and Allows Ceramic Output Capacitor Wide VCC Input Voltage Range: 4.5 V to 18 V Wide VIN Input Voltage Range: 2 V to 18 V Output Voltage Range: 0.76 V to 5.5 V Highly Efficient Integrated FET’s Optimized for Lower Duty Cycle Applications – 160 mΩ (High Side) and 110 mΩ (Low Side) High Efficiency, less than 10 μA at shutdown High Initial Bandgap Reference Accuracy Adjustable Soft Start Pre-Biased Soft Start 700-kHz Switching Frequency (fSW) Cycle By Cycle Over Current Limit Power Good Output Auto-Skip Mode APPLICATIONS • Wide Range of Applications for Low Voltage System – Digital TV Power Supply – High Definition Blu-ray Disc™ Players – Networking Home Terminal – Digital Set Top Box (STB) DESCRIPTION The TPS54226 is a adaptive on-time D-CAP2™ mode synchronous buck converter. TheTPS54226 enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution. The main control loop for the TPS54226 uses the D-CAP2™ mode control which provides a very fast transient response with no external compensation components. The adoptive on-time control supports seamless operation between PWM mode at heavy load condition and reduced frequency operation at light load for high efficiency. The TPS54226 also has a proprietary circuit that enables the device to adopt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VCC input, and from 2-V to 18-V VIN input power supply voltage. The output voltage can be programmed between 0.76 V and 5.5 V. The device also features an adjustable slow start time and a power good function. The TPS54226 is available in the 14 pin HTSSOP package, and designed to operate from –40°C to 85°C. VOUT - 50 mA/div IOUT - 1 A/div 100 ms/div 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP2, PowerPAD are trademarks of Texas Instruments. Blu-ray Disc is a trademark of Blu-ray Disc Association. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPS54226 SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TA PACKAGE –45°C to 85°C (1) (2) (3) ORDERABLE PART NUMBER (2) (3) PIN TPS54226PWP PowerPAD™ (HTSSOP) – PWP 14 TPS54226PWPR TRANSPORT MEDIA, QUANTITY ECO PLAN Tube Green (RoHS & no Sb/Br) Tape and Reel, 3000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. All package options have Cu NIPDAU lead/ball finish. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT –0.3 to 20 V VBST –0.3 to 26 V VBST (vs SW1, SW2) –0.3 to 6.5 V VFB, VO, SS, PG –0.3 to 6.5 V SW1, SW2 –2 to 20 V SW1, SW2 (10 ns transient) –3 to 20 V VREG5 –0.3 to 6.5 V PGND1, PGND2 –0.3 to 0.3 V VIN, VCC, EN VI Input voltage range VO Output voltage range Vdiff Voltage from GND to POWERPAD Human Body Model (HBM) –0.2 to 0.2 V 2 kV 500 V ESD rating Electrostatic discharge TJ Operating junction temperature –40 to 150 °C Tstg Storage temperature –55 to 150 °C (1) Charged Device Model (CDM) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS (1) (2 oz. trace and copper pad with solder) (1) PACKAGE THERMAL IMPEDANCE JUNCTION TO AMBIENT TA = 25°C POWER RATING TA = 85°C POWER RATING 14 Pin PWP 44.5°C/W 2.25 W 0.9 W Rating based on JEDEC high thermal conductivity (High K) board with 2 x 2 arrays of thermal vias. See Texas Instruments application report (SLMA002) regarding thermal characteristic of the PowerPAD™ package. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply input voltage range 4.5 18 V VIN Power input voltage range 2 18 V 2 UNIT Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 www.ti.com SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 RECOMMENDED OPERATING CONDITIONS (continued) over operating free-air temperature range (unless otherwise noted) VI Input voltage range MIN MAX VBST –0.1 24 VBST (vs SW1, SW2) –0.1 5.7 SS, PG –0.1 5.7 EN –0.1 18 VO, VFB –0.1 5.5 SW1, SW2 –1.8 18 SW1, SW2 (10 ns transient) –3 18 PGND1, PGND2 –0.1 0.1 UNIT V VO Output voltage range VREG5 –0.1 5.7 V IO Output Current range IVREG5 0 10 mA TA Operating free-air temperature –40 85 °C TJ Operating junction temperature –40 125 °C TYP MAX UNIT ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SUPPLY CURRENT IVCC Operating - non-switching supply current VCC current, TA = 25°C, EN = 5 V, VFB = 0.8 V 800 1200 μA IVCCSDN Shutdown supply current VCC current, TA = 25°C, EN = 0 V 1.8 10 μA LOGIC THRESHOLD VENH EN high-level input voltage EN VENL EN low-level input voltage EN 2 V 0.4 V VFB VOLTAGE AND DISCHARGE RESISTANCE VFB voltage light load mode, TA = 25°C, VO = 1.05 V, IO=10mA VFBTH VFB threshold voltage 771 TA = 25°C, VO = 1.05 V, continuous mode 757 TA = 0°C to 85°C, VO = 1.05 V, continuous mode (1) 753 777 TA = –40°C to 85°C, VO = 1.05 V, continuous mode (1) 751 779 IVFB VFB input current VFB = 0.8 V, TA = 25°C RDischg VO discharge resistance EN = 0 V, VO = 0.5 V, TA = 25°C 765 773 mV 0 ±0.1 μA 50 100 Ω 5.5 5.7 V 20 mV 100 mV VREG5 OUTPUT VVREG5 VREG5 output voltage TA = 25°C, 6.0 V < VCC < 18 V, 0 < IVREG5 < 5 mA VLN5 Line regulation 6.0 V < VCC < 18 V, IVREG5 = 5 mA VLD5 Load regulation 0 mA < IVREG5 < 5 mA IVREG5 Output current VCC = 6 V, VREG5 = 4.0 V, TA = 25°C Rdsonh High side switch resistance Rdsonl Low side switch resistance 5.3 70 mA 25°C, VBST - SW1,2 = 5.5 V 160 mΩ 25°C 110 mΩ MOSFET CURRENT LIMIT Iocl Current limit L out = 2.2 μH (1) 2.5 3.1 4.5 A THERMAL SHUTDOWN TSDN (1) Thermal shutdown threshold Shutdown temperature Hysteresis (1) (1) 150 25 °C Not production tested. 3 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ON-TIME TIMER CONTROL TON On time VIN = 12 V, VO = 1.05 V 145 ns TOFF(MIN) Minimum off time TA = 25°C, VFB = 0.7 V 260 310 ns 2.6 μA SOFT START ISSC SS charge current VSS = 0 V 1.4 2.0 ISSD SS discharge current VSS = 0.5 V 0.1 0.2 VFB rising (good) 85 90 mA POWER GOOD VTHPG PG threshold IPG PG sink current VFB falling (fault) 95 % 85 % 2.5 5 mA OVP detect 115 120 UVP detect 65 70 PG = 0.5 V OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVP Output OVP trip threshold TOVPDEL Output OVP prop delay VUVP Output UVP trip threshold TUVPDEL Output UVP delay TUVPEN Output UVP enable delay 125 μs 5 Hysteresis Relative to soft-start time % 75 % 10 % 0.25 ms x 1.7 UVLO VUVLO UVLO threshold Wake up VREG5 voltage 3.55 3.8 4.05 Hysteresis VREG5 voltage 0.23 0.35 0.47 V DEVICE INFORMATION 1 VO VCC 14 2 VFB VIN 13 VBST 12 SW2 11 SW1 10 3 VREG5 POWER PAD 4 SS 5 GND 6 PG PGND2 9 7 EN PGND1 8 PIN FUNCTIONS PIN NAME NO. DESCRIPTION VO 1 Connect to output of converter. This terminal is used for On-Time Adjustment. VFB 2 Converter feedback input. Connect to output voltage with feedback resistor divider. VREG5 3 5.5 V power supply output. A capacitor (typical 1µF) should be connected to GND. 4 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 www.ti.com SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 PIN FUNCTIONS (continued) PIN NAME DESCRIPTION NO. SS 4 Soft-start control. A external capacitor should be connected to GND. GND 5 Signal ground pin PG 6 Open drain power good output EN 7 Enable control input PGND1, PGND2 Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and GND strongly together near the IC. 8, 9 SW1, SW2 Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current comparators. 10, 11 VBST 12 Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin. VIN 13 Power input and connected to high side NFET drain VCC 14 Supply input for 5 V internal linear regulator for the control circuitry PowerPAD™ Back side Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to PGND. FUNCTIONAL BLOCK DIAGRAM -20% UV 14 VCC OV 1 13 +20% VO VIN VIN VREG5 12 VBST Ref SS SW 11 10 2 VFB VREG5 SGND VREG5 Ceramic Capacitor 3 SS 4 PGND SS GND SW PGND SGND PG PGND ZC Softstart 5 9 8 SW PGND VO Ref 6 VCC -10% UV VREG 5 EN 7 UVLO EN Logic OV UVLO Protection Logic TSD REF Ref 5 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 www.ti.com OVERVIEW The TPS54226 is a 2-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs and Auto-Skip mode to improve light lode efficiency. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types. DETAILED DESCRIPTION PWM Operation The main control loop of the TPS54226 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control. PWM Frequency and Adaptive On-Time Control TPS54226 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS54226 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant. Light Load Mode Control The TPS54226 is designed with Auto-Skip mode to increase light load efficiency. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage. The transition point to the light load operation IOUT(LL) current can be calculated in Equation 1. 1 (VIN - VOUT) · VOUT IOUT(LL) = - = 2 · L · fws VIN (1) Soft Start and Pre-Biased Soft Start The soft start function is adjustable. When the EN pin becomes high, 2-μA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is 2 μA. C6(nF) • Vref C6(nF) • 0.765 Tss(ms) = − = − Iss(µA) 2 (2) A unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation. 6 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 www.ti.com SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 Power Good The power good function is activated after soft start has finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage is within -10% of the target value, internal comparators detect power good state and the power good signal becomes high. The power good output, PG, is an open drain output. If the feedback voltage goes under 15% of the target value, the power good signal becomes low after a 10 μs internal delay. Output Discharge Control TPS54226 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP, UVP, UVLO and thermal shutdown). The output is discharged by an internal 50-Ω MOSFET which is connected from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge operation to avoid the possibility of causing negative voltage at the output. Current Protection Output current is limited by cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state and the controller keeps the OFF state when the inductor current is larger than the over current trip level. To provide both good accuracy and cost effective solution, the device supports temperature compensated internal MOSFET RDS(on) sensing. The inductor current is monitored by the voltage between PGND pin and SW1/SW2 pin. In an overcurrent condition, the current to the load exceeds the current to the output capacitor; thus, the output voltage tends to fall off. Eventually, it will end up with crossing the undervoltage protection threshold and shutdown. Over/Under Voltage Protection The TPS54226 detects over and undervoltage conditions by monitoring the feedback voltage (VFB). This function is enabled after approximately 1.7 times the soft-start time.When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches the high-side MOSFET driver turns off and the low-side MOSFET turns on. When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins. After 250 μs, the device latches off both internal top and bottom MOSFET. UVLO Protection Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower than UVLO threshold voltage, the TPS54226 is shut off. This is protection is non-latching. Thermal Shutdown Thermal protection is self-activating. If the junction temperature exceeds the threshold value (typically 150°C), the TPS54226 shuts off. This protection is non-latching. 7 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS 8 1200 IVCCSDN - Shutdown Current - mA ICC - Supply Current - mA 1000 800 600 400 200 0 -50 0 50 100 TJ - Junction Temperature -° C 6 4 2 0 -50 150 Figure 1. VCC CURRENT vs JUNCTION TEMPERATURE 0 50 100 TJ - Junction Temperature -° C Figure 2. VCC SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 100 1.1 80 VI = 18 V VO - Output Voltage - V 1.075 EN Input Current - mA 150 60 40 VI = 12 V 1.05 VI = 5.5 V 1.025 20 1 0 0 5 10 15 EN Input Voltage - V 20 Figure 3. EN CURRENT vs EN VOLTAGE 0 1 IO - Output Current - A 2 Figure 4. 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT 8 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 www.ti.com SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS (continued) 1.1 VO - Output Voltage - V VOUT - 50 mV/div IO = 10 mA 1.075 1.05 IO = 1 A IOUT - 1 A/div 1.025 100 ms/div 1 0 5 10 15 VI - Input Voltage - V 20 Figure 5. 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE Figure 6. 1.05 V 50 mA TO 2A LOAD TRANSIENT RESPONSE 100 VO = 3.3 V EN - 10 V/div 90 VO = 1.8 V VOUT - 0.5 V/div Efficiency - % 80 VO = 2.5 V 70 60 PG - 5 V/div 50 400 ms/div Figure 7. START-UP WAVE FORM 40 0 0.5 1 1.5 IO - Output Current - A 2 Figure 8. EFFICIENCY vs OUTPUT CURRENT 9 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) 100 900 VO = 2.5 V VO = 3.3 V 60 fsw - Switching Frequency - kHz Efficiency - % 80 VO = 1.8 V 40 20 0 0.001 0.01 IO - Output Current - A 0.1 Figure 9. LIGHT LOAD EFFICIENCY vs OUTPUT CURRENT 800 VO = 1.8 V 700 600 VO = 3.3 V 500 0 5 10 15 VI - Input Voltage - V 20 Figure 10. SWITCHING FREQUENCY vs INPUT VOLTAGE (IO=1 A) 800 VO = 1.05 V VO - 10 mV/div fsw - Switching Frequency - kHz 700 600 500 VO = 1.8 V 400 300 SW - 5 V/div VO = 2.5 V 200 100 0 0.001 0.01 0.1 1 IO - Output Current - A 10 Figure 11. SWICHING FREQUENCY vs OUTPUT CURRENT Figure 12. VOLTAGE RIPPLE AT OUTPUT (IO=2A) 10 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 www.ti.com SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS (continued) VI - 50 mV/div SW - 5 V/div Figure 13. VOLTAGE RIPPLE AT INPUT (IO=2A) 11 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 www.ti.com DESIGN GUIDE Step By Step Design Procedure • • • • This example details the design of a switching regulator design using ceramic output capacitors. This design is available as the HPA539 evaluation module (EVM). A few parameters must be known in order to start the design process. These parameters are typically determined on the system level. For this example, start with the following known parameters: Input voltage range = 4.5 -18 V Output voltage = 1.05 V Output current = 2 A Output voltage ripple = 3% of output voltage (1.05 V x 0.03 = 31.5 mV Figure 14 shows the schematic diagram for this design example. Figure 14. Schematic Output Inductor Selection The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load. Larger ripple current increases output ripple voltage, improves S/N ratio and contributes to stable operation. Smaller ripple currents result in lower output voltage ripple. When using low ESR output capacitors output ripple voltage is usually low, so larger ripple currents are acceptable. The coefficient Kind represents the percentage of ripple current. The value of Kind must not be greater than 0.4. Use 0.3 when using low ESR output capacitors. Equation 3 can be used to calculate L1. Use 700 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS current of Equation 6. 12 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 www.ti.com SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 VOUT VIN (max) - VOUT •− LO = − VIN (max) IOUT • fSW • Kind (3) VOUT VIN (max) - VOUT • Ilp - p = V L •f (4) IN (max) O SW Ilp - p Ilpeak = IO + 2 − 1 Ilp - p2 ILo(RMS) = IO2 + − 12 (5) √ (6) For this design example, use KIND = 0.3 and the inductor value is calculated to be 2.35 μH. For this design, a nearest standard value was chosen: 2.2 μH. For 2.2 μH, the calculated peak current is 2.32 A and the calculated RMS current is 2.008 A. The inductor used is a TDK SPM6530-2R2M with a peak current rating of 8.4 A and an RMS current rating of 8.2 A. Output Capacitor Selection The capacitor value and ESR determines the amount of output voltage ripple. Ceramic output capacitors of at least 20 uF total capacitance is recommended. Using Equation 7 to Equation 9, an initial estimate for the capacitor value, ESR, and RMS current can be calculated. If the load transients are significant consider using the load step, instead of ripple current to calculate the maximum ESR. 1 •− 1 CO > − 8 • fSW VO(ripple) - RESR − I(ripple) (7) VO(ripple) RESR < − Il(ripple) (8) VOUT • (VIN - VOUT) ICO(RMS) =− − √12 • VIN • LO • fSW (9) ( ) For this design, the minimum required capacitance is 4.8 µF and maximum ESR is 49 mΩ. Two TDK C3216JB0J226M 22 µF output capacitors are used. The maximum ESR is 12 mΩ each. The calaculated RMS current is .185 A and each output capacitor is rated for 2 A. Input Capacitor Selection The TPS54226 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. The capacitor voltage rating needs to be greater than the maximum input voltage. In case of separate VCC and VIN, then a ceramic capacitor over 10 μF is recommended for the VIN and also placing ceramic capacitor over 0.1 μF for the VCC is recommended. Bootstrap Capacitor Selection A 0.1-μF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is recommended to use a ceramic capacitor. VREG5 Capacitor Selection A 1-μF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is recommended to use a ceramic capacitor. Output Voltage Resistors Selection The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use 1% tolerance or better divider resistors. Start by using Equation 10 and Equation 11 to calculate VOUT. To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more susceptible to noise and voltage errors from the VFB input current will be more noticeable. 13 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 www.ti.com For output voltage from 0.76 V to 2.5 V: ( R1 VOUT = 0.765 • 1 + − R2 ) (10) For output voltage over 2.5 V: ( R1 VOUT = (0.763 + 0.0017 • VOUT) • 1 + − R2 ) (11) THERMAL INFORMATION This PowerPad™ package incorporates an exposed thermal pad that is designed to be directly to an external heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004. The exposed thermal pad dimensions for this package are shown in the following illustration. 8 14 Thermal Pad 2.46 ° 7 1 2.31 Figure 15. Thermal Pad Dimensions 14 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 www.ti.com SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 LAYOUT CONSIDERATIONS 1. Keep the input switching current loop as small as possible. 2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback pin of the device. 3. Keep analog and non-switching components away from switching components. 4. Make a single point connection from the signal ground to power ground. 5. Do not allow switching current to flow under the device. 6. Keep the pattern lines for VIN and PGND broad. 7. Exposed pad of device must be connected to PGND with solder. 8. VREG5 capacitor should be placed near the device, and connected PGND. 9. Output capacitor should be connected to a broad pattern of the PGND. 10. Voltage feedback loop should be as short as possible, and preferably with ground shield. 11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND. 12. Providing sufficient via is preferable for VIN, SW and PGND connection. 13. PCB pattern for VIN, SW, and PGND should be as broad as possible. 14. If VIN and VCC is shorted, VIN and VCC patterns need to be connected with broad pattern lines. 15. VIN Capacitor should be placed as near as possible to the device. Additional Thermal Vias FEEDBACK RESISTORS VCC SLOW START CAP ANALOG GROUND TRACE To Enable Control VFB VIN VREG5 VBST SS SW1 GND SW2 PG PGND1 EN VIN VIN INPUT BYPASS CAPACITOR VCC VOUT BIAS CAP Connection to POWER GROUND on internal or bottom layer VCC INPUT BYPASS CAPACITOR EXPOSED POWERPAD AREA BOOST CAPACITOR OUTPUT INDUCTOR PGND2 VOUT OUTPUT FILTER CAPACITOR Additional Thermal Vias POWER GROUND VIA to Ground Plane Etch on Bottom Layer or Under Component Figure 16. TPS54226 Layout 15 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 TPS54226 SLVSA14A – OCTOBER 2009 – REVISED OCTOBER 2009 www.ti.com REVISION HISTORY Changes from Original (October 2009) to Revision A • Page Changed the device from Product Preview to Production .................................................................................................... 1 16 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS54226 PACKAGE OPTION ADDENDUM www.ti.com 9-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 14 Lead/Ball Finish MSL Peak Temp (3) TPS54226PW PREVIEW TBD Call TI Call TI TPS54226PWP ACTIVE HTSSOP PWP 14 90 TBD Call TI Call TI TPS54226PWPR ACTIVE HTSSOP PWP 14 2000 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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