TI TPS92010DR

TPS92010
www.ti.com
SLUSA14 – DECEMBER 2009
8-PIN HIGH-EFFICIENCY, OFFLINE LED LIGHTING CONTROLLER
Check for Samples: TPS92010
FEATURES
.
1
•
2
•
•
•
•
•
•
•
•
LED Lighting Current Driver Controller with
Energy Saving Features
Quasi-Resonant Mode Operation for Reduced
EMI and Low Switching Losses (Low Voltage
Switching)
Low Standby Current for Deep Dimming
Efficiency Power Consumption
Low Startup Current: 25 μA Maximum
Programmable Line and Load Overvoltage
Protection
– Provides Open LED Protection
Internal Overtemperature Protection
Current Limit Protection
– Cycle-by-Cycle Power Limit
– Primary-Side Overcurrent Hiccup Restart
Mode
1-A Sink TrueDrive™, –0.75-A Source Gate
Drive Output
Programmable Soft-Start
.
APPLICATIONS
•
•
•
Residential LED Lighting Drivers for A19
E12/E26/27, GU10, MR16, PAR30/38 Integral
Lamps
Drivers for Wall Sconces, Pathway Lighting
and Overhead Lighting
Drivers for Wall Washing, Architectural and
Display Lighting
DESCRIPTION
The TPS92010 is a PWM controller with advanced
energy features to provide high efficiency driving for
LED lighting applications.
The TPS92010 incorporates frequency fold back and
low power mode operation to reduce the operation
frequency at light load and no load operations.
The TPS92010 is offered in the 8-pin SOIC (D)
package. Operating junction temperature range is
–40°C to 105°C.
Primary
Secondary
TPS92010
Feedback
1
SS
VSD
7
2
FB
LPM
8
3
PCS
VDD
6
4
GND
GD
5
+
TL431
UDG-09220
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TrueDrive is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS92010
SLUSA14 – DECEMBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TPS92010
UNIT
27
V
Supply current
20
mA
Output sink current (peak)
1.2
Output source current (peak)
–0.8
VDD
Supply voltage range
IDD
IGD(sink)
IGD(source)
Analog inputs
IDD < 20 mA
FB, PCS, SS
VVSD
A
–0.3 to 6.0
IVSD(source)
VLPM
–1.0
mA
30
V
650
mW
VDD = 0 V to 30 V
Power dissipation
SOIC-8 package, TA = 25°C
TJ
Operating junction temperature range
–55 to 150
Tstg
Storage temperature
–65 to 150
TLEAD
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
V
–1.0 to 6.0
°C
300
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages
are with respect to GND. Currents are positive into, negative out of the specified terminal.
RECOMMENDED OPERATING CONDITIONS
MIN
VDD
Input voltage
IGD
Output sink current
TJ
Operating junction temperature
MAX
V
105
°C
0
–40
UNIT
21
A
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
MAX
Human body model
2000
CDM
1500
2
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UNIT
V
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ELECTRICAL CHARACTERISTICS
VDD = 15 V, 0.1-μF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ω resistor from
VSD to -0.1 V, FB = 4.8 V, LPM = not connected, 1-nF capacitor from GD to GND, PCS = GND, TA = –40°C to 105°C,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERALL
ISTARTUP
Startup current
VDD = VUVLO –0.3 V
12
25
ILPM
Standby current
VFB = 0 V
350
550
IDD
Operating current
Not switching
2.5
3.5
130 kHz, QR mode
5.0
7.0
21
26
27
10.3
13.0
15.3
VDD clamp
FB = GND, IDD = 10 mA
μA
mA
V
UNDERVOLTAGE LOCKOUT
VDD(uvlo)
ΔVDD(uvlo)
Startup threshold
Stop threshold
6.3
8
9.3
Hysteresis
4.0
5.0
6.0
V
PWM (Ramp) (1)
DMIN
Minimum duty cycle
VSS = GND, VFB = 2 V
DMAX
Maximum duty cycle
QR mode, fS = max, (open loop)
0%
99%
OSCILLATOR (OSC)
fQR(max)
Maximum QR and DCM frequency
117
130
143
fQR(min)
Minimum QR and FFM frequency
VFB = 1.3 V
32
40
48
fSS
Soft start frequency
VSS = 2.0 V
32
40
48
dTS/dFB
VCO gain
TS for 1.6 V < VFB < 1.8 V
–38
–30
–22
μs/V
12
20
28
kΩ
3.30
4.87
6.00
kHz
FEEDBACK (FB)
RFB
Feedback pullup resistor
VFB
FB, no load
QR mode
Low power mode ON threshold
VFB threshold
0.3
0.5
0.7
Low power mode OFF threshold
VFB threshold
1.2
1.4
1.6
Low power mode hysteresis
VFB threshold
Burst hysteresis
VFB during low power mode
V
0.9
0.13
0.25
0.42
1.0
2.4
3.8
kΩ
2.0
μA
LOW POWER MODE
RDS(on)
LPM on resistance
VLPM = 1 V
ILPM(leakage)
LPM leakage/off current
VFB = 0.44 V, VSTATUS = 15 V
PEAK CURRENT SENSE (PCS)
APCS(FB)
VPCS(os)
(1)
–0.1
(1)
Gain, FB = ΔVFB / ΔVPCS
QR mode
Shutdown threshold
VFB = 2.4 V, VSS = 0 V
PCS to output delay time (power limit)
PCS to output delay time (over current
fault)
PCS discharge impedance
PCS = 0.1 V, VSS = 0 V
PCS offset
SS mode, VSS ≤ 2.0 V, via FB
2.5
1.13
V/V
1.25
1.38
V
PCS = 1.0 VPULSE
175
300
PCS = 1.45 VPULSE
100
150
25
115
250
Ω
0.35
0.40
0.45
V
ns
RPCST and CPCST are not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.
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ELECTRICAL CHARACTERISTICS (continued)
VDD = 15 V, 0.1-μF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ω resistor from
VSD to -0.1 V, FB = 4.8 V, LPM = not connected, 1-nF capacitor from GD to GND, PCS = GND, TA = –40°C to 105°C,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μA
POWER LIMIT (PL) (2)
PCS current
IVSD = -300 μA
–165
–150
–135
PCS working range
QR mode, peak PCS voltage
0.70
0.81
0.92
PL threshold
Peak CS voltage + PCS offset
1.05
1.20
1.37
ISS(chg)
Softstart charge current
VSS = GND
–8.3
–6.0
–4.5
μA
ISS(dis)
Softstart discharge current
VSS = 0.5 V
2.0
5.0
10
mA
VSS
Switching ON threshold
Output switching start
0.8
1.0
1.2
V
–450
–370
μA
–25
mV
4.13
V
IPL(Pcs)
VPL
V
SOFT START (SS)
VALLEY SWITCHING DETECT (VSD)
IVSD(line)
Valley switching detect
IVSD threshold, GD = HI
–512
VVSD(on)
VSD voltage at OUT = HIGH
VFB = 4.8 V, VSS = 5.0 V,
IVSD(on), = –300 μA
–125
VVSD(load)
Load overvoltage protection
VVSD threshold, GD = LO
3.37
3.75
THERMAL PROTECTION (TSP) (3)
Thermal shutdown (TSP) temperature
140
Thermal shutdown hysteresis
°C
15
GATE DRIVE
tRISE
Rise time
tFALL
Fall time
(2)
(3)
4
10% to 90% of 13 V typical out clamp
50
75
10
20
ns
RPCST and CPCST are not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.
Specified by design. Not production tested.
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SLUSA14 – DECEMBER 2009
OPEN LOOP TEST CIRCUIT
VFB
[A]R
PCST
37.4 kW
[A]C
+
PCST
560 pF
TPS92010
1
SS
LPM
LPM
8
RVSD
500 W
CSS
3.3 nF
2
FB
VSD
7
3
PCS
VDD
6
VVSD
CFBT
47 pF
VPCS
IPCS
VDD
IVDD
4
GND
GD
CVDD
100 nF
GND
CBIAS
1 mF
5
VGD
RGD
10 W
CGD
1.0 nF
UDG-09221
A.
RPCST and CPCST are not connected for maximum and minimum duty cycle tests, current sense tests and power limit
tests.
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TPS92010
SLUSA14 – DECEMBER 2009
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BLOCK DIAGRAM
VSD
VDD
6
7
TPS92010
REF
13/8 V
On-Chip
Thermal
Shutdown
Fault Logic
REF_OK
UVLO
LOAD_VSD
OVR_T
LPM
LINE_VSD
PCS
SS_DIS
SS_OVR
LOW PWR
RUN
LPM 8
SS
26 V
+
UVLO
5.0
VREF
QR DETECT
___
LOAD_VSD GD
LINE_VSD
PCS
LOW POWER
QR_DONE
OSCILLATOR
RUN
SS_OVR QR_DONE
CLK
OSC_CL
1
REF
D
SET
+
Low Power Mode
OSC_CL
FB
FB_CLAMP
REF
CLR
PL
1.2 V
GAIN = 1/2.5
FB 2
20
kW
VDD
Modulation
Comparison
Q
5
GD
3
PCS
4
GND
Q
+
+
1.5
R R
400 mV
UDG-09222
6
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SLUSA14 – DECEMBER 2009
ORDERING INFORMATION
(1)
TA
PACKAGES
PART NUMBER
–40°C to 105°C
SOIC (D) (1)
TPS92010D
SOIC (D) package is available taped and reeled by adding “R” to the above part numbers. Reeled
quantities for TPS92010DR is 2,500 devices per reel.
DEVICE INFORMATION
TPS92010 (TOP VIEW)
SS
1
8
LPM
FB
2
7
VSD
PCS
3
6
VDD
GND
4
5
GD
PIN FUNCTIONS
PIN
NAME
NO.
I/O
DESCRIPTION
FB
2
I
Feedback input or control input from the output sensing network to the PWM comparator used to control the peak
current in the power MOSFET. An internal 20-kΩ resistor is between this pin and the internal 5-V regulated
voltage. The voltage of this pin controls the mode of operation in one of the three modes: quasi resonant (QR),
frequency foldback mode (FFM) and low power mode (LPM).
GND
4
–
Ground for internal circuitry. Connect a ceramic 0.1-μF bypass capacitor between VDD and GND, with the
capacitor as close to these two pins as possible.
GD
5
O
1-A sink (TrueDrive™ ) and 0.75-A source gate drive output. This output drives the power MOSFET and switches
between GND and the lower of VDD or the 13-V internal output clamp.
LPM
8
O
The low power mode pin is an ACTIVE HIGH open drain signal that indicates the device has entered low power
mode. LPM pin is high during UVLO, (VDD < startup threshold), and softstart, (SS < FB).
PCS
3
I
Peak current sense input, also programs power limit and is used to control modulation and activate overcurrent
protection. The PCS voltage input originates across a current sense resistor and ground. Power limit is
programmed with an effective series resistance between this pin and the current sense resistor.
SS
1
I
Soft-start programming pin. Program the soft-start rate with a capacitor to ground; the rate is determined by the
capacitance and the internal soft-start charge current. Placement of the soft-start capacitor is critical and should be
placed as close as possible to the SS pin and GND, keeping trace length to a minimum. All faults discharge the
SS pin to GND through an internal MOSFET with an RDS(on) of approximately 100 Ω. The internal modulator
comparator reacts to the lowest of the SS voltage, the internal FB voltage and the peak current limit.
VDD
6
I
Provides power to the device. Use a ceramic 0.1-μF by-pass capacitor for high-frequency filtering of the VDD pin,
as described in the GND pin description. Operating energy is usually delivered from auxiliary winding. To prevent
hiccup operation during start-up, a larger energy storage cap is also needed between VDD and GND.
VSD
7
I
The valley switching detect (VSD) pin senses line, load and resonant conditions using the primary bias winding.
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APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
The TPS92010 is a multi-mode LED Lighting controller, as illustrated in Figure 1 and Figure 2. The mode of
operation depends upon input and dimming conditions. Under all modes of operation, the TPS92010 terminates
the GD = HI signal based on the switch current. Thus, the TPS92010 always operates in current mode control so
that the power MOSFET current is always limited.
START
N
RUN = Logic Low
LPM = Hi Z
N
VDD < 8V?
REF < 4V?
VSD = Logic High?
OT = Logic High?
OC = Logic High
VDD > 13V?
Y
Continuous Fault
Monitor
Y
RUN = Logic High
LPM = Hi Z
Soft Start
RUN = Logic Low
Monitor VFB
V FB < 1.4V
1.4V < VFB < 2.0V
V FB > 2.0V
Fixed V/s
40kHz
LPM = 0V
(In Run-Mode)
LPM = 0V
(In Run-Mode)
V FB < 0.5V
Fixed V/s
Freq. Foldback
(Light Load)
Quasi-Resonant
Mode or DCM
(Normal Load)
N
Y
Zero Pulses
LPM = Hi Z
(In Low Power
Mode)
LPM = 0 V
(In Run-Mode)
Fixed V-sec
40 kHz Burst
N
Y
Y
V FB > 1.5V?
N
V FB > 1.2V?
UDG-09136
Figure 1. Control Flow Chart
8
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fSW
SLUSA14 – DECEMBER 2009
SS Mode
(fixed fSW )
QR Mode
(ZVS)
DCM
(maximum fS)
Constant Voltseconds (ZCS)
Low Power
Mode
Switching
Frequency
fMAX = Oscillator
Frequency
(130 kHz)
fSS
(40 kHz)
This mode applies bursts of 40
kHz soft-start pulses to the power
MOSFET gate. The average fSW
is shown in this operating mode.
fLPM_MX
(40 kHz)
fQR_MIN : (internally
limited to 40 kHz.
t
Hysteretic
transition into
Low Power
Mode.
Feedback
Voltage
VFB
Power Supply
Output Voltage
t
VOUT
Low Power Mode,
PFC bias OFF
t
Peak MOSFET
Current
LPM, pulled up to
VDD
t
VLPM
Load shown is slightly less
than overcurrent threshold
IC Off Softstart
Regular Operation
Fixed Frequency
Frequency Foldback
t
Low Power Mode
Load Power
POUT
POUT
t
UDG-09137
Figure 2. Operation Mode Switching Frequencies
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Under normal operating conditions, the FB pin commands the operating mode of the TPS92010 at the voltage
thresholds shown in Figure 3. Soft-start and fault responses are exceptions. During soft-start mode the
TPS92010 controls the converter at a fixed constant switching frequency of 40 kHz. The soft-start mode is
latched-OFF when VFB becomes less than VSS for the first time after UVLOON. The soft-start state cannot be
recovered until after passing UVLOOFF, and then, UVLOON.
VFB (V)
5.0
Internal Reference
4.0
VFB Control Range Limit
QR Mode
or
DCM Mode
2.0
fSW = 130 kHz
Frequency Foldback Mode
1.4
fSW = 40 kHz
Low Power
Mode
0.7
0.5
Burst-ON
Burst-OFF
Burst Hysteresis
0
Figure 3. Mode Control with FB Pin Voltage
At normal rated operating loads (from 100% to approximately 30% full rated power) the TPS92010 controls the
converter in quasi-resonant mode (QRM) or discontinuous conduction mode (DCM), where DCM operation is at
the clamped maximum switching frequency (130 kHz). For loads that are between approximately 30% and 10%
full rated power, the converter operates in frequency foldback mode (FFM), where the peak switch current is
constant and the output is regulated by modulating the switching frequency for a given and fixed VIN. Effectively,
operation in FFM results in the application of constant volt-seconds to the flyback transformer each switching
cycle. Voltage regulation in FFM is achieved by varying the switching frequency in the range from 130 kHz to 40
kHz. For extremely light loads (below approximately 10% full rated power), the converter is controlled using
bursts of 40-kHz pulses. Keep in mind that the aforementioned boundaries of steady-state operation are
approximate because they are subject to converter design parameters.
Refer to the typical applications block diagram for the electrical connections to implement the features.
10
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Details of the functional boxes in the Block Diagram are shown in Figure 4, Figure 5, Figure 6 and Figure 7
showing how the TPS92010 executes the command of the FB voltage to have the responses that are shown in
Figure 3, Figure 1 and Figure 2. The details of the functional boxes also show the various fault detections and
responses that are included in the TPS92010. During all modes of operation, this controller operates in current
mode control. This allows the TPS92010 to monitor the FB voltage to determine and respond to the varying load
levels.
Quasi-resonant mode and DCM occurs for feedback voltages VFB between 2.0 V and 4.0 V, respectively. In turn,
the PCS voltage is commanded to be between 0.4 V and 0.8 V. A cycle-by-cycle power limit imposes a fixed
0.8-V limit on the PCS voltage. An overcurrent shutdown threshold in the fault logic gives added protection
against high-current, slew-rate shorted winding faults, shown in Figure 7. The power limit feature in the QR
DETECT circuit of Figure 6 adds an offset to the PCS signal that is proportional to the line voltage. The power
limit feature is programmed with RPL, as shown in the typical application diagram.
REF
+
1.4 V
+
OSC Peak
Comparator
OSC_CL
450 kW
+
4.0V
100 kW
SS_OVR
S
Q
R
Q
QR_DONE
+
OSC_CL
0.1V
FB
450 kW
100 kW
CLK
130 kHz OSC
Clamp
Comparator
+
2.0 V
FB_CL
+
OSC Valley
Comparator
UDG-09139
RUN
UDG-09138
Figure 4. Oscillator Details
Figure 5. Mode Clamp Details
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CIN
RSU
NP
CVDD
Auxiliary
Winding
RVSD1
NS
COUT
NB
RVSD2
VDD
VSD
7
TPS92010
QR Detect
0.1 V
+
Slope
RPCS
+
QR_DONE
(Oscillator)
–0.1 V
GD (From Driver)
0.1 V
+
+
+
REF (5 V)
ILINE
REF (5 V)
Power Limit
Offset
3.75 V
RPL1
ILINE
+
ILINE
2
Low Power
(from FAULT logic)
1
LOAD_VSD
(Fault Logic)
1 kW
LINE_VSD
(Fault Logic)
0.45 V
0
PCS
PCS
3
RPL2
UDG-09223
Figure 6. QR Detect Details
12
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TPS92010
REF
UVLO
SET
D
Q
REF_OK
Thermal
Shutdown
Q
CLR
OVR_T
REF
(5 V)
RUN
LINE_VSD
(QR Detect)
SS/DIS
LOAD_VSD
(QR Detect)
20 kW
Q
R
Q
+
0.6 V/0.7 V
FB
S
1.25 V
7
+
Low
Power
Power-Up Reset
0.6 V/1.5 V
FB
Low
Power
8
LPM
+
SS_OVR
PCS
3
PCS
UDG-09224
Figure 7. Fault Logic Details
Quasi-Resonant / DCM Control
Quasi-resonant (QR) and DCM operation occur for feedback voltages VFB between 2.0 V and 4.0 V. In turn, the
peak PCS voltage is commanded to be between 0.4 V and 0.8 V. During this control mode, the rising edge of GD
always occurs at the valley of the resonant ring after demagnetization. Resonant valley switching is an integral
part of QR operation. Resonant valley switching is also imposed if the system operates at the maximum
switching frequency clamp. In other words, the frequency varies in DCM operation in order to have the switching
event occur on the first resonant valley that occurs after a 7.7-μs (130-kHz) interval. Notice that the PCS pin has
an internal dependent current source, ½ ILINE. This current source is part of the cycle-by-cycle power limit
function that is discussed in the Protection Features section.
Frequency Foldback Mode Control
Frequency foldback mode uses elements of the FAULT LOGIC, shown in Figure 7 and the mode clamp circuit,
shown in Figure 5. At the minimum operating frequency, the internal oscillator sawtooth waveform has a peak of
4.0 V and a valley of 0.1 V. When the FB voltage is between 2.0 V and 1.4 V, the FB_CL signal in Figure 5
commands the oscillator in a voltage controlled oscillator (VCO) mode by clamping the peak oscillator voltage.
The additional clamps in the OSCILLATOR restrict VCO operation between 40 kHz and 130 kHz. The FB_CL
voltage is reflected to the modulator comparator effectively clamping the reflected PCS command to 0.4 V.
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Low Power Mode Control
Low power mode uses elements of the FAULT LOGIC, shown in Figure 7 and the mode clamps circuit, shown in
Figure 5. The OSC_CL signal clamps the Low Power-mode operating frequency at 40 kHz. Thus, when the FB
voltage is between 1.4 V and 0.5 V, the controller is commanding an excess of energy to be transferred to the
load which in turn, drives the error higher and FB lower. When FB reaches 0.5 V, GD pulses are terminated and
do not resume until FB reaches 0.7 V. In this mode, the converter operates in hysteretic control with the GD
pulse terminated at a fixed PCS voltage level of 0.4 V. The power limit offset is turned OFF during Low Power
mode and it returns to ON when FB is above 1.4 V, as depicted in Figure 7. H mode reduces the average
switching frequency in order to minimize switching losses and increase the efficiency at light load conditions.
Fault Logic
Advanced logic control coordinates the fault detections to provide proper power supply recovery. This provides
the conditioning for the thermal protection. Line overvoltage protection and load overvoltage protection are
implemented in this block. It prevents operation when the internal reference is below 4.5 V. If a fault is detected
in the thermal shutdown, line overvoltage protection, load overvoltage protection, or REF, the TPS92010
undergoes a shutdown/retry cycle.
Refer to the fault logic diagram in Figure 7 and the QR detect diagram in Figure 6 to program line overvoltage
protection and load overvoltage protection. To program the load overvoltage protection, select the RVSD1 – RVSD2
divider ratio to be 3.75 V at the desired output shut-down voltage. To program line overvoltage protection, select
the impedance of the RVSD1 – RVSD2 combination to draw 450 μA when the VVSD is 0.45 V during the ON-time of
the power MOSFET at the highest allowable input voltage.
Oscillator
The oscillator, shown in Figure 4, is internally set and trimmed so it is clamped by the circuit in Figure 4 to a
nominal 130-kHz maximum operating frequency. It also has a minimum frequency clamp of 40 kHz. If the FB
voltage tries to drive operation to less than 40 kHz, the converter operates in low power mode.
Low Power
The LPM pin is an open drain output, as shown in Figure 7. The LPM output goes into the OFF-state when FB
falls below 0.5 V and it returns to the ON-state (low impedance to GND) when FB rises above 1.4 V.
OPERATING MODE PROGRAMMING
Boundaries of the operating modes are programmed by the flyback transformer and the four components RPL,
RPCS, RVSD1 and RVSD2; shown in Figure 1.
The transformer characteristics that predominantly affect the modes are the magnetizing inductance of the
primary and the magnitude of the output voltage, reflected to the primary. To a lesser degree (yet significant), the
boundaries are affected by the MOSFET output capacitance and transformer leakage inductance. The design
procedure here is to select a magnetizing inductance and a reflected output voltage that operates at the
DCM/CCM boundary at maximum load and maximum line. The actual inductance should be noticeably smaller to
account for the ring between the magnetizing inductance and the total stray capacitance measured at the drain
of the power MOSFET. This programs the QR/DCM boundary of operation. All other mode boundaries are preset
with the thresholds in the oscillator and green-mode blocks.
PROTECTION FEATURES
The TPS92010 has many protection features. Refer to Figures 1, 4, 8, 9 and 10 for detailed block descriptions
that show how the features are integrated into the normal control functions.
Overtemperature
Overtemperature lockout typically occurs when the substrate temperature reaches 140ºC. Retry is allowed if the
substrate temperature reduces by the hysteresis value. Upon an overtemperature fault, CSS on softstart is
discharged and LPM is forced to a high impedance.
Cycle-by-Cycle Power Limit
The cycle terminates when the PCS voltage plus the power limit offset exceeds 1.2 V.
14
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In order to have power limited over the full line voltage range of the QR Flyback converter, the PCS pin voltage
must have a component that is proportional to the primary current plus a component that is proportional to the
line voltage due to predictable switching frequency variations due to line voltage. At power limit, the PCS pin
voltage plus the internal PCS offset is compared against a constant 1.2-V reference in the PWM comparator.
Thus during cycle-by-cycle power limit, the peak PCS voltage is typically 0.8 V.
The current that is sourced from the VSD pin (ILINE) is reflected to a dependent current source of ½ ILINE, that is
connected to the PCS pin. The power limit function can be programmed by a resistor, RPL, that is between the
PCS pin and the current sense resistor. The current, ILINE, is proportional to line voltage by the transformer turns
ratio NB/NP and resistor RVSD1. Current ILINE is programmed to set the line over voltage protection. Resistor RPL
results in the addition of a voltage to the current sense signal that is proportional to the line voltage. The proper
amount of additional voltage has the effect of limiting the power on a cycle-by-cycle basis. Note that RPCS, RPL,
RVSD1 and RVSD2 must be adjusted as a set due to the functional interactions.
Current Limit
When the primary current exceeds maximum current level which is indicated by a voltage of 1.25 V at the PCS
pin, the device initiates a shutdown. Retry occurs after a UVLOOFF/UVLOON cycle.
Overvoltage Protection Function
Input line overvoltage and LED open string protection is programmed with the transformer turn ratios, RVSD1 and
RVSD2. The VSD pin has a 0-V voltage source that can only source current; VSD cannot sink current.
Open String LED protection occurs when the VSD pin is clamped at 0 V. When the bias winding is negative,
during GD = HI or portions of the resonant ring, the 0-V voltage source clamps VSD to 0 V and the current that is
sourced from the VSD pin is mirrored to the Line_VSD comparator and the QR detection circuit. The Line_VSD
comparator initiates a shutdown-retry sequence if VSD sources any more than 450 μA.
Open String LED protection occurs when the VSD pin voltage is positive. When the bias winding is positive,
during demagnetization or portions of the resonant ring, the VSD pin voltage is positive. If the VSD voltage is
greater than 3.75 V, the device initiates a shutdown. Retry occurs after a UVLOOFF/UVLOON cycle.
Undervoltage Lockout
Protection is provided to guard against operation during unfavorable bias conditions. Undervoltage lockout
(UVLO) always monitors VDD to prevent operation below the UVLO threshold.
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15
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TYPICAL CHARACTERISTICS
CLAMP VOLTAGE
vs
JUNCTION TEMPERATURE
SWITCHING FREQUENCY
vs
JUNCTION TEMPERATURE
140
fSW(max) – Maximum Switching Frequency – kHz
30
VDD – Clamp Voltage – V
28
26
24
22
20
–40
–15
10
35
60
85
110
138
136
134
132
130
128
126
124
122
120
–40
135
–15
85
110
135
Figure 9.
PL THRESHOLD
vs
TEMPERATURE
OVERVOLTAGE PROTECTION THRESHOLD
vs
TEMPERATURE
–375
IVSD – Overcoltage Protection Current – mA
VPL – Power Limit Threshold Voltage – mV
60
Figure 8.
850
840
–400
830
820
–425
810
800
–450
790
780
–475
770
760
–15
10
35
60
85
110
135
–500
–40
TJ – Junction Temperature – °C
Figure 10.
16
35
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
750
–40
10
–15
10
35
60
85
110
135
TJ – Junction Temperature – °C
Figure 11.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS92010D
ACTIVE
SOIC
D
8
TPS92010DR
ACTIVE
SOIC
D
8
75
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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