TSL401 128 × 1 LINEAR SENSOR ARRAY SOES011 – MARCH 1996 D D D D D D D 128 × 1 Sensor-Element Organization 400 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity for 256 Gray-Scale (8-Bit) Applications Output Referenced to Ground Low Image Lag (0.5% Typical) Operation to 2 MHz Single 5-V Supply (TOP VIEW) SI CLK AO VDD 1 8 2 7 3 6 4 5 NC GND GND NC NC – No internal connection description The TSL401 linear sensor array consists of a 128 × 1 array of photodiodes and associated charge amplifier circuitry. The pixels measure 63.5 µm (H) × 50 µm (W) with 63.5-µm center-to-center spacing and 13.5 µm between pixels. Operation is simplified by internal logic requiring only a serial input (SI) signal and a clock. functional block diagram Pixel 1 Integrator Reset Pixel 3 Pixel 2 Pixel 128 VDD Analog Bus 4 Output Amplifier + _ 3 Sample/ Output 6,7 Switch Control Logic Q1 CLK SI 2 AO RL (External Load) Gain Trim Q2 Q3 Q128 128-Bit Shift Register 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 1 TSL401 128 × 1 LINEAR SENSOR ARRAY SOES011 – MARCH 1996 Terminal Functions TERMINAL DESCRIPTION NAME NO. AO 3 Analog output CLK 2 Clock. The clock controls charge transfer, pixel output, and reset. GND 6, 7 Ground (substrate). All voltages are referenced to the substrate. NC 5, 8 No internal connection SI 1 Serial input. This input defines the start of the data-out sequence. VDD 4 Supply voltage. Supply voltage for both analog and digital circuits. detailed description The sensor consists of 128 photodiode pixels, arranged in a linear array. Light energy striking a pixel generates photocurrent, which is then integrated. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time. The integration time is the interval between two consecutive output periods. A 128-bit shift register controls the output period of the device. An output period is initiated by applying a logic level 1 to SI for one positive-going clock edge (see Figure 1). This logic one is clocked through a 128-bit shift register, in which one bit is associated with each pixel. When a given bit is high, the associated pixel signal is coupled to the analog output (AO) through an output amplifier. When the bit goes low, the integrator is reset. AO is a source follower that requires an external pulldown resistor. The source-follower configuration permits an analog wired-OR hookup of multiple devices. When the device is not in the output phase, the output is in a high-impedance state. The output is nominally 0 V for no light input and 2 V for a nominal full-scale output. The TSL401 is intended for use in a wide variety of applications, including mark and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical linear and rotary encoding. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TSL401 128 × 1 LINEAR SENSOR ARRAY SOES011 – MARCH 1996 absolute maximum ratings† Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20 mA to 20 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 25°C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions (see Figures 1 and 2) Supply voltage, VDD Input voltage, VI MIN NOM 4.5 5 0 VDD × 0.7 0 High-level input voltage, VIH Low-level input voltage, VIL Wavelength of light source, λ Sensor integration time, tint Setup time, serial input, tsu(SI) 5.5 V VDD VDD V 5 2000 kHz 0.0645 100 ms 0 V ns 20 Operating free-air temperature, TA V nm 0 Hold time, serial input, th(SI) (see Note 1) UNIT VDD × 0.3 700 565 Clock frequency, fclock MAX ns 70 °C NOTE 1: SI must go low before the rising edge of the next clock pulse. CLK 128 Cycles Clock Continues or Remains Low After 129th Cycle 128 Cycles tint SI AO ÇÇÇÇÇ ÇÇÇÇÇ Analog Output Period ÇÇÇÇ ÇÇÇÇ Figure 1. Timing Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 3 TSL401 128 × 1 LINEAR SENSOR ARRAY SOES011 – MARCH 1996 electrical characteristics at fclock = 200 kHz, VDD = 5 V, TA = 25°C, λp = 565 nm, tint = 5 ms, RL = 330 Ω, Ee = 20 µW/cm2 (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS Analog output voltage (white, average over 128 pixels) Analog output voltage (dark, each pixel) PRNU MIN TYP MAX 1.8 2 2.2 V 0.15 0.3 V ± 5% ± 7.5% Pixel response nonuniformity Ee = 0 See Note 3 0 Linearity of analog output voltage See Note 4 ± 0.4% Output noise voltage See Note 5 1 Saturation exposure Analog output saturation voltage IDD IIH Supply current IIL Ci Low-level input current 136 175 3 3.5 2.5 High-level input current VI = VDD VI = 0 Input capacitance UNIT F.S. mVrms nJ/cm2 V 4 mA 1 µA 1 µA 5 pF NOTES: 2. Clock duty cycle is assumed to be 50%. 3. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated. 4. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 5. Peak-to-peak noise is the variation of a single-pixel output under constant illumination as observed over a 5-second period. operating characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tw(H) tw(L) Clock pulse duration (high) 50 ns Clock pulse duration (low) 50 ns ts tv Analog output settling time to ± 1% RL = 330 Ω, CL = 50 pF Valid time RL = 330 Ω, CL = 50 pF, 350 See Note 2 1/(2 fclock) ns s NOTE 2: Clock duty cycle is assumed to be 50%. tw 1 2 128 129 5V 2.5 V CLK 0V tsu(SI) SI 5V 50% 0V th(SI) ts ts AO Pixel 128 Pixel 1 tv Figure 2. Operational Waveforms 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TSL401 128 × 1 LINEAR SENSOR ARRAY SOES011 – MARCH 1996 TYPICAL CHARACTERISTICS PHOTODIODE SPECTRAL RESPONSIVITY 1 TA = 25°C Normalized Responsivity 0.8 0.6 0.4 0.2 0 300 400 500 700 600 800 900 1000 1100 λ – Wavelength – nm Figure 3 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 5 TSL401 128 × 1 LINEAR SENSOR ARRAY SOES011 – MARCH 1996 APPLICATIONS INFORMATION This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated with an electrically nonconductive clear plastic compound. Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 0.430 (10,92) 0.370 (9,40) Pixel 4 is centered horizontally on Pin 1 SI CLK AO VDD NC GND GND NC 8 5 0.325 (8,26) 0.300 (7,62) C L (pixel) C L 0.017 (0,43) 0.260 (6,60) 0.240 (6,10) 0.075 (1,91) 0.040 (1,02) 0.030 (0,76) D NOM 1 0.065 (1,65) 0.200 (5,08) 0.045 (1,14) 0.155 (3,94) 15° TYP 4 0.020 (0,51) R NOM 4 Places 7° MAX TYP 0.063 (1,6) 0.059 (1,5) Seating Plane 0.020 (0,51) R MAX 4 Places 105° 90° 8 Places 0.012 (0,30) 0.008 (0,20) 0.050 (1,27) 0.020 (0,51) 0.060 (1,52) 0.015 (0,38) 0.300 (7,62) T.P.† 0.065 (1,65) 0.045 (1,14) † True position when unit is installed NOTES: A. All linear dimensions are in inches and parenthetically in millimeters. B. This drawing is subject ot change without notice. Figure 4. Packaging Configuration 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 0.150 (3,81) 0.125 (3,18) 0.022 (0,56) 0.014 (0,36) 0.100 (2,54) T.P.† IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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