LTC3445 I2C Controllable Buck Regulator with Two LDOs in a 4mm × 4mm QFN U FEATURES DESCRIPTIO Buck Regulator ■ High Efficiency: Up to 93% ■ 600mA Output Current (V CC1 = 3V, VOUT = 1.3V) ■ Programmable Output Voltage: 0.85V to 1.55V ■ 2.5V to 5.5V Input Voltage Range ■ 1.5MHz Constant Frequency or Spread Spectrum Option ■ Soft-Start LDOs ■ Two LDO Regulators: 0.3V Dropout at 50mA PowerPath Controller ■ Dynamically Regulates V CC BATT 2 IC ■ Standard (100kHz) or Fast Mode (400kHz) ■ 24-Lead (4mm × 4mm) QFN Package The LTC®3445 contains a high efficiency monolithic synchronous current mode buck regulator, two LDO regulators, a PowerPathTM controller and an I2CTM interface. The buck regulator has a 6-bit programmable output range of 0.85V to 1.55V. Also, the buck regulator uses either a constant (1.5MHz) or a spread spectrum switching frequency. Using the spread spectrum option allows for a lower noise regulated output as well as low noise at the input. In addition, the regulated output voltage slew rate is programmable via the I2C interface. The LTC3445 contains two LDO voltage regulators. The regulator output voltages are externally resistor programmable. Each LDO is capable of delivering up to 50mA. The LTC3445 contains control circuitry (PowerPath) for automatic back-up battery selection. VBACKUP is typically a coin cell. U APPLICATIO S ■ ■ Typical supply current during operation is only 360µA and drops to 27µA in shutdown. The 2.5V to 5.5V input voltage range makes the LTC3445 ideal for single Li-Ion battery-powered applications. Automatic Burst Mode ® operation increases efficiency at light loads, further extending battery life. Intel’s Microprocessor Supply (PXA27X) Portable Instruments , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. PowerPath is a trademark of Linear Technology Corporation. I2C is a trademark of Philips Electronics N.V. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, Spread Spectrum patent pending. U TYPICAL APPLICATIO VCC Efficiency and Power Loss vs Load Current, VCC1 = 3.6V VBACKUP 3V COIN CELL + VBACKUP VCC1 VTRACK VCC2 20k VCC1 100 nBATT_FAULT BATTFAULT VCC BATT VBACKUP 2.2µH PWR_EN I2C BUS RUN SW SDA FB LTC3445 VCC 20k nVCC_FAULT 4.7µF CER 1.3V 705k VCC1 OR GND ADD7 VCC1 OR GND ADD6 604k 10µF CER DAC MIN 100 60 50 DAC MAX 40 10 DAC MIN POWER LOSS 1.0 20 1.1V LDO2 503k GND DAC MAX 30 LDO1FB PGOOD EFFICIENCY 80 70 0.85V TO 1.55V LDO1 SCL 3VTYP 1000 604k 10µF CER LDO2FB 3445 TA01 POWER LOSS (mW) 4.7µF CER 90 EFFICIENCY (%) 4.7µF CER 10 0 0.1 1 10 100 LOAD CURRENT (mA) 0.1 1000 3445 TA01b 3445fa 1 LTC3445 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO LDO1FB LDO1 VCC2 LDO2 LDO2FB TOP VIEW 24 23 22 21 20 19 VTRACK 1 18 VCC BATT VBACKUP 2 17 FB VCC1 3 16 NC 25 PGOOD 4 15 RUN 13 NC NC 9 10 11 12 GND 8 VCC1 7 ADD6 14 SW SDA 6 NC ADD7 5 SCL VCC1, VCC2, SDA, SCL Voltages .................. – 0.3V to 6V RUN, VTRACK, VBACKUP, PGOOD, ADD7, ADD6, FB, VCC BATT, BATTFAULT Voltages .............................. – 0.3V to VCC1 SW Voltage ................................ – 0.3V to (VCC1 + 0.3V) LDO1FB, LDO2FB Voltages ..................... – 0.3V to VCC2 LDO1, LDO2 Voltages ................ – 0.3V to (VCC2 + 0.3V) LDO1, LDO2 Source Current ............................... 50mA VCC BATT Source Current ...................................... 8mA P-Channel Switch Source Current (DC) ............. 800mA N-Channel Switch Sink Current (DC) ................. 800mA Peak SW Sink and Source Current ........................ 1.3A LDO1, LDO2, VCC BATT Output Short-Circuit Duration .......................................................... Indefinite Operating Temperature Range (Note 2) ...–40°C to 85°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range ................. –65°C to 125°C BATTFAULT (Note 1) UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 125°C, θJA = 37°C/W, θJC = 2.6°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB ORDER PART NUMBER UF PART MARKING LTC3445EUF 3445 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = VCC2 = 3.6V, unless otherwise noted. SYMBOL PARAMETER VCC1, VCC2 Input Voltage Range CONDITIONS MIN ● 2.5 ● 0.3 ● 3 TYP 1 MAX UNITS 5.5 V RUN Run Threshold PGOOD Reports Undervoltage of any Regulator PGOOD = 0.4V 1.5 V IS DC Bias Current (Shutdown) RUN = 0 27 50 µA DC Bias Current (Buck, LDO1, LDO2 Disabled) RUN = VCC1 105 150 µA mA Buck Regulator RFB Feedback Resistance VOUT(MIN) Regulated Output Voltage IOUT = 100mA, Burst Mode Operation Disabled ● 0.824 0.850 340 0.875 V VOUT(MAX) Regulated Output Voltage IOUT = 100mA, Burst Mode Operation Disabled ● 1.504 1.55 1.597 V VOUT(STEP) Output Voltage Step Size (0 to 48) IOUT = 100mA ● 13.1 14.7 16.1 Output Voltage Slew Rate = 00 IOUT = 100mA, VOUT = 0.85V to 1.55V 11.3 mV/µs Output Voltage Slew Rate = 01 IOUT = 100mA, VOUT = 0.85V to 1.55V 7.5 mV/µs Output Voltage Slew Rate = 10 IOUT = 100mA, VOUT = 0.85V to 1.55V 3.8 mV/µs Output Voltage Slew Rate = 11 IOUT = 100mA, VOUT = 0.85V to 1.55V IPK Peak Inductor Current VCC1 = 3V, VFB = 0.5V or VOUT = 90%, Duty Cycle < 35% VLOADREG Output Voltage Load Regulation kΩ 0.9 0.75 1 0.5 mV mV/µs 1.25 A % 3445fa 2 LTC3445 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = VCC2 = 3.6V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS IS Additional Input DC Bias Current For Buck (Note 4) Active Mode VOUT = 90%, ILOAD = 0A Sleep Mode VOUT = 103%, ILOAD = 0A MIN TYP MAX µA µA 220 6 ● 1.2 1.5 300 UNITS fOSC Nominal Oscillator Frequency VOUT = 100% VOUT = 0V 1.8 MHz kHz RPFET RDS(ON) of P-Channel FET ISW = 100mA 0.45 RNFET RDS(ON) of N-Channel FET ISW = –100mA 0.325 Ω ILSW SW Leakage VRUN = 0V, VSW = 0V or 5V, VCC1 = 5V 1 µA Ω LDO1 IS Additional DC Bias for LDO1 VOUT Regulated Output Voltage VFB 23 2.5V < VIN < 5.5V, 1mA < ILOAD < 50mA Line Regulation ∆VCC2 = 2.5V to 5.5V, ILOAD = 1mA, VOUT = 1.2V Load Regulation VCC2 = 2.5V, ∆ILOAD = 1mA to 50mA, VOUT = 1.2V Dropout Voltage ILOAD = 50mA LDO Feedback Voltage ILOAD = 0mA 0.582 1 30 µA VCC2 – 0.3 V 5 mV 15 mV 0.3 ● 0.582 V 0.6 0.618 V 23 30 µA VCC2 – 0.3 V LDO2 IS Additional DC Bias for LDO2 VOUT Regulated Output Voltage 2.5V < VIN < 5.5V, 1mA < ILOAD < 50mA Line Regulation ∆VCC2 = 2.5V to 5.5V, ILOAD = 1mA, VOUT = 1.2V Load Regulation VCC2 = 2.5V, ∆ILOAD = 1mA to 50mA, VOUT = 1.2V Dropout Voltage ILOAD = 50mA LDO Feedback Voltage ILOAD = 0mA VFB 0.582 1 5 mV 15 mV 0.3 ● 0.582 0.6 V 0.618 V VCC1 – 0.2 V 0.2 V 5.5 V 4 6.5 µA 3 3.1 PowerPath Controller VTRACK Tracked Input Voltage VTRACK – VCC BATT Tracked Output Voltage at VCC BATT VBACKUP Backup Battery Voltage IBACKUP Backup Battery Bias Current VCC1 = VTRACK = 0V, VBACKUP = 2.5V VCC BATT VCC BATT Output VTRACK = 0V, VCC1 = 4V, IVCCBAT = 8mA IVCCBATT Max VCC BATT Output Current VCC1 = 2.5V BATTFAULT VCC1 High Level (Good) 3 3V < VTRACK < VCC1 – 0.2V –0.2 0 2 2.85 8 Where BATTFAULT Goes High 2.65 VCC1 Low Level (Bad) Where BATTFAULT Goes Low 2.4 Hysteresis VCC1 = 0V to 4.2V, 4.2 to 0V V mA 2.8 2.9 2.5 2.6 0.3 V V V I2C Interface fI2C(MAX) Maximum I2C Operating Frequency (Note 5) 400 kHz tBUF Bus Free Time Between Stop and Start Condition (Note 5) 1.3 µs tHD(RSTA) Hold Time After (Repeated) Start Condition (Note 5) 600 ns 3445fa 3 LTC3445 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = VCC2 = 3.6V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS tSU(RSTA) Repeated Start Condition Setup Time tSU(STOP) tHD(DIN) MIN TYP MAX UNITS (Note 5) 600 ns Stop Condition Setup Time (Note 5) 600 ns Data Hold Time, Input (Note 5) 0 ns tSU(DAT) Data Setup Time (Note 5) 100 ns VTHR SCL and SDA Logic Input Threshold VHYS SCL and SDA Logic Input Hysteresis (Note 5) ILVTRACK VTRACK Leakage VCC = 3.6V 2.2 µA ILVBACKUP VBACKUP Leakage VCC = 3.6V ● 1 µA ILADD7 ADD7 Leakage VCC = 3.6V ● 1 µA ILADD6 ADD6 Leakage VCC = 3.6V ● 1 µA ILSCL SCL Leakage VCC = 3.6V ● 1 µA ILSDA SCL Leakage VCC = 3.6V ● 1 µA ILLDO1 LDO1 Leakage VCC = 3.6V, RUN = 0 ● 1 µA ILLDO2 LDO2 Leakage VCC = 3.6V, RUN = 0 ● 1 µA ILLDO1FB LDO1FB Leakage VCC = 3.6V, RUN = 0 ● 1 µA ILLDO2FB LDO2FB Leakage VCC = 3.6V, RUN = 0 ● 1 µA ILBATTFAULT BATTFAULT Leakage VCC = 3.6V ● 1 µA IFB1,2 LDO Feedback Input Current VFB1 = 0.6V ● 1 µA 1.8 V 50 mV 1.44 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3445EUF is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature, TA, and power dissipation, PD, according to the following formula: TJ = TA + PD • 37°C/W Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Note 5: Determined by design, not production tested. U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage VOUT vs DAC 500 1.6 0mA 600mA 1.5 300 ONE LDO TWO LDOs 1.3 1.2 1.1 1.0 100 0 2.4 100mA 1.4 BUCK 200 0.014 VOUT(N) – VOUT(N–1) (V) ALL ON VOUT (V) SUPPLY CURRENT (µA) 400 VOUT Step Size vs DAC 0.016 RUN = HIGH 2.8 4.4 4.8 3.2 3.6 4 SUPPLY VOLTAGE (V) 5.2 5.6 3445 G01 0.8 0.010 0.008 0.006 0.004 0.002 0.9 RUN = LOW 0.012 0 –0.002 0 10 20 30 40 50 DAC VALUE 60 70 80 3445 G02 0 10 20 30 40 50 DAC VALUE 60 70 80 3445 G03 3445fa 4 LTC3445 U W TYPICAL PERFOR A CE CHARACTERISTICS 100 1000 100 90 EFFICIENCY 80 80 50 10 DAC MAX 40 POWER LOSS 30 1.0 20 DAC MIN 10 DAC MAX 1 50 10 30 DAC MAX 20 1 VCC2 LEAKAGE CURRENT (µA) BUCK OUTPUT (V) 1.540 1.520 1.500 1.480 100 0.700 –100 500 700 300 LOAD CURRENT (mA) 0.6 0.4 0.2 –10 30 70 110 TEMPERATURE (°C) 0.8 0.6 0.4 0.2 0 –50 150 550 600 500 RDS(ON) (mΩ) SYNCHRONOUS SWITCH 30 70 110 TEMPERATURE (°C) 150 3445 G09 Main Switch RDS(ON) vs Temperature 800 VCC1 = 2.5V VCC1 = 3.6V VCC1 = 4.2V VCC1 = 5.5V 700 RDS(ON) (mΩ) 700 400 –10 3445 G08 600 900 VCC2 = 2.5V VCC2 = 3.6V VCC2 = 4.2V VCC2 = 5.5V 1.0 Synchronous Switch RDS(ON) vs Temperature MAIN SWITCH 500 700 300 LOAD CURRENT (mA) IVCC2 vs Temperature (RUN = 0V) 1.2 0.8 0 –50 900 450 100 3445 G06 VCC2 = 2.5V VCC2 = 3.6V VCC2 = 4.2V VCC2 = 5.5V 1.0 RDS(ON) vs Input Voltage RDS(ON) (mΩ) 0.750 0.1 1000 10 100 LOAD CURRENT (mA) 3445 G07 350 1.0 IVCC2 vs Temperature (RUN = VCC1) 1.2 DAC = MAX 1.460 –100 POWER LOSS 0.800 3445 G05 Buck Output Voltage vs Load Current 1.560 DAC = MIN DAC MIN 0 0.1 3445 G04 1.580 0.850 40 0.1 1000 10 100 LOAD CURRENT (mA) 100 60 10 0 0.1 DAC MIN 70 EFFICIENCY (%) 60 0.900 POWER LOSS (mW) DAC MAX POWER LOSS (mW) EFFICIENCY (%) 100 DAC MIN 70 1000 EFFICIENCY VCC2 LEAKAGE CURRENT (µA) 90 Buck Output Voltage vs Load Current Buck Efficiency and Power Loss vs Load Current, VCC1 = 4.2V BUCK OUTPUT (V) Buck Efficiency and Power Loss vs Load Current, VCC1 = 2.5V 500 400 300 VCC1 = 2.5V VCC1 = 3.6V VCC1 = 4.2V VCC1 = 5.5V 600 500 400 300 250 2.2 2.6 3 3.4 3.8 4.2 4.6 INPUT VOLTAGE (V) 5 5.4 5.8 3445 G10 200 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 3445 G11 300 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 3445 G12 3445fa 5 LTC3445 U W TYPICAL PERFOR A CE CHARACTERISTICS Buck (DAC = Min) 100mA to 300mA Load Step Slew Rates DAC Min to DAC Max Buck (DAC = Max) 100mA to 400mA Load Step BUCK VOLTAGE 50mV/DIV BUCK VOLTAGE 50mV/DIV 200mV/DIV LOAD CURRENT 100mA/DIV LOAD CURRENT 100mA/DIV 100µs/DIV 20µs/DIV 3445 G13 Buck Switching Frequency vs VCC1 Buck Switching Frequency vs Temperature 1.56 1.52 1.48 1.44 Soft-Start (DAC = Min and Max) 4.7Ω Load 2.5 3.5 4.5 5.5 1.540 BUCK OUTPUTS 500mV/DIV 1.520 1.500 1.480 1.460 200µs/DIV 1.440 –50 –25 VCC1 (V) 0 3445 G17 VCC BATT vs VCC1 6 PowerPath LDO Load Step 1mA to 5.5mA VCC BATT vs VTRACK 6 VTRACK = VBACKUP = 2V 5 4 4 VOLTAGE (V) 5 VCC BATT 3 2 3445 G18 25 50 75 100 125 150 TEMPERATURE (°C) 3445 G16 VOLTAGE (V) 3445 G15 1.560 SWITCHING FREQUENCY (MHz) SWITCHING FREQUENCY (MHz) 1.60 1.40 20µs/DIV 3445 G14 VCC1 = 5.5V VBACKUP = 2V VCC BATT 0mA 5mA VCC BATT 20mV/DIV LOAD CURRENT 10mA/DIV 3 2 VTRACK VCC1 1 1 0 200µs/DIV 3445 G21 0 0 0 VCC1 RAMP (V) VTRACK RAMP (V) 3445 G19 3445 G20 3445fa 6 LTC3445 U W TYPICAL PERFOR A CE CHARACTERISTICS LDO Reference Voltage vs Load Current LDO Reference Voltage vs Temperature 0.604 0mA 0.598 0.596 0.594 0.592 0.590 1.202 1.201 0.606 LDO OUTPUT VOLTAGE (V) LDO REFERENCE VOLTAGE (V) 0.600 0.604 VCC2 = 2.5V 0.602 VCC2 = 5.5V 0.600 0.598 0 25 50 75 100 125 150 TEMPERATURE (°C) 1.200 1.199 10mA 1.198 50mA 1.197 1.196 1.195 0.596 0 10 20 30 40 50 60 LOAD CURRENT (mA) 70 80 1.194 2.5 3.1 3.7 4.3 VCC2 (V) LDO Output Voltage vs Load Current 4.9 5.5 3445 G24 3445 G23 3445 G22 LDO Output Voltage vs Load Current 1.204 2.590 LDO OUTPUT VOLTAGE (V) LDO OUTPUT VOLTAGE (V) 2.588 2.586 2.584 2.582 VCC2 = 5.5V 2.580 VCC2 = 3.6V 2.578 1.202 1.200 VCC2 = 5.5V 1.198 VCC2 = 2.5V 1.196 2.576 2.574 1.194 0 10 20 30 40 50 60 LOAD CURRENT (mA) 70 0 80 10 20 30 40 LOAD CURRENT (mA) 50 60 3445 G26 3445 G25 LDO Dropout Voltage vs Load Current LDO Load Step (10mA to 40mA) 200 LDO DROPOUT VOLTAGE (mV) LDO REFERENCE VOLTAGE (V) 0.602 0.498 –50 –25 LDO Output Voltage vs VCC2 0.608 –50°C 25°C 150°C 160 LDO OUTPUT 20mV/DIV 120 LOAD CURRENT 20mA/DIV 80 40 0 40µs/DIV 0 10 30 40 20 LOAD CURRENT (mA) 3445 G29 50 3445 G28 3445fa 7 LTC3445 U U U PI FU CTIO S VTRACK (Pin 1): Supply Sense that VCC BATT Tracks when above 3V. Must be ≤ VCC1. NC (Pin 13): Not Connected. VBACKUP (Pin 2): Back-Up Battery Input. RUN (Pin 15): Chip Enable. 1.5V enables the part. Forcing this pin below 0.3V shuts down the device. In shutdown, all functions are disabled, drawing <35µA supply current. Do not leave RUN floating. Must be ≤ VCC1. VCC1 (Pins 3, 10): Power Supply (2.5V to 5.5V). Both VCC1 pins must be connected externally to the 2.5V to 5.5V supply. PGOOD (Pin 4): Fault Report (Undervoltage). Open-drain driver sinks current whenever LDO1, LDO2 or buck outputs are low. ADD7 (Pin 5): I2C Strappable Address (Bit 7)—VCC1 or ground. SDA (Pin 6): I2C Data Input. NC (Pin 7): Not Connected. SCL (Pin 8): I2C Clock Input. SW (Pin 14): Buck Regulator Switch. NC (Pin 16): Not Connected. FB (Pin 17): Buck Regulator Feedback. VCC BATT (Pin 18): VCC BATT PowerPath Output. BATTFAULT (Pin 19): Open-Drain Output. It is low when VCC1 is low. LDO1FB (Pin 20): LDO1 Regulator Sense. LDO1 (Pin 21): LDO1 Regulator Output. VCC2 (Pin 22): LDO Regulator Supply Voltage. ADD6 (Pin 9): I2C Strappable Address (Bit 6)—VCC1 or ground. LDO2 (Pin 23): LDO2 Regulator Output. GND (Pin 11): Buck NFET Ground. LDO2FB (Pin 24): LDO2 Regulator Sense. NC (Pin 12): Not Connected. Exposed Pad (Pin 25): Ground. Must be soldered to PCB ground for electrical contact and optimum thermal performance. 3445fa 8 LTC3445 W FU CTIO AL DIAGRA S U U VCC CIN1 3 10 VCC1 VCC1 PWR_EN 15 6 8 VCC1 OR GND VCC1 OR GND 5 9 RUN SDA SCL ADD7 ADD6 I2C VREF DAC STRAPPABLE STRAPPABLE SLEW CONTROL BUCK REGULATOR SOFT-START VOUT CONTROL 0.6V VCC 4 VCC BUCK/LDO ENABLE BURST POWER FOR ALL EXCEPT LDOs AND BUCK PFET 22 PGOOD VREF SW OSC ADJUST FB L1 14 17 C1 GND GND SPREAD SPECTRUM POWER GOOD FB SW 11 VCC2 POWER FOR LDOs LDO1 REF EXPOSED PAD 25 LDO1 OUT OUT LD01FB FB 21 R1 20 C11 R2 LDO2 REF LDO2 OUT OUT LD02FB FB 23 R3 24 C21 R4 VCC1 1 VBACKUP 3V COIN CELL + 2 VTRACK PowerPath LDO PowerPath CONTROL POWER SWITCH DRIVER POWER SWITCH VBACKUP VBACKUP VCC BATT BATTFAULT 18 19 3445 F01 Figure 1 3445fa 9 LTC3445 W FU CTIO AL DIAGRA S U U VCC1 VFB PEAK CURRENT LEVEL REFERENCE EA RS VREF ICOMP OSC S Q R QB PFET L SW LOGIC L BURST NFET IRCOMP 3445 F02 Figure 2. Buck Regulator Detail 3445fa 10 LTC3445 WU W TI I G DIAGRA SDA tSU(DAT) tSU(STA) tHD(DAT) tLOW tBUF tHD(STA) tSUSTO 3445 TD SCL tHIGH tHD(STA) tr tf START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION I2C Fast Mode Timing Specifications (for Reference) SYMBOL PARAMETER fI2C(MAX) Maximum I2C Operating Frequency MIN tBUF Bus Free Time Between Stop and Start Condition 1.3 µs tHD(RSTA) Hold Time After (Repeated) Start Condition 0.6 µs tSU(RSTA) Repeated Start Condition Setup Time 0.6 µs tSU(STOP) Stop Condition Setup Time 0.6 tHD(DAT) Data Hold Time 0 tSU(DAT) Data Setup Time 100 ns tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 0.6 µs tSP Pulse Width of Spikes Suppressed by Input Filter tf tr 0 TYP MAX UNITS 400 kHz µs 0.9 ns 0 50 ns Clock, Data Fall Time (Note 1) 20 + 0.1 • CB 300 ns Clock, Data Rise Time (Note 1) 20 + 0.1 • CB 300 ns Note 1: CB = Capacitance of one bus line. U OPERATIO (refer to Figure 1) BUCK REGULATOR Main Control Loop The LTC3445 uses a constant or spread spectrum frequency, current mode step-down architecture (Figure 2). Both the main (P-channel MOSFET) and synchronous (N-channel MOSFET) switches are internal. During normal operation, the internal top power MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP resets the RS latch is controlled by the output of error amplifier EA. When the load current increases, it causes a slight decrease in the feedback voltage, FB, relative to an internal reference voltage, which in turn, causes the EA’s output voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator IRCMP, or the beginning of the next clock cycle. 3445fa 11 LTC3445 U OPERATIO (refer to Figure 1) Burst Mode Operation 1400 1300 In Burst Mode operation, the peak current of the inductor is set to approximately 200mA regardless of the output load. Each burst event can last from a few cycles at light loads to almost continuous cycling with short sleep intervals at moderate loads. In between these burst events, the power MOSFETs and any nonessential circuitry are turned off, reducing the buck regulator’s quiescent current to 6µA. In this sleep state, the load current is being supplied solely from the output capacitor. As the output voltage droops, the EA’s output rises above the sleep threshold, signaling the BURST comparator to trip and turn the top MOSFET on. This process repeats at a rate that is dependent on the load demand. Short-Circuit Protection When the output is shorted to ground, the frequency of the oscillator is reduced to about 300kHz. This frequency foldback ensures that the inductor current has more time to decay, thereby preventing current runaway. The oscillator’s frequency will progressively increase to 1.5MHz when VOUT rises above 0V. Low Supply Operation The LTC3445 will operate with input supply voltages as low as 2.5V, but the maximum allowable output current is reduced at this low voltage. Figure 3 shows the reduction in the typical maximum output current as a function of input voltage for various output voltages. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles >40%. However, the LTC3445 uses a patent-pending scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. MAXIMUM LOAD CURRENT (mA) The LTC3445 is capable of Burst Mode operation, in which the internal power MOSFETs operate intermittently based on load demand. 1200 DAC (MIN) 1100 DAC (MAX) 1000 900 800 700 600 500 400 2.5 3 3.5 4.5 4 VCC1 (V) 5 5.5 3445 F03 Figure 3. Buck Maximum Peak Current vs VCC1 Spread Spectrum The LTC3445 has a spread spectrum mode that can be enabled via two register bits. In the spread spectrum mode, the switching frequency is dithered about a center frequency of 1.5MHz. Spread spectrum lowers noise at the regulated output and at the input. Figure 4 shows the noise reduction capabilities of the LTC3445 in spread spectrum mode. The percent spread of the frequency is controlled by two bits in register 5. 00 = 0% Spread 01 = 7.4% Spread 10 = 14.8% Spread 11 = 22.4% Spread DAC The buck output voltage is controlled by programming a 6-bit DAC register (REG0[5:0]) and GO bit (REG2[0]). The output voltage range is 0.85V to 1.55V in ~15mV steps. The DAC setting range is from 0 to 48. Any settings above 48 will default to the 48 settings value. When the desired DAC setting is loaded, the GO bit needs to be changed from 0 to 1. Once the GO bit transition occurs, VOUT will begin to change to the DAC setting loaded at that instant. Slew Rate A 2-bit register is used to control the rate of change of VOUT between DAC settings. The slew rate is controlled by stepping VOUT to its new setting using a series of 3445fa 12 LTC3445 U OPERATIO (refer to Figure 1) SPR = 00 (Spread Spectrum OFF) NOISE 10dBm/DIV SPR = 10 NOISE 10dBm/DIV START FREQ: 100kHz, RBW: 10kHz, STOP FREQ: 30MHz START FREQ: 100kHz, RBW: 10kHz, STOP FREQ: 30MHz SPR = 01 SPR = 11 NOISE 10dBm/DIV NOISE 10dBm/DIV START FREQ: 100kHz, RBW: 10kHz, STOP FREQ: 30MHz START FREQ: 100kHz, RBW: 10kHz, STOP FREQ: 30MHz Figure 4. LTC3445 Output Noise Spectrum micro-steps. The table below shows the register settings and corresponding slew rates. REG1 [1:0] 00 01 10 11 SLEW RATE (mV/µs) 11.3 7.5 3.8 0.9 It should be noted that during DAC transistions, PGOOD fault reporting is disabled. LDO OPERATION Adjustable Operation The LTC3445 contains two 50mA LDOs with an output voltage range of 0.6V to (VCC2 – 0.3V). The output voltage is set by the ratio of two external resistors as shown in Figure 1. Each LDO servos the output voltage (Pin LDOx) in order to maintain a feedback voltage (Pin LDOxFB) of 0.6V. The current in R1 and R2 is then equal to 0.6V/R2. The regulated voltage is equal to: VOUT = (0.6V/R2) • (R1+R2) Frequency Compensation The LT3445 is frequency compensated by an internal dominant pole. An output capacitor of 2µF to 10µF is usually large enough to provide good stability. In order to insure stability, a feedforward capacitor may be needed between the output pin and the feedback pin. This cancels the pole formed by the stray capacitance in large value feedback resistors. Also, a feedback capacitor minimizes noise pickup and improves ripple rejection. PowerPath OPERATION The output of the PowerPath (VCC BATT) is controlled by a combination of three inputs: main battery (VCC1), VTRACK, and VBACKUP. 3445fa 13 LTC3445 U OPERATIO (refer to Figure 1) When VCC1 rises above 2.8V, the PowerPath’s LDO is enabled and set to the lesser of 3V or VCC1. Once VTRACK is 3V or higher, it controls the PowerPath’s LDO output (VCC BATT) voltage to within 200mV of VTRACK. Note that VTRACK needs to be less than or equal to VCC1. When VTRACK falls below 3V, VCC1 is used to regulate the PowerPath’s LDO (VCC BATT) to 3V. When VCC1 falls below 2.4V, the PowerPath LDO is disconnected and VBACKUP is connected to VCC BATT. Figure 5 I2C Bus and SMBus are reasonably similar examples of 2-wire, bidirectional, serial communications busses. Calling them 2-wire is not strictly accurate, as there is an implied third wire, which is the ground line. Large ground drops or spikes between the grounds of different parts on the bus can interrupt or disrupt communications, as the signals on the two wires are both inherently referenced to a ground which is expected to be common to all parts on the bus. Both bus types have one data line and one clock line which are externally pulled to a high voltage when they are not being controlled by a device on the bus. The devices on the bus can only pull the data and clock lines low, which makes it simple to detect if more than one device is trying to control the bus; eventually, a device will release a line and it will not pull high because another device is still holding it low. Pull-ups for the data and clock lines are usually provided by external discrete resistors, but external current sources can also be used. Since there are no dedicated lines to use to tell a given device if another device is trying to communicate with it, each device must have a unique address to which it will respond. The first part of any communication is to send out an address on the bus and wait to see if another device responds to it. After a response is detected, meaningful data can be exchanged between the parts. Simple 2-wire interface Multiple devices on same bus Idle bus must have SDA and SCL lines high LTC3445 is read/write Master controls bus Devices listen for unique address that precedes data Typically, one device will control the clock line at least most of the time and will normally be sending data to the other parts and polling them to send data back to it, and this device is called the master. There can certainly be more than one master, since there is an effective protocol to resolve bus contentions, and non-master (slave) devices can also control the clock to delay rising edges and give themselves more time to complete calculations or communications (clock stretching). Slave devices need to The PowerPath’s fault detection circuit uses an open-drain driver (BATTFAULT) to report when the main battery is disconnected. Figure 5 shows the different states of the PowerPath circuits. Typically, VBACKUP is a coin cell; however, other types of back up power supplies may be used. BATTFAULT = 1 4.2V 3.6V 3V 2.8V VBACKUP 2.4V VCC1 VTRACK 0V 3445 F05 I2C OPERATION • • • • • • General I2C Bus/SMBus Description SDA SCL S START CONDITION 1-7 ADDRESS 8 9 R/W ACK 1-7 DATA 8 9 ACK 1-7 DATA 8 9 ACK P STOP CONDITION 3445 F06 Figure 6. Typical 2-Wire Serial I2C Waveforms 3445fa 14 LTC3445 U OPERATIO (refer to Figure 1) be able to control the data line to acknowledge communications from the master, and some devices will need to able to send data back to the master; they will be in control of the data line while they are doing so. Many slave devices will have no need to stretch the clock signal and will have no ability to pull the clock line low, which is the case with the LTC3445. The START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. Data is exchanged in the form of bytes, which are 8-bit packets. Any byte needs to be acknowledged by the slave (data line pulled low) or not acknowledged by the master (data line left high), so communications are broken up into 9-bit segments, one byte followed by one bit for acknowledging. For example, sending out an address consists of 7 bits of device address, 1 bit that signals whether a read or write operation will be performed, and then 1 more bit to allow the slave to acknowledge. There is no theoretical limit to how many total bytes can be exchanged in a given transmission. Acknowledge The acknowledge signal is used for handshaking between the master and the slave. An acknowledge signal (LOW active) as generated by the slave lets the master know that the latest byte of information was received. The acknowledge-related clock pulse is generated by the master. The transmitter master releases the SDA line (HIGH) during the acknowledge clock pulse. The slave receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. I2C and SMBus are very similar specifications, SMBus having been derived from I2C. In general, SMBus is targeted to low power devices (particularly battery-powered ones) and emphasizes low power consumption, while I2C is targeted to higher speed systems where the power consumption of the bus is not so critical. I2C has three different specifications for three different maximum speeds, these being standard mode (100kHz max), fast mode (400kHz max) and HS mode (3.4MHz max). Standard and fast mode are not radically different, but HS mode is very different from a hardware and software perspective and requires an initiating command at standard or fast speed before data can start transferring at HS speed. SMBus simply specifies a 100kHz maximum speed. When a slave receiver doesn’t acknowledge the slave address (for example, it’s unable to receive because it’s performing some real-time function), the data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If a slave receiver does acknowledge the slave address but, some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition. The WRITE BYTE PROTOCOL 1 START 7 1 AA01011 8 1 WR ACK XXXXXAAA S 0 SLAVE ADDRESS 0 8 1 REGISTER ADDRESS ACK 1 DDDDDDDD S 0 DATA BYTE 1 ACK STOP S 0 READ BYTE PROTOCOL 1 START 7 1 AA01011 SLAVE ADDRESS 0 8 1 WR ACK S 0 1 1 XXXXXAAA REGISTER ADDRESS ACK START S 0 7 1 AA01011 SLAVE ADDRESS 1 8 1 RD ACK S 0 1 DDDDDDDD DATA BYTE 1 ACK M 1 STOP 3445 G07 Figure 7 3445fa 15 LTC3445 U OPERATIO (refer to Figure 1) data line is also left high by the slave and master after a slave has transmitted a byte of data to the master in a read operation, but this is a not-acknowledge that indicates that the data transfer is successful. 12C Register Definitions (POR = 00 for all registers) REG 0 7 7 0 (Logic Low) 6 0 (Logic Low) 6 0 (Logic Low) 5 Buck DAC5 5 0 (Logic Low) 4 Buck DAC4 4 0 (Logic Low) 3 Buck DAC3 3 0 (Logic Low) 2 Buck DAC2 2 0 (Logic Low) 1 Buck DAC1 1 Slew Rate 1 0 Buck DAC0 0 Slew Rate 0 REG 2 The LTC3445 supports read byte and write byte commands. For the ACK bits, an S indicates that the slave is pulling the data line low and an M indicates that the master is effectively acknowledging by leaving the data line high. Data Transfer Timing for Write Commands REG 1 0 (Logic Low) Commands Supported REG 3 In order to help assure that bad data is not written into the part, data from a write command is only stored after a valid acknowledge has been performed. The part will detect that SDA is low on the rising edge of SCL that marks the end of the period in which the LTC3445 acknowledges the data write and then latch the data during the following SCL low period. REG 5 7 0 (Logic Low) 7 PGOOD Blank Disable 7 0 (Logic Low) 6 0 (Logic Low) 6 0 (Logic Low) 6 % SPR1 5 0 (Logic Low) 5 0 (Logic Low) 5 % SPR0 4 STATUS—Buck Thermal Shutdown 4 0 (Logic Low) 4 (Logic Low) 3 STATUS—Buck PGOODb 3 BURST Mode 3 (Logic Low) 2 STATUS—LDO2 PGOODb 2 LDO2 Disable 2 (Logic Low) 1 STATUS—LDO1 PGOODb 1 LDO1 Disable 1 (Logic Low) 0 Buck Update (GO Bit) 0 Buck Disable 0 (Logic Low) 3445fa 16 LTC3445 U W U U APPLICATIO S I FOR ATIO BUCK REGULATOR The basic LTC3445 application circuit is shown on the first page of this data sheet. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Table 1 MANUFACTURER PART NUMBER Inductor Selection For most applications, the value of the inductor will fall in the range of 1µH to 4.7µH. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple currents. Higher VCC1 or lower VOUT also increases the ripple current as shown in Equation 1. A reasonable starting point for setting ripple current is ∆IL = 240mA (40% of 600mA). ⎛ V ⎞ 1 VOUT ⎜ 1 – OUT ⎟ ∆IL = ( f)(L) ⎝ VCC1 ⎠ requirements and any radiated field/EMI requirements than on what the LTC3445 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3445 applications. (1) The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 720mA rated inductor should be enough for most applications (600mA + 120mA). For better efficiency, choose a low DC-resistance inductor. The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 200mA. Lower inductor values (higher ∆IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size VALUE DCR MAX DC SIZE (µH) (mΩ MAX) (A) L × W × H (mm3) Sumida CDRH3D16/ HP2R2 2.2 72 1.2 4.0 × 4.0 × 1.8 Sumida CR434R7 4.7 109 1.15 4.0 × 4.5 × 3.5 TDK TDK7030T2R2M5R4 2.2 12 5.5 7.3 × 6.8 × 3.2 Coilcraft D03316P-222 2.2 12 7 12.45 × 9.4 × 5.21 CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VCC1. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: 1/ 2 VOUT ( VCC1 – VOUT )] [ CIN required IRMS ≅ IOMAX VCC1 (2) This formula has a maximum at VCC1 = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple ∆VOUT is determined by: ⎛ 1 ⎞ ∆VOUT ≅ ∆IL ⎜ ESR + ⎟ ⎝ 8 fCOUT ⎠ (3) 3445fa 17 LTC3445 U W U U APPLICATIO S I FOR ATIO where f = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since ∆IL increases with input voltage. that any DAC settings above 48 defaults to the 48 setting. The DAC controls the VOUT range of 0.85V to 1.55V in ~15mV steps. The default value for VOUT is 1.35V and is reset to this value whenever VCC1 comes up. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. When the DAC’s value is changed, LTC3445 controls VOUT’s slew rate via a 2-bit RATE register. The RATE register can be updated via the I2C interface. The slew rate can be set to approximately 0.9mV/µs, 3.8mV/µs, 7.5mV/µs or 11.3mV/µs. The default value for RATE is 10mV/µs and is reset to this value whenever VCC1 comes up. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3445’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VCC1. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VCC1, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Buck Output Voltage Programming The LTC3445 has an internal resistor divider network tied to the FB pin. The output voltage is controlled by a DAC (6-bit register) whose setting is controlled by the I2C interface. The effective DAC bit range is from 0 to 48. Note The DAC and RATE values are not lost whenever the RUN pin is deasserted. Once the DAC and RATE registers are programmed, a GO bit transition is required for the buck to update. This is accomplished by changing the GO bit (REG2[0]) from logic low to a logic high. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3445 buck regulator circuits: VCC1 quiescent current and I2R losses. The VCC1 quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 8. 1. The VCC1 quiescent current is due to two components: the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the 3445fa 18 LTC3445 U W U U APPLICATIO S I FOR ATIO 1000 Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD • ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. POWER LOSS (mW) 100 10 DAC MAX DAC MIN 1 0.1 0.1 1 10 100 LOAD CURRENT (mA) 1000 3445 F08 Figure 8. Power Loss vs Load Current, VCC1 = 3.6V internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VCC1 to ground. The resulting dQ/dt is the current out of VCC1 that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VCC1 and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The regulator loop then acts to return VOUT to its steadystate value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10µF capacitor charging to 3.3V would require a 250µs rise time, limiting the charging current to about 130mA. LDO REGULATORS The LDOs in the LTC3445 are 50mA low dropout regulators with low quiescent and shutdown currents. Each device is capable of supplying 50mA at a dropout voltage of 300mV. The LDOs are current limited to greater than 50mA but less than 75mA. The output voltages of the LDOs are set with external resistive dividers according to the following formula: The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Charateristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Output Capacitance and Transient Response Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss. The LTC3445 LDOs are designed to be stable with a wide range of output capacitors. A minimum output capacitor of 2.2µF with an ESR of 3Ω or less is recommended to VLDOOUT1 = 0.6(1 + R1/R2) (4) VLDOOUT2 = 0.6(1 + R3/R4) (5) 3445fa 19 LTC3445 U W U U APPLICATIO S I FOR ATIO prevent oscillations. The LTC3445 LDOs are micropower devices and output transient response will be a function of output capacitance. Larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. PowerPath CONTROLLER The PowerPath circuitry in the LTC3445 is used to provide backup power from VBACKUP to the VCC BATT pin when VCC1 is low or disconnected. When VCC1 is below 2.8V, the PowerPath routes VBACKUP, typically a coin cell, to the VCC BATT pin. While VBACKUP is selected there is no current limiting except for a small (<5Ω) resistance from the VBACKUP input to the VCC BATT output. The LTC3445 sinks less than 6.5µA from VBACKUP when it is selected and sinks less than 0.1µA from VBACKUP when it is not selected. When VCC1 exceeds 2.8V, VBACKUP is disconnected from VCC BATT and an internal LDO regulates the VCC BATT voltage to the minimum of VCC1 or typically 3V. The internal LDO is current limited to less than 50mA, but greater than 10mA. Capacitance on the VCC BATT pin should be at least 2µF with an ESR less than 3Ω. VBACKUP will be routed to the VCC BATT output when the main battery voltage falls below 2.4V. As the main battery, VCC1, voltage drops from 3V to 2.4V, the LDO will be in dropout, VCC BATT will follow VCC1 down, rebounding to VBACKUP when VCC1 falls below 2.4V. If VCC1 is removed quickly, the capacitor on VCC BATT will limit the VCC BATT droop until VBACKUP is switched in. The VTRACK input offers the capability of the VCC BATT voltage to follow the voltage on VTRACK up to VCC1. In effect, VTRACK overrides the internal reference of the LDO, resulting in the LDO output (VCC BATT) having a gain of 1 relative to VTRACK once VTRACK exceeds a typical value of 3V. VCC BATT will follow VTRACK to within 200mV providing VTRACK does not exceed the dropout voltage of the LDO, which is powered by VCC1. VBACKUP should be present prior to VCC1 being connected. VBACKUP provides power to the BATTFAULT driver which is used to detect an absent or low VCC1. If VBACKUP is not present, the LTC3445 will be unable to pull the BATTFAULT pin low to signal a VCC1 fault condition. Output Capacitance and Transient Response The LDO used LTC3445 PowerPath is designed to be stable with a wide range of output capacitors. A minimum output capacitor of 2.2µF with an ESR of 3Ω or less is recommended to prevent oscillations. The LTC3445 PowerPath LDO is a micropower device and output transient response will be a function of output capacitance. Larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. THERMAL CONSIDERATIONS In most applications the LTC3445 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3445 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. The remaining regulators will also turn off. To ensure the LTC3445 doesn’t exceed the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = θJA • (PDBUCK + PDLDO1 + PDLDO2 + PDPowerPath) where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. 3445fa 20 LTC3445 U W U U APPLICATIO S I FOR ATIO As an example, consider the LTC3445 in dropout at an input voltage of 2.7V, an ambient temperature of 70°C, a buck load current of 600mA, LDO1 set to 1.3V with a load of 25mA, LDO2 set to 1.1V with a load of 15mA, and the PowerPath regulator at 2.5V with a load of 6µA. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 70°C is approximately 0.52Ω. Therefore, power dissipated by the part is: PD(BUCK) = ILOAD 2 • RDS(ON) = 180mW PD(LDO2) = (2.7 – 1.1)V • 0.015A = 24mW PD(PowerPath) = (2.7 – 2.5)V • 6µA = 1.2µW PD(TOTAL) = 0.239W For the QFN24 package, the θJA is 37°C/W. Thus, the junction temperature of the regulator is: TJ = 70°C + (0.239)(37) = 78.8°C which is well below the maximum junction temperature of 125°C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). FB 4. Keep the switching node, SW, away from the sensitive FB node. 5. Keep the (–) plates of CIN and COUT as close as possible. FB 17 GND 25 RUN 15 SW 14 SW NC 13 L1 VCC1 10 NC 12 CIN RUN 15 RUN NC 13 GND 11 3. Does the (+) plate of CIN1 connect to VCC1 as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. NC 16 SW 14 VCC1 10 1. The power traces, consisting of the GND trace, the SW trace, the VCC1 trace and the VCC2 trace should be kept short, direct and wide. VIA TO OUT NC 16 GND 25 When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3445. These items are also illustrated graphically in Figures 9 and 10. Check the following in your layout: 2. Does the FB pin connect directly to the output voltage reference? Ensure that there is no load current running from the reference voltage and the FB pin. PD(LDO1) = (2.7 – 1.3)V • 0.025A = 35mW FB 17 PC BOARD LAYOUT CHECKLIST COUT GND 11 CIN VIA TO FB NC 12 L1 COUT 3445 f10 VCC1 GND VOUT OUT 3445 F09 Figure 9 VCC1 BOLD LINES INDICATE HIGH CURRENT PATH Figure 10 3445fa 21 LTC3445 U W U U APPLICATIO S I FOR ATIO DESIGN EXAMPLE The buck regulator’s maximum load requirement for this application is 300mA. Although the default start-up voltage for the buck regulator is 1.35V, ripple current is greatest when the output voltage is programmed to 0.85V. For ripple currents of 200mA and the main battery at 4.2V, the required inductor value is 2.2µH (Equation 1). For best efficiency choose a 400mA or greater inductor with less than 0.3Ω series resistance. Choosing a 10µF output capacitor with an ESR of 0.25Ω will generate a ripple voltage of 52mV (Equation 3). In most cases, a ceramic capacitor’s ESR will be less than 0.25Ω further reducing the output ripple (see Figure 11). Note that as VCC1 decreases or VOUT increases, the ripple current and ripple voltage will decrease. The input capacitor, CIN, will require an RMS current rating of at least 0.150A ≅ ILOAD(MAX)/2 at temperature (Equation 2). As a design example, assume the LTC3445 is used in a single lithium-ion battery-powered Intel PXA270 microprocessor application. The battery will be operating from a maximum of 4.2V down to about 2.7V. Also, the battery will be connected to all three power pins on the LTC3445. The desired LDO outputs are 1.3V with a 23mA load and 1.1V with a 14mA load. Since both LDO’s are the same, we will select LDO1 for the 1.3V output and LDO2 for the 1.1V output. Using Equations 4 and 5, and choosing R2 and R4 to be 604k, the values for R1 and R2 are 705k and 503k respectively. Also, selecting a 10µF output capacitor provides adequate stability and transient reponses. The PXA270’s VCC BATT requirement can be readily handled by the LTC3445’s PowerPath control circuits. By simply connecting a coin cell battery to VBACKUP, the PowerPath control circuits regulate VCC BATT within the PXA270’s requirements. 3V_TYP LTC3406 BUCK SYS_EN INTEL PXA270 VCC_IO 3V COIN CELL VCC nVCC_FAULT 20k VBACKUP 20k PGOOD PWR_EN nBATT_FAULT VTRACK RUN BATTFAULT 3V VCC BATT SUMIDA CDRH3D16/HP2R2 2.2µH VCC 10µF CER 2.5V TO 5.5V LITHIUM ION VCC1 SW VCC1 FB 0.85V TO 1.55V VCC_BATT VCC_CORE 10µF CER VCC2 LTC3445 ADD7 1.3V LDO1 VCC_PLL 705k ADD6 I2C BUS 3k 10µF CER LDO1FB 604k 3k SCL 1.1V LDO2 VCC_SRAM 503k SDA 10µF CER LDO2FB 3445 F11 604k Figure 11. Design Example 3445fa 22 LTC3445 U PACKAGE DESCRIPTIO UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 ±0.05 4.50 ± 0.05 2.45 ± 0.05 3.10 ± 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.23 TYP R = 0.115 (4 SIDES) TYP 23 24 0.75 ± 0.05 0.38 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 2.45 ± 0.10 (4-SIDES) (UF24) QFN 1103 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3445fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC3445 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1761 100mA, Low Noise Micropower, LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.30V, IQ = 20µA, ISD < 1µA, VOUT = Adj, 1.5V, 1.8V, 2V, 2.5V, 2.8V, 3V, 3.3V, 5V, ThinSOTTM Package. Low Noise < 20µVRMS(P-P), Stable with 1µF Ceramic Capacitors LT1762 150mA, Low Noise Micropower, LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.30V, IQ = 25µA, ISD < 1µA, VOUT = Adj, 2.5V, 3V, 3.3V, 5V, MS8 Package. Low Noise < 20µVRMS(P-P) LT1763 500mA, Low Noise Micropower, LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.30V, IQ = 30µA, ISD < 1µA, VOUT = 1.5V, 1.8V, 2.5V, 3V, 3.3V, 5V, S8 Package. Low Noise < 20µVRMS(P-P) LTC1844 150mA, Very Low Dropout LDO VIN: 6.5V to 1.6V, VOUT(MIN) = 1.25V, Dropout Voltage = 0.08V, IQ = 40µA, ISD < 1µA, VOUT = Adj, 1.5V, 1.8V, 2.5V, 2.8V, 3.3V, ThinSOT Package. Low Noise < 30µVRMS(P-P), Stable with 1µF Ceramic Capacitors LT1962 300mA, Low Noise Micropower, LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.27V, IQ = 30µA, ISD < 1µA, VOUT = 1.5V, 1.8V, 2.5V, 3V, 3.3V, 5V, MS8 Package. Low Noise < 20µVRMS(P-P) LT3020 Low VIN (0.9V) Low VOUT (0.2V) VLDOTM VIN: 0.9V to 10V, VOUT(MIN) = 0.20V, Dropout Voltage = 0.15V, IQ = 120µA, ISD < 1µA, VOUT = Adj, DFN Package LTC3405/LTC3405A 300mA (IOUT), 1.5MHz Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20µA, ISD < 1µA, ThinSOT Package LTC3406/LTC3406B 600mA (IOUT), 1.5MHz Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20µA, ISD < 1µA, ThinSOT Package LTC3407 Dual 600mA, 1.5MHz Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, ISD < 1µA, MS10E Package LTC3411 1.25A (IOUT), 4MHz Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA, ISD < 1µA, MS10 Package LTC3412 2.5A (IOUT), 4MHz Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA, ISD < 1µA, TSSOP16E Package LTC3455 Dual DC/DC Converter with USB Power Manager and Li-Ion Battery Charger VIN: 3V to 5.5V, Seamless Transition Between Input Sources and Li-Ion Battery, USB, 5V Wall Adapter, QFN24 Package LTC4055 USB Power Manager and Li-Ion Battery Charger Standalone Charger, Automatic Switchover when Input Supply is Removed LTC4411/LTC4412 PowerPath Controllers in ThinSOT More Efficient than Diode ORing ThinSOT and VLDO are trademarks of Linear Technology Corporation. 3445fa 24 Linear Technology Corporation LT/LT 0705 REV A • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004