TI SN74AC04MDREP

SCAS717 − OCTOBER 2003
D Controlled Baseline
D
D
D
D
− One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
D 2-V to 6-V VCC Operation
D Inputs Accept Voltages to 6 V
D Max tpd of 7 ns at 5 V
D PACKAGE
(TOP VIEW)
1A
1Y
2A
2Y
3A
3Y
GND
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
6A
6Y
5A
5Y
4A
4Y
description/ordering information
The SN74AC04 contains six independent inverters. The device performs the Boolean function Y = A.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE‡
TA
TOP-SIDE
MARKING
−55°C to 125°C
SOIC − D
Tape and reel
SN74AC04MDREP
SAC04MEP
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram, each inverter (positive logic)
A
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
!"# $%
$ ! ! & ' $$ ()% $ !* $ #) #$
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1
SCAS717 − OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, Tstg (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. Long-term high−temperature storage and/or extended use at maximum recommended operating conditions may result in a
reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
VI
VO
IOH
IOL
∆t /∆v
MIN
MAX
2
6
Input voltage
3.15
0.9
1.35
Low-level output current
Input transition rise or fall rate
V
1.65
0
High-level output current
V
3.85
0
Output voltage
V
2.1
VCC = 4.5 V
VCC = 5.5 V
Low-level input voltage
UNIT
VCC
VCC
VCC = 3 V
VCC = 4.5 V
−12
VCC = 5.5 V
VCC = 3 V
−24
VCC = 4.5 V
VCC = 5.5 V
24
−24
V
V
mA
12
mA
24
8
ns / V
TA
Operating free-air temperature
−55
125
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCAS717 − OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −50 µA
VOH
VOL
IOH = −12 mA
VCC
MIN
TA = 25°C
TYP
MAX
MIN
3V
2.9
2.99
2.9
4.5 V
4.4
4.49
4.4
5.5 V
5.4
5.49
5.4
3V
2.56
2.4
MAX
V
4.5 V
3.86
3.7
IOH = −24 mA
5.5 V
4.86
4.7
3V
0.002
0.1
0.1
IOL = 50 µA
4.5 V
0.001
0.1
0.1
5.5 V
0.001
IOL = 12 mA
IOL = 24 mA
II
ICC
VI = VCC or GND
VI = VCC or GND,
Ci
VI = VCC or GND
IO = 0
0.1
0.1
3V
0.36
0.5
4.5 V
0.36
0.5
5.5 V
0.36
0.5
5.5 V
± 0.1
±1
µA
5.5 V
2
40
µA
2.8
switching characteristics over recommended operating
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
MIN
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
temperature
TA = 25°C
TYP
MAX
MIN
MAX
1.5
4.5
9
1
11
1.5
4.5
8.5
1
10
free-air
MIN
V
pF
free-air
switching characteristics over recommended operating
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
UNIT
temperature
TA = 25°C
TYP
MAX
MIN
MAX
1.5
4
7
1
8.5
1.5
3.5
6.5
1
7.5
range,
UNIT
ns
range,
UNIT
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
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f = 1 MHz
TYP
45
UNIT
pF
3
SCAS717 − OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
TEST
tPLH/tPHL
S1
Open
From Output
Under Test
CL = 50 pF
(see Note A)
S1
Open
50% VCC
50% VCC
0V
tPHL
tPLH
2 × VCC
500 Ω
VCC
Input
(see Note B)
In-Phase
Output
50% VCC
tPLH
tPHL
500 Ω
Out-of-Phase
Output
LOAD CIRCUIT
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
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