L29C525 L29C525 DEVICES INCORPORATED Dual Pipeline Register Dual Pipeline Register DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ DESCRIPTION Dual 8-Deep Pipeline Register Configurable to Single 16-Deep Low Power CMOS Technology Replaces AMD Am29525 Load, Shift, and Hold Instructions Separate Data In and Data Out Pins Three-State Outputs Package Styles Available: • 28-pin Plastic DIP • 28-pin Plastic LCC, J-Lead The L29C525 is a high-speed, low power CMOS pipeline register. It is pin-for-pin compatible with the AMD Am29525. The L29C525 can be configured as two independent 8-level pipelines or as a single 16-level pipeline. The configuration implemented is determined by the instruction code (I1-0) as shown in Table 2. The I1-0 instruction code controls the internal routing of data and loading of each register. For instruction I1-0 = 00 (Push A and B), data applied at the D 7-0 inputs is latched into register A0 on the rising edge of CLK. The contents of A0 simultaneously move to register A1, A1 moves to A2, and so on. The contents of register A7 are wrapped back to register B0. The registers on the B side are similarly shifted, with the contents of register B7 lost. Instruction I1-0 = 01 (Push B) acts similarly to the Push A and B instruction, except that only the B side registers are shifted. The input data is applied to register B0, and the contents of register B7 are lost. The contents of the A side registers are unaffected. Instruction I1-0 = 10 (Push A) is identical to the Push B instruction, except that the A side registers are shifted and the B side registers are unaffected. Instruction I1-0 = 11 (Hold) causes no internal data movement. It is equivalent to preventing the application of a clock edge to any internal register. The contents of any of the registers is selectable at the output through the use of the S3-0 control inputs. The independence of the I and S control lines allows simultaneous reading and writing. Encoding for the S3-0 controls is given in Table 3. 2 REGISTER B7 REGISTER B6 REGISTER B5 REGISTER B4 REGISTER B3 REGISTER B2 REGISTER B1 REGISTER B0 MUX CLK A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 MUX REGISTER A7 REGISTER A6 REGISTER A5 REGISTER A4 REGISTER A3 8 I 1-0 REGISTER A2 D 7-0 REGISTER A1 REGISTER A0 L29C525 BLOCK DIAGRAM Y 7-0 8 OE S 3-0 4 Pipeline Registers 1 03/23/2000–LDS.29C525-G L29C525 DEVICES INCORPORATED TABLE 1. Dual Pipeline Register REGISTER LOAD OPERATIONS Single 16 Level Dual 8 Level Push A and B Push B Push A HOLD A0 A1 A2 A3 A4 A5 A6 A7 TABLE 2. B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A2 A3 A4 A5 A6 A7 INSTRUCTION SET TABLE 3. Inputs Hold All Registers HOLD HOLD HOLD B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 OUTPUT SELECT S3 S2 S1 S0 Y7-0 Mnemonics I1 I0 Description 0 0 0 0 A0 Shift 0 0 Push A and B 0 0 0 1 A1 LDB 0 1 Push B 0 0 1 0 A2 LDA 1 0 Push A 0 0 1 1 A3 HLD 1 1 Hold All Registers 0 1 0 0 A4 0 1 0 1 A5 0 1 1 0 A6 0 1 1 1 A7 1 0 0 0 B0 1 0 0 1 B1 1 0 1 0 B2 1 0 1 1 B3 1 1 0 0 B4 1 1 0 1 B5 1 1 1 0 B6 1 1 1 1 B7 Pipeline Registers 2 03/27/2000–LDS.29C525-G L29C525 DEVICES INCORPORATED Dual Pipeline Register MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Active Operation, Commercial Active Operation, Military Supply Voltage 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –12 mA 2.4 VOL Output Low Voltage VCC = Min., IOL = 24 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current IOZ Typ Max Unit V 0.5 V 2.0 VCC V 0.0 0.8 V Ground ≤ VIN ≤ VCC (Note 12) ±20 µA Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 35 mA ICC2 VCC Current, Quiescent (Note 7) 1.0 mA 10 Pipeline Registers 3 03/32/2000–LDS.29C525-G L29C525 DEVICES INCORPORATED Dual Pipeline Register SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) L29C525– 20 Symbol Parameter Min 15 Max Min Max tPD Clock to Output Delay 20 15 tSEL Select to Output Delay 20 15 tPW Clock Pulse Width 12 10 tSD Data Setup Time 7 5 tHD Data Hold Time 0 0 tSI Instruction Setup Time 7 5 tHI Instruction Hold Time 2 tENA Three-State Output Enable Delay (Note 11) 15 15 tDIS Three-State Output Disable Delay (Note 11) 13 13 2 MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) Symbol 1234567890123456789012345678901 L29C525– 1234567890123456789012345678901 1234567890123456789012345678901 * 25 20* 1234567890123456789012345678901 1234567890123456789012345678901 1234567890123456789012345678901 Min Max Min Max 1234567890123456789012345678901 1234567890123456789012345678901 25 20 1234567890123456789012345678901 1234567890123456789012345678901 1234567890123456789012345678901 1234567890123456789012345678901 25 20 1234567890123456789012345678901 1234567890123456789012345678901 12 12 1234567890123456789012345678901 1234567890123456789012345678901 1234567890123456789012345678901 7 7 1234567890123456789012345678901 1234567890123456789012345678901 1234567890123456789012345678901 2 2 1234567890123456789012345678901 1234567890123456789012345678901 1234567890123456789012345678901 7 7 1234567890123456789012345678901 1234567890123456789012345678901 1234567890123456789012345678901 2 2 1234567890123456789012345678901 1234567890123456789012345678901 1234567890123456789012345678901 15 15 1234567890123456789012345678901 1234567890123456789012345678901 13 13 1234567890123456789012345678901 1234567890123456789012345678901 Parameter tPD Clock to Output Delay tSEL Select to Output Delay tPW Clock Pulse Width tSD Data Setup Time tHD Data Hold Time tSI Instruction Setup Time tHI Instruction Hold Time tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) SWITCHING WAVEFORMS tSD tHD tSI tHI D7-0 I1-0 tPW tPW CLK tPD S3-0 tSEL OE tDIS tENA HIGH IMPEDANCE Y7-0 1234567890123456789 1234567890123456789 1234567890123456789 *DISCONTINUED SPEED GRADE Pipeline Registers 4 03/27/2000–LDS.29C525-G L29C525 DEVICES INCORPORATED Dual Pipeline Register NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of I OH and I OL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and ac12. These parameters are only tested at cumulations of static charge. Neverthethe high temperature extreme, which is less, conventional precautions should the worst case for leakage current. be observed during storage, handling, FIGURE A. OUTPUT LOADING CIRCUIT and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. S1 As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following DUT IOL transient undershoot and overshoot. In- measures are recommended: VTH CL put levels below ground or above VCC IOH will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test FIGURE B. THRESHOLD LEVELS range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tENA tDIS tion will not be adversely affected, how- should be installed between device VCC OE 1.5 V 1.5 V ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 3.5V Vth 0 Z 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a min- 1.5 V 1.5 V Z 1 VOL* 0.2 V VOH* 0.2 V 0 Z 1 Z 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 5 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency Pipeline Registers 5 03/32/2000–LDS.29C525-G L29C525 DEVICES INCORPORATED Dual Pipeline Register ORDERING INFORMATION 28-pin — 0.3" wide Speed 28 27 26 25 24 23 22 21 20 19 18 17 16 15 S2 S3 Y0 Y1 Y2 Y3 VCC GND OE Y4 Y5 Y6 Y7 I1 D1 D0 S0 S1 S2 S3 Y0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D2 D3 VCC GND D4 D5 D6 Plastic DIP (P10) 4 3 2 1 28 27 26 25 6 7 8 9 Y1 Y2 Y3 VCC GND OE Y4 24 Top View 23 22 21 10 20 11 19 12 13 14 15 16 17 18 Plastic J-Lead Chip Carrier (J4) 0°C to +70°C — COMMERCIAL SCREENING 0°C to +70°C — COMMERCIAL SCREENING 20 ns 15 ns 5 D7 I0 CLK I1 Y7 Y6 Y5 S1 S0 D0 D1 D2 D3 VCC GND D4 D5 D6 D7 I0 CLK 28-pin L29C525PC20 L29C525PC15 L29C525JC20 L29C525JC15 –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — MIL-STD-883 COMPLIANT Pipeline Registers 6 03/27/2000–LDS.29C525-G