TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 www.ti.com SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES Check for Samples: TPS2041B-Q1, TPS2042B-Q1, TPS2051B-Q1 FEATURES APPLICATIONS • • • • • • • 1 • • • • • • • • • • Qualified for Automotive Applications 70-mΩ High-Side MOSFET 500-mA Continuous Current Thermal and Short-Circuit Protection Accurate Current Limit: 0.75 A (Min), 1.25 A (Max) Operating Range: 2.7 V to 5.5 V 0.6-ms Typical Rise Time Undervoltage Lockout Deglitched Fault Report (OC) No OC Glitch During Power Up Maximum Standby Supply Current: 1 mA (Single, Dual) or 2 mA (Triple, Quad) Bidirectional Switch Junction Temperature Range: –40°C to 125°C ESD Protection Level Per AEC-Q100 Classification UL Recognized, File Number E169910 Heavy Capacitive Loads Short-Circuit Protection TPS2041B DBV PACKAGE (TOP VIEW) OUT 1 GND 2 OC 3 5 IN 4 EN TPS2042B D PACKAGE (TOP VIEW) GND IN EN1 EN2 1 8 2 7 3 6 4 5 TPS2051B D PACKAGE (TOP VIEW) OC1 OUT1 OUT2 OC2 GND IN IN EN 1 8 2 7 3 6 4 5 OUT OUT OUT OC DESCRIPTION The TPS204xB/TPS205xB power-distribution switches are intended for applications where heavy capacitive loads and short circuits are likely to be encountered. These devices incorporate 70-mΩ N-channel MOSFET power switches for power-distribution systems that require multiple power switches in a single package. Each switch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit threshold or a short is present, the device limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains off until valid input voltage is present. This power-distribution switch is designed to set current limit at 1 A (typ). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2010, Texas Instruments Incorporated TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. GENERAL SWITCH CATALOG 33 mΩ, single TPS201xA 0.2 A − 2 A TPS202x TPS203x 80 mΩ, single TPS2014 TPS2042B TPS2052B TPS2046 TPS2056 TPS2062 TPS2066 TPS2060 TPS2064 80 mΩ, dual 0.2 A − 2 A 0.2 A − 2 A 600 TPS2015 1A TPS2041B 500 TPS2051B 500 TPS2045 250 TPS2055 250 TPS2061 1A TPS2065 1A 260 mΩ mA mA mA mA mA IN1 OUT IN2 1.3 Ω 500 mA 500 mA 250 mA 250 mA 1A 1A 1.5 A 1.5 A TPS2100/1 IN1 500 mA IN2 10 mA TPS2102/3/4/5 IN1 500 mA IN2 100 mA 80 mΩ, dual TPS2080 TPS2081 TPS2082 TPS2090 TPS2091 TPS2092 500 mA 500 mA 500 mA 250 mA 250 mA 250 mA 80 mΩ, triple TPS2043B TPS2053B TPS2047 TPS2057 500 500 250 250 80 mΩ, quad mA mA mA mA TPS2044B TPS2054B TPS2048 TPS2058 500 500 250 250 mA mA mA mA 80 mΩ, quad TPS2085 TPS2086 TPS2087 TPS2095 TPS2096 TPS2097 500 mA 500 mA 500 mA 250 mA 250 mA 250 mA ORDERING INFORMATION (1) TJ –40°C to 125°C (1) (2) 2 ENABLE NO. OF SWITCHES Active high Single SOIC – D Reel of 2500 TPS2051BQDRQ1 2051BQ Single SOT-23 – DBV Reel of 3000 TPS2041QDBVRQ1 PLIQ SOIC – D Reel of 2500 TPS2042BQDRQ1 2042B Active low Dual PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 www.ti.com SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range unless otherwise noted Input voltage range (IN) (2) VI(IN) –0.3 V to 6 V VO(OUT), VO(OUTx) Output voltage range (OUT, OUTx) VI( ENx ), VI(EN) Input voltage range (ENx, EN) –0.3 V to 6 V VI( OC ), VI( OCx ) Voltage range (OC, OCx) –0.3 V to 6 V IO(OUT), IO(OUTx) Continuous output current Internally limited (2) –0.3 V to 6 V Continuous total power dissipation See Dissipation Ratings TJ Operating virtual-junction temperature range Tstg Storage temperature range –40°C to 125°C –65°C to 150°C Lead temperature, soldering 1,6 mm (1/16 in) from case for 10 s 260°C Human-Body Model (HBM) (H2) 2500 V TPS2041B Machine Model (MM) (M0) Electrostatic discharge (ESD) protection 50 V Charged-Device Model (CDM) (C5) 1500 V Human-Body Model (HBM) (H2) 2500 V TPS2042B Machine Model (MM) (M0) 50 V Charged-Device Model (CDM) (C5) 1500 V Human-Body Model (HBM) (H2) 2000 V TPS2051B Machine Model (MM) (M0) 50 V Charged-Device Model (CDM) (C5) (1) (2) 1500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. DISSIPATING RATINGS PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D-8 585.82 mW 5.8582 mW/°C 322.20 mW 234.32 mW DBV-5 285 mW 2.85 mW/°C 155 mW 114 mW RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT 2.7 5.5 V VI(IN) Input voltage (IN) VI( ENx ), VI(EN) Input voltage (ENx, EN) 0 5.5 V IO(OUT), IO(OUTx) Continuous output current (OUT, OUTx) 0 500 mA TJ Operating virtual-junction temperature –40 125 °C Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 3 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.5 A, VI(ENx) = 0 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT Power Switch rDS(on) tr tf Static drain-source on-state resistance, 5-V or 3.3-V operation VI(IN) = 5 V or 3.3 V, IO = 0.5 A Static drain-source on-state resistance, 2.7-V operation (2) VI(IN) = 2.7 V, IO = 0.5 A 70 VI(IN) = 2.7 V VI(IN) = 5.5 V (2) 135 mΩ –40°C ≤ TJ ≤ 125°C VI(IN) = 5.5 V Rise time, output (2) Fall time, output –40°C ≤ TJ ≤ 125°C CL = 1 mF, RL = 10 Ω TJ = 25°C VI(IN) = 2.7 V 75 150 0.6 1.5 0.4 1 0.05 0.5 0.05 0.5 ms Enable Input (EN, ENx ) VIH High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V VIL Low-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V II Input current VI( ENx ) = 0 V or 5.5 V 0.5 mA ton Turn-on time (2) CL = 100 mF, RL = 10 Ω 3 ms toff Turn-off time (2) CL = 100 mF, RL = 10 Ω 10 ms 2 V 0.8 –0.5 V Current Limit VI(IN) = 5 V, OUT connected to GND, device enabled into short-circuit TJ = 25°C Supply current, low-level output No load on OUT, VI(EN) = 5.5 V or VI(EN) = 0 V Supply current, high-level output No load on OUT, VI(EN) = 0 V or VI(EN) = 5.5 V Leakage current Reverse leakage current IOS Short-circuit output current 0.65 1 1.25 0.6 1 1.3 TJ = 25°C 0.5 1 –40°C ≤ TJ ≤ 125°C 0.5 5 TJ = 25°C 43 60 –40°C ≤ TJ ≤ 125°C 43 70 OUT connected to ground, VI(EN) = 5.5 V or VI(EN) = 0 V –40°C ≤ TJ ≤ 125°C 1 mA VI(OUTx) = 5.5 V, IN = ground (2) TJ = 25°C 0 mA TJ = 25°C 0.5 1 –40°C ≤ TJ ≤ 125°C 0.5 5 TJ = 25°C 50 70 –40°C ≤ TJ ≤ 125°C 50 90 –40°C ≤ TJ ≤ 125°C 1 mA 0.2 mA –40°C ≤ TJ ≤ 125°C A Supply Current (TPS2041B/TPS2051B) mA mA Supply Current (TPS2042B) Supply current, low-level output No load on OUT, VI( ENx ) = 5.5 V Supply current, high-level output No load on OUT, VI( ENx ) = 0 V Leakage current OUT connected to ground, VI( ENx ) = 5.5 V Reverse leakage current VI(OUTx) = 5.5 V, IN = ground (2) TJ = 25°C mA mA Undervoltage Lockout Low-level input voltage, IN, INx 2 Hysteresis, IN, INx TJ = 25°C 2.5 75 V mV Overcurrent (OC, OCx ) Output low voltage, VOL(/OCx) IO( OCx ) = 5 mA Off-state current (2) VO( OCx ) = 5 V or 3.3 V OC deglitch (2) OCx assertion or deassertion 4 8 0.4 V 1 mA 15 ms Thermal Shutdown (3) Thermal shutdown threshold (2) Recovery from thermal shutdown 135 (2) 125 Hysteresis (2) (1) (2) (3) 4 °C °C 10 °C Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be accounted for separately. Specified by design The thermal shutdown only reacts under overcurrent conditions. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 www.ti.com SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 DEVICE INFORMATION Terminal Functions (TPS2041B) TERMINAL NAME I/O NO. I DESCRIPTION EN 4 GND 2 Enable input, logic low turns on power switch IN 5 I Input voltage OC 3 O Overcurrent, open-drain output, active low OUT 1 O Power-switch output Ground Functional Block Diagram (TPS2041B) (See Note A) CS IN OUT Charge Pump EN Driver Current Limit OC UVLO Thermal Sense GND A. Deglitch CS = Current sense Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 5 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 www.ti.com Terminal Functions (TPS2042B) TERMINAL NAME I/O NO. DESCRIPTION EN1 3 I Enable input, logic low turns on power switch IN-OUT1 EN2 4 I Enable input, logic low turns on power switch IN-OUT2 GND 1 IN 2 I Input voltage OC1 8 O Overcurrent, open-drain output, active low, IN-OUT1 OC2 5 O Overcurrent, open-drain output, active low, IN-OUT2 OUT1 7 O Power-switch output, IN-OUT1 OUT2 6 O Power-switch output, IN-OUT2 Ground Functional Block Diagram (TPS2042B) OC1 Thermal Sense GND Deglitch EN1 Driver Current Limit Charge Pump (See Note A) CS OUT1 UVLO (See Note A) IN CS OUT2 Charge Pump Driver Current Limit OC2 EN2 Thermal Sense A. 6 Deglitch CS = Current sense Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 www.ti.com SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 Terminal Functions (TPS2051B) TERMINAL NAME EN I/O NO. 4 GND I 1 DESCRIPTION Enable input, logic high turns on power switch Ground IN 2, 3 I Input voltage OC 5 O Overcurrent open-drain output, active low 6, 7, 8 O Power-switch output OUT Functional Block Diagram (TPS2051B) (See Note A) CS IN OUT Charge Pump EN Driver Current Limit OC UVLO Thermal Sense GND A. Deglitch CS = Current sense Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 7 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION OUT RL tf tr CL VO(OUT) 90% 10% 90% 10% TEST CIRCUIT 50% VI(EN) 50% toff ton VO(OUT) 50% VI(EN) 90% 50% toff ton 90% VO(OUT) 10% 10% VOLTAGE WAVEFORMS Figure 1. Test Circuit and Voltage Waveforms RL = 10 W, CL = 1 mF TA = 255C VI(EN) VI(EN) 5 V/div VI(EN) VI(EN) 5 V/div RL = 10 W, CL = 1 mF TA = 255C VO(OUT) 2 V/div VO(OUT) 2 V/div t − Time − 500 ms/div Figure 2. Turn-On Delay and Rise Time With 1-mF Load 8 Submit Documentation Feedback t − Time − 500 ms/div Figure 3. Turn-Off Delay and Fall Time With 1-mF Load Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 www.ti.com SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 PARAMETER MEASUREMENT INFORMATION (continued) VI(EN) VI(EN) 5 V/div RL = 10 W, CL = 100 mF TA = 255C VI(EN) VI(EN) 5 V/div RL = 10 W, CL = 100 mF TA = 255C VO(OUT) 2 V/div VO(OUT) 2 V/div t − Time − 500 ms/div t − Time − 500 ms/div Figure 4. Turn-On Delay and Rise Time With 100-mF Figure 5. Turn-Off Delay and Fall Time With 100-mF Load Load VI = 5 V, RL = 10 W, TA = 255C VI(EN) VI(EN) 5 V/div VI(EN) VI(EN) 5 V/div 220 mF 470 mF IO(OUT) 500 mA/div IO(OUT) 500 mA/div 100 mF t − Time − 500 ms/div Figure 6. Short-Circuit Current, Device Enabled Into Short Copyright © 2007–2010, Texas Instruments Incorporated t − Time − 500 ms/div Figure 7. Inrush Current With Different Load Capacitance Submit Documentation Feedback Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 9 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VO(OC) 2 V/div VO(OC) 2 V/div IO(OUT) 500 mA/div IO(OUT) 500 mA/div t − Time − 2 ms/div Figure 8. 3-Ω Load Connected to Enabled Device 10 Submit Documentation Feedback t − Time − 2 ms/div Figure 9. 2-Ω Load Connected to Enabled Device Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 www.ti.com SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 TYPICAL CHARACTERISTICS TURN-ON TIME vs INPUT VOLTAGE TURN-OFF TIME vs INPUT VOLTAGE 1.0 3.3 CL = 100 mF, RL = 10 W, TA = 255C 0.9 0.8 CL = 100 mF, RL = 10 W, TA = 255C 3.2 Turnoff Time − ms Turnon Time − ms 0.7 0.6 0.5 0.4 3.1 3 0.3 0.2 2.9 0.1 0 2 3 4 5 VI − Input Voltage − V 2.8 6 3 4 5 6 VI − Input Voltage − V Figure 10. Figure 11. RISE TIME vs INPUT VOLTAGE FALL TIME vs INPUT VOLTAGE 0.25 0.6 CL = 1 mF, RL = 10 W, TA = 255C CL = 1 mF, RL = 10 W, TA = 255C 0.5 0.2 0.4 Fall Time − ms Rise Time − ms 2 0.3 0.15 0.1 0.2 0.05 0.1 0 2 3 4 5 VI − Input Voltage − V Figure 12. Copyright © 2007–2010, Texas Instruments Incorporated 6 0 2 3 4 5 VI − Input Voltage − V 6 Figure 13. Submit Documentation Feedback Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 11 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS2041B/TPS2051B SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE TPS2042B SUPPLY CURRENT, OUTPUT ENABLED vs JUNCTION TEMPERATURE 70 I I (IN) − Supply Current, Output Enabled − µ A I I (IN) − Supply Current, Output Enabled − µ A 60 VI = 5.5 V 50 VI = 5 V 40 30 VI = 2.7 V 20 VI = 3.3 V 10 0 −50 0 50 100 50 VI = 5 V VI = 3.3 V 40 30 VI = 2.7 V 20 10 0 150 VI = 5.5 V 60 −50 TPS2041B/TPS2051B SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE TPS2042B SUPPLY CURRENT, OUTPUT DISABLED vs JUNCTION TEMPERATURE I I (IN) − Supply Current, Output Disabled − µ A I I (IN) − Supply Current, Output Disabled − µ A 100 Figure 15. VI = 5.5 V 0.45 VI = 5 V 0.4 0.35 0.3 VI = 2.7 V VI = 3.3 V 0.25 0.2 0.15 0.1 0.05 0 50 100 TJ − Junction Temperature − 5C Figure 16. 12 50 Figure 14. 0.5 0 −50 0 Submit Documentation Feedback 150 TJ − Junction Temperature − 5C TJ − Junction Temperature − 5C 150 0.5 0.45 VI = 5.5 V VI = 5 V 0.4 0.35 0.3 VI = 2.7 V VI = 3.3 V 0.25 0.2 0.15 0.1 0.05 0 −50 0 50 100 TJ − Junction Temperature − 5C 150 Figure 17. Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 www.ti.com SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 TYPICAL CHARACTERISTICS (continued) SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE 1.08 120 IO = 0.5 A I OS − Short-Circuit Output Current − A r DS(on) − Static Drain-Source On-State Resistance − m Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE VI = 2.7 V 100 80 VI = 3.3 V 60 VI = 5 V 40 20 −50 0 50 100 150 1.02 1.0 0.98 VI = 5 V 0.96 0.92 0 50 100 TJ − Junction Temperature − 5C Figure 18. Figure 19. THRESHOLD TRIP CURRENT vs INPUT VOLTAGE UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE 2 150 2.3 UVLO − Undervoltage Lockout − V TA = 255C Load Ramp = 1 A/10 ms 1.8 Threshold Trip Current − A VI = 5.5 V 0.94 TJ − Junction Temperature − 5C 1.6 1.4 1.2 1 2.5 VI = 3.3 V 1.04 0.9 −50 0 VI = 2.7 V 1.06 3 3.5 4 4.5 VI − Input Voltage − V Figure 20. Copyright © 2007–2010, Texas Instruments Incorporated 5 5.5 6 UVLO Rising 2.26 2.22 UVLO Falling 2.18 2.14 2.1 −50 0 50 100 TJ − Junction Temperature − 5C 150 Figure 21. Submit Documentation Feedback Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 13 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) CURRENT-LIMIT RESPONSE vs PEAK CURRENT 100 Current-Limit Response − µ s VI = 5 V, TA = 255C 80 60 40 20 0 0 14 Submit Documentation Feedback 2.5 5 7.5 Peak Current − A Figure 22. 10 12.5 Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 www.ti.com SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 APPLICATION INFORMATION Power-Supply Considerations TPS2042B 2 Power Supply 2.7 V to 5.5 V IN OUT1 0.1 µF 8 3 5 4 7 Load 0.1 µF 22 µF 0.1 µF 22 µF OC1 EN1 OUT2 OC2 6 Load EN2 GND 1 Figure 23. Typical Application (Example, TPS2042B) A 0.01-mF to 0.1-mF ceramic bypass capacitor between IN and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-mF to 0.1-mF ceramic capacitor improves the immunity of the device to short-circuit transients. Overcurrent A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 14 and Figure 15). The TPS204xB/TPS205xB senses the short and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded (see Figure 16 and Figure 17). The TPS204xB/TPS205xB is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. OC Response The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit. The TPS204xB/TPS205xB is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned off due to an overtemperature shutdown. Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 15 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 www.ti.com V+ TPS2042B GND Rpullup OC1 IN OUT1 EN1 OUT2 EN2 OC2 Figure 24. Typical Circuit for the OC Pin (Example, TPS2042B) Power Dissipation and Junction Temperature The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large currents. The thermal resistances of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on) from Figure 18. Using this value, the power dissipation per switch can be calculated by: PD = rDS(on) × I2 Multiply this number by the number of switches being used. This step renders the total power dissipation from the N-channel MOSFETs. Finally, calculate the junction temperature: TJ = PD × RqJA + TA Where: TA = Ambient temperature (°C) RqJA = Thermal resistance PD = Total power dissipation based on number of switches being used. Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. Thermal Protection Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The TPS204xB/TPS205xB implements a thermal sensing to monitor the operating junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises due to excessive power dissipation. Once the die temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown or overcurrent occurs. Undervoltage Lockout (UVLO) The UVLO ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage overshoots. 16 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 www.ti.com SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 Universal Serial Bus (USB) Applications The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution. USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply. The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements: • Hosts/self-powered hubs (SPHs) • Bus-powered hubs (BPHs) • Low-power bus-powered functions • High-power bus-powered functions • Self-powered functions Self-powered and bus-powered hubs distribute data and power to downstream functions. TPS204xB/TPS205xB can provide power-distribution solutions to many of these classes of devices. The Hosts/Self-Powered Hubs and Bus-Powered Hubs Hosts and self-powered hubs have a local power supply that powers the embedded functions and the downstream ports (see Figure 25). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs. Power Supply 3.3 V Downstream USB Ports 5V TPS2051B 2, 3 IN D+ D- 6, 7, 8 0.1 µF VBUS OUT 0.1 µF 5 USB Control 4 120 µF GND OC EN GND 1 Figure 25. Typical One-Port USB Host/Self-Powered Hub Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port. Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 17 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 www.ti.com Low-Power and High-Power Bus-Powered Functions Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω and 10 mF at power up, the device must implement inrush current limiting (see Figure 26). Power Supply 3.3 V D+ D− VBUS TPS2042B 2 10 µF 0.1 µF IN OUT1 GND 8 3 USB Control 5 4 7 0.1 µF 10 µF Internal Function 0.1 µF 10 µF Internal Function OC1 EN1 OC2 EN2 OUT2 GND 1 6 Figure 26. High-Power Bus-Powered Function (Example, TPS2042B) USB Power-Distribution Requirements USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented. • Hosts/self-powered hubs must: – Current-limit downstream ports – Report overcurrent conditions on USB VBUS • Bus-powered hubs must: – Enable/disable power to downstream ports – Power up at <100 mA – Limit inrush current (<44 Ω and 10 mF) • Functions must: – Limit inrush currents – Power up at <100 mA The feature set of the TPS204xB/TPS205xB allows them to meet each of these requirements. The integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input ports for bus-powered functions (see Figure 27 and Figure 28). 18 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 www.ti.com SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 TUSB2046 Hub Controller Upstream Port SN75240 BUSPWR A C B D GANGED D+ DP0 DP1 D- DM0 DM1 Tie to TPS2051B EN Input D+ 5V 33 µF (see Note A) DP3 OUT IN DM3 D+ A C B D 1 µF TPS76333 D- SN75240 Ferrite Beads GND DP4 IN 0.1 µF 4.7 µF 5V DM2 5-V Power Supply EN 3.3 V 4.7 µF VCC DGND SN75240 DP2 OC Ferrite Beads A C B D GND TPS2051B Downstream Ports DM4 5V TPS2051B GND GND PWRON1 EN OVRCUR1 OC 33 µF (see Note A) IN 0.1 µF OUT D+ TPS2051B 48-MHz Crystal XTAL1 PWRON2 EN OVRCUR2 OC D- IN Ferrite Beads 0.1 µF GND OUT Tuning Circuit XTAL2 PWRON3 OCSOFF 5V TPS2051B OVRCUR3 EN 33 µF (see Note A) IN 0.1 µF OC OUT GND D+ TPS2051B PWRON4 EN OVRCUR4 OC Ferrite Beads IN DGND 0.1 µF OUT 5V 33 µF (see Note A) A. USB rev 1.1 requires 120 mF per hub. Figure 27. Hybrid Self-Powered/Bus-Powered Hub Implementation (TPS2051B) Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 19 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 www.ti.com TUSB2046 Hub Controller Upstream Port SN75240 BUSPWR A C B D GANGED D+ D- DP0 DP1 DM0 DM1 Tie to TPS2051B EN Input D+ A C B D GND OC 5V IN 5-V Power Supply 5V 33 µF (see Note A) DP3 OUT DM3 A C B D TPS76333 SN75240 D+ DFerrite Beads GND DP4 IN 0.1 µF 3.3 V 4.7 µF VCC DM4 5V TPS2042B GND GND 48-MHz Crystal XTAL1 PWRON1 EN1 OUT1 OVRCUR1 OC1 OUT2 PWRON2 EN2 OVRCUR2 OC2 33 µF (see Note A) D+ IN D0.1 µF Tuning Circuit DGND DM2 EN 4.7 µF Ferrite Beads SN75240 DP2 TPS2051B Downstream Ports XTAL2 OCSOFF GND Ferrite Beads GND TPS2042B PWRON3 EN1 OUT1 OVRCUR3 OC1 OUT2 PWRON4 EN2 OVRCUR4 OC2 5V 33 µF (see Note A) IN D+ 0.1 µF Ferrite Beads DGND 5V 33 µF (see Note A) A. USB rev 1.1 requires 120 mF per hub. Figure 28. Hybrid Self-Powered/Bus-Powered Hub Implementation (TPS2042B) 20 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 www.ti.com SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 Generic Hot-Plug Applications In many applications, it may be necessary to remove modules or PC boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS204xB/TPS205xB, these devices can be used to provide a softer startup to devices being hot-plugged into a powered system. The UVLO feature of the TPS204xB/TPS205xB also ensures that the switch is off after the card has been removed, and that the switch is off during the next insertion. The UVLO feature ensures a soft start with a controlled rise time for every insertion of the card or module. PC Board TPS2042B OC1 GND Power Supply 2.7 V to 5.5 V 1000 µF Optimum 0.1 µF IN EN1 EN2 Block of Circuitry OUT1 OUT2 OC2 Block of Circuitry Overcurrent Response Figure 29. Typical Hot-Plug Implementation (Example, TPS2042B) By placing the TPS204xB/TPS205xB between the VCC input and the rest of the circuitry, the input power reaches these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device. DETAILED DESCRIPTION Power Switch The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a minimum current of 500 mA. Charge Pump An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires little supply current. Driver The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. Enable (ENx) The logic enable pin disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current. The supply current is reduced to less than 1 mA or 2 mA when a logic high is present on EN. A logic zero input on EN restores bias to the drive and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic levels. Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 21 TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 SLVS782A – NOVEMBER 2007 – REVISED JUNE 2010 www.ti.com Enable (EN) The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current. The supply current is reduced to less than 1 mA or 2 mA when a logic low is present on EN. A logic high input on EN restores bias to the drive and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic levels. Overcurrent (OCx) The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A 10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown occurs, the OCx is asserted instantaneously. Current Sense A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant-current mode and holds the current constant while varying the voltage on the load. Thermal Sense The TPS204xB/TPS205xB implements a thermal sensing to monitor the operating temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises. When the die temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch, thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an overtemperature shutdown or overcurrent occurs. Undervoltage Lockout (UVLO) A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control signal turns off the power switch. 22 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1 PACKAGE OPTION ADDENDUM www.ti.com 2-Jun-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS2041BQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples TPS2042BQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples TPS2051BQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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