UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 Digital Control Compatible Dual Low-Side ±4 Amp MOSFET Drivers with Programmable Common Current Sense FEATURES • • • • • • • • • • • • DESCRIPTION Adjustable Current Limit Protection 3.3-V, 10-mA Internal Regulator DSP/µC Compatible Inputs Dual ±4-A TrueDrive™ High Current Drivers 10-ns Typical Rise and Fall Times with 2.2-nF Loads 20-ns Input-to-Output Propagation Delay 25-ns Current Sense-to-Output Propagation Delay Programmable Current Limit Threshold Digital Output Current Limit Flag 4.5-V to 15-V Supply Voltage Range Rated from -40°C to 105°C Lead(Pb)-Free Packaging The UCD7201 is a member of the UCD7K family of digital control compatible drivers for applications utilizing digital control techniques or applications requiring fast local peak current limit protection. The UCD7201 includes dual low-side ±4-A high-current MOSFET gate drivers. It allows the digital power controllers such as UCD9110 or UCD9501 to interface to the power stage in double ended topologies. It provides a cycle-by-cycle current limit function for both driver channels, a programmable threshold and a digital output current limit flag which can be monitored by the host controller. With a fast cycle-by-cycle current limit protection, the driver can turn off the power stage in the event of an overcurrent condition. For fast switching speeds, the UCD7201 output stages use the TrueDrive™ output architecture, which delivers rated current of ±4 A into the gate of a MOSFET during the Miller plateau region of the switching transition. It also includes a 3.3-V, 10-mA linear regulator to provide power to the digital controller. APPLICATIONS • • • • Digitally Controlled Power Supplies DC/DC Converters Motor Controllers Line Drivers TYPICAL APPLICATION DIAGRAM (Push-Pull Converter) VIN Bias Winding VOUT Bias Supply DIGITAL CONTROLLER UCD7201PWP 1 NC NC 14 ADC1 VCC 2 3V3 GND 4 AGND PWMA 3 PWMB VDD 13 PVDD 12 IN1 OUT1 11 5 IN2 OUT2 10 INTERRUPT or CCR 6 CLF PGND 9 PWM or GPIO 7 ILIM CS 8 ADC2 ADC3 ADC4 Isolation Amplifier COMMUNICATION (Programming & Status Reporting) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TrueDrive, PowerPAD are trademarks of Texas Instruments. is a registered trademark of ~ Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 DESCRIPTION (CONT.) For similar applications requiring direct start-up capability from higher voltages such as the 48-V telecom input line, the UCD7601 includes a 110-V high-voltage startup circuit. The UCD7K driver family is compatible with standard 3.3-V I/O ports of DSPs, Microcontrollers, or ASICs. UCD7201 is offered in PowerPAD™ HTSSOP-14 or space-saving QFN-16 packages. CONNECTION DIAGRAMS PWP−14 PACKAGE (TOP VIEW) IN1 AGND 3 4 5 PVDD 15 6 OUT1 14 7 OUT2 8 PGND CLF 13 12 11 10 9 PGND IN2 2 CS NC − No internal connection VDD 1 16 NC 3V3 NC NC VDD PVDD OUT1 OUT2 PGND CS ILIM 14 13 12 11 10 9 8 1 2 3 4 5 6 7 NC NC 3V3 IN1 AGND IN2 CLF ILIM RSA−16 PACKAGE (BOTTOM VIEW) ORDERING INFORMATION PACKAGED DEVICES (1) (2) TEMPERATURE RANGE CURRENT SENSE LIMIT PER CHANNEL 110-V HV STARTUP CIRCUIT PowerPAD™ HTSSOP-14 (PWP) QFN-16 (RSA) (3) -40°C to 105°C Common No UCD7201PWP UCD7201RSA (1) (2) (3) These products are packaged in Pb-Free and Green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations. HTSSOP-14 (PWP) and QFN-16 (RSA), packages are available taped and reeled. Add R suffix to device type (e.g. UCD7201PWPR) to order quantities of 2,000 devices per reel for the PWP package and 1,000 devices per reel for the RSA packages. Contact factory for availability of QFN packaging. PACKAGING INFORMATION PACKAGE (1) 2 SUFFIX θJC θJA (°C/W) (°C/W) POWER RATING TA = 70°C, DERATING FACTOR, ABOVE 70°C (mW/°C) TJ = 125°C (mW) PowerPAD™ HTSSOP- 14 PWP 2.07 37.47 (1) 1470 27 QFN-16 RSA - - - - PowerPAD® soldered to the PWB (TI recommended PWB as defind in TI's application report SLMA002 pg.33) with OLFM. UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 ABSOLUTE MAXIMUM RATINGS (1) (2) SYMBOL VDD PARAMETER 16 V Quiescent 20 Switching, TA = 25°C, , TJ = 125°C, VDD = 12 V 200 Supply Current VOUT Output Gate Drive VoltOUT age IOUT(sink) IOUT(source) Output Gate Drive Current Analog Input Digital I/O’s Power Dissipation TJ Junction Operating Temperature Tstr Storage Temperature HBM CDM TSOL (2) UNIT Supply Voltage IDD (1) UCD7201 ESD Rating mA -1 to PVDD V 4.0 OUT A -4.0 ISET, CS -0.3 to 3.6 ILIM -0.3 to 3.6 IN, CLF -0.3 to 3.6 TA = 25°C (PWP-14 package), TJ = 125°C 2.67 TA = 25°C (QFN-16 package), TJ = 125°C - UCD7201 V W -55 to 150 °C -65 to 150 Human body model 2000 Change device model 500 Lead Temperature (Soldering, 10 sec) V +300 °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. ELECTRICAL CHARACTERISTICS VDD = 12 V, 4.7-µF capacitor from VDD to GND, 0.22µF from 3V3 to AGND, TA = TJ = -40°C to 105°C, (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY SECTION Supply current, OFF VDD = 4.2 V - 200 400 µA Supply current Outputs not switching IN = LOW - 1.5 2.5 mA LOW VOLTAGE UNDER-VOLTAGE LOCKOUT VDD UVLO ON 4.25 4.5 4.75 VDD UVLO OFF 4.05 4.25 4.45 VDD UVLO hysteresis 150 250 350 3.267 3.3 3.333 3.234 3.3 3.366 V mV REFERENCE / EXTERNAL BIAS SUPPLY 3V3 initial set point TA = 25°C, ILOAD = 0 3V3 set point over temperature 3V3 load regulation ILOAD = 1 mA to 10 mA, VDD = 5 V - 1 6.6 3V3 line regulation VDD = 4.75 V to 12 V, ILOAD = 10 mA - 1 6.6 Short circuit current VDD = 4.75 to 12 V 11 20 35 3V3 OK threshold, ON 3.3 V rising 2.9 3.0 3.1 3V3 OK threshold, OFF 3.3 V falling 2.7 2.8 2.9 HIGH, positive-going input threshold voltage (VIT+) 1.65 - 2.08 LOW negative-going input threshold voltage (VIT-) 1.16 - 1.5 0.6 - 0.8 V mV mA V INPUT SIGNAL Input voltage hysteresis, (VIT+ VIT-) V 3 UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 ELECTRICAL CHARACTERISTICS (continued) VDD = 12 V, 4.7-µF capacitor from VDD to GND, 0.22µF from 3V3 to AGND, TA = TJ = -40°C to 105°C, (unless otherwise noted). PARAMETER TEST CONDITIONS Frequency MIN TYP MAX UNIT - - 2 MHz 0.51 0.55 0.58 CURRENT LIMIT (ILIM) ILIM internal current limit threshold ILIM = OPEN ILIM maximum current limit threshold ILIM = 3.3 V 1.05 1.10 1.15 ILIM current limit threshold ILIM = 0.75 V 0.700 0.725 0.750 ILIM minimum current limit threshold ILIM = 0.25 V 0.21 0.23 0.25 CLF output high level CS > ILIM , ILOAD = -7 mA 2.64 - - CLF output low level CS ≤ ILIM, ILOAD = 7 mA - - 0.66 Propagation delay from IN to CLF IN rising to CLF falling after a current limit event - 10 20 ns Includes CS comp offset 5 25 50 mV - –1 - uA V CURRENT SENSE COMPARATOR Bias voltage Input bias current Propagation delay from CS to OUTx (1) ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV - 25 40 Propagation delay from CS to CLF (1) ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV - 25 50 10 35 75 ns CURRENT SENSE DISCHARGE TRANSISTOR Discharge resistance IN = low, resistance from CS to AGND Ω OUTPUT DRIVERS Source current Sink current Source (1) (1) current (1) Sink current (1) VDD = 12 V, IN = high, OUTx = 5 V 4 VDD = 12 V, IN = low, OUTx = 5 V 4 VDD = 4.75 V, IN = high, OUTx = 0 2 VDD = 4.75 V, IN = low, OUTx = 4.75 V A 3 Rise time, tR CLOAD= 2.2 nF, VDD = 12 V 10 20 Fall time, tF CLOAD = 2.2 nF, VDD = 12 V 10 15 Output with VDD < UVLO VDD =1.0 V, ISINK = 10 mA 0.8 1.2 Propagation delay from IN to OUT1, tD1 CLOAD = 2.2 nF, VDD = 12 V, CLK rising 20 35 Propagation delay from IN to OUT2, tD2 CLOAD = 2.2 nF, VDD = 12 V, CLK falling 20 35 (1) 4 ns V ns Ensured by design. Not 100% tested in production. UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 FUNCTIONAL BLOCK DIAGRAM NC 1 3V3 2 IN1 3 AGND 4 IN2 5 CLF 6 3V3 Regulator UVLO NC 13 VDD 12 PVDD 11 OUT1 10 OUT2 9 PGND 8 CS + and Reference 14 + Q SD 25 mV R Q ILIM R 7 Figure 1. UCD7201 Timing Diagram VIT+ INPUT VIT− tF tF tD1 90% tD2 OUTPUT 10% 5 UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 TERMINAL FUNCTIONS UCD7201 PIN NAME I/O - NC - No Connection 2 1 3V3 O Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. Place 0.22 µF of ceramic capacitance from this pin to ground. 3 2 IN1 I The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry from any external noise. 4 3 AGND - Analog ground return. 5 4 IN2 I The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry from any external noise. 6 5 CLF O Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the device receives the next rising edge on the IN pin. 7 6 ILIM I Current limit threshold set pin. The current limit threshold can be set to any value between 0.25 V and 1.0 V. The default value while open is 0.5 V. 8 7 CS I Current sense pin. Fast current limit comparator connected to the CS pin is used to protect the power stage by implementing cycle-by-cycle current limiting. 9 8, 9 PGND - Power ground return. The pin should be connected very closely to the source of the power MOSFET. 10 10 OUT2 O The high-current TrueDrive™ driver output. 11 11 OUT1 O The high-current TrueDrive™ driver output. 12 12 PVDD I Supply pin provides power for the output drivers. It is not connected internally to the VDD supply rail. The bypass capacitor for this pin should be returned to PGND. 13 13 VDD I Supply input pin to power the driver. The UCD7K devices accept an input range of 4.5 V to 15 V. Bypass the pin with at least 4.7 µF of capacitance, returned to AGND. 14 14, 15, 16 NC - HTSSOP -14 PIN # QFN-16 PIN # 1 6 FUNCTION No Connection. UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 APPLICATION INFORMATION The UCD7201 is member of the UCD7K family of digital compatible drivers targeting applications utilizing digital control techniques or applications that require local fast peak current limit protection. If limiting the rise or fall times to the power device is desired then an external resistance may be added between the output of the driver and the load device, which is generally the gate of a power MOSFET. Supply Current Sensing and Protection The UCD7K devices accept a supply range of 4.5 V to 15 V. The device has an internal precision linear regulator that produces the 3V3 output from this VDD input. A separate pin, PVDD, not connected internally to the VDD supply rail provides power for the output drivers. In all applications the same bus voltage supplies the two pins. It is recommended that a low value of resistance be placed between the two pins so that the local capacitance on each pin forms low pass filters to attenuate any switching noise that may be on the bus. A very fast current limit comparator connected to the CS pin is used to protect the power stage by implementing cycle-by-cycle current limiting. Although quiescent VDD current is low, total supply current depends on the gate drive output current required for capacitive load and switching frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (QG), average OUT current can be calculated from: IOUT = QG x f, where f is frequency. For the best high-speed circuit performance, VDD bypass capacitors are recommended to prevent noise problems. A 4.7-µF ceramic capacitor should be located closest to the VDD and the AGND connection. In addition, a larger capacitor with relatively low ESR should be connected to the PVDD and PGND pin, to help deliver the high current peaks to the load. The capacitors should present a low impedance characteristic for the expected current levels in the driver application. The use of surface mount components for all bypass capacitors is highly recommended. Reference / External Bias Supply All devices in the UCD7K family are capable of supplying a regulated 3.3-V rail to power various types of external loads such as a microcontroller or an ASIC. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. For normal operation, place 0.22-µF of ceramic capacitance between the 3V3 pin to the AGND pin. Input Pin The input pins are high impedance digital inputs capable of accepting 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt Trigger comparator which isolates the internal circuitry from any external noise. The current limit threshold may be set to any value between 0.25 V and 1.0 V by applying the desired threshold voltage to the current limit (ILIM) pin. If the ILIM pin is left floating, the internal current limit threshold will be 0.5 volts. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the device receives the next rising edge on either of the IN pins. When the CS voltage is below ILIM, the driver output follows the PWM input. The CLF digital output flag can be monitored by the host controller to determine when a current limit event occurs and to then apply the appropriate algorithm to obtain the desired current limit profile (i.e. straight time, fold back, hickup or latch-off). A benefit of this local protection feature is that the UCD7K devices can protect the power stage if the software code in the digital controller becomes corrupted. If the controller’s PWM output stays high, the local current sense circuit turns off the driver output when an over-current event occurs. The system would then likely go into retry mode because most DSP and microcontrollers have on-board watchdog, brown-out, and other supervisory peripherals to restart the device in the event that it is not operating properly. But these peripherals typically do not react fast enough to save the power stage. The UCD7K’s local current limit comparator provides the required fast protection for the power stage. The CS threshold is 25 mV below the ILIM voltage. If the user attempts to command zero current while the CS pin is at ground the CLF flag will latch high until the IN pin receives a pulse. At start-up it is necessary to ensure that the ILIM pin will always be greater than the CS pin for the handshaking to work as described below. If for any reason the CS pin comes to within 25 mV of the ILIM pin during start-up, then the CLF flag will be latched high and the digital controller must poll the UCD7K device, by sending it a narrow IN pulse. If a fault condition is not present the IN pulse will reset the CLF signal to low indicating that the UCD7K device is ready to process power pulses. 7 UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 Handshaking Drive Current and Power Requirements The UCD7K family of devices have a built-in handshaking feature to facilitate efficient start-up of the digitally controlled power supply. At start-up the CLF flag is held high until all the internal and external supply voltages of the UCD7K device are within their operating range. Once the supply voltages are within acceptable limits, the CLF goes low and the device will process input drive signals. The micro-controller should monitor the CFL flag at start-up and wait for the CLF flag to go LOW before sending power pulses to the UCD7K device. The UCD7K family of drivers can deliver high current into a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. Driver Output The high-current output stage of the UCD7K device family is capable of supplying ±4-A peak current pulses and swings to both PVDD and PGND. The driver outputs follow the state of the IN pin provided that the VDD and 3V3 voltages are above their respective under-voltage lockout threshold. The drive output utilizes Texas Instruments' TrueDrive™ architecture, which delivers rated current into the gate of a MOSFET when it is most needed, during the Miller plateau region of the switching transition providing efficiency gains. TrueDrive™ consists of pullup pulldown circuits with bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. This hybrid output stage also allows efficient current sourcing at low supply voltages. Each output stage also provides a very low pedance to overshoot and undershoot due to body diode of the external MOSFET. This means in many cases, external-schottky-clamp diodes not required. imthe that are Source/Sink Capabilities During Miller Plateau Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCD7K drivers have been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate capacitance with current supplied or removed by the driver device. See Reference [1] 8 Reference [1] discusses the current required to drive a power MOSFET and other capacitive-input switching devices. When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by: E 1 CV2 2 where C is the load capacitor and V is the bias voltage feeding the driver. There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by the following: P CV 2 f where f is the switching frequency. This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. With VDD = 12 V, CLOAD = 2.2 nF, and f = 300 kHz, the power loss can be calculated as: P 2.2 nF 122 300 kHz 0.095 W With a 12-V supply, this would equate to a current of: I P 0.095 W 7.9 mA V 12 V Operational Waveforms Figure 24 shows the circuit performance achievable with the output driving a 10-nF load at 12-V VDD. The input pulsewidth (not shown) is set to 200 ns to show both transitions in the output waveform. Note the linear rising and falling edges of the switching waveforms. This is due to the constant output current characteristic of TrueDrive™ stage as opposed to the resistive output impedance of traditional MOSFET-based gate drivers. UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 Thermal Information The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCD7K family of drivers is available in PowerPAD™ TSSOP and QFN/DFN packages to cover a range of application requirements. Both have an exposed pad to enhance thermal conductivity from the semiconductor junction. As illustrated in Reference [2], the PowerPAD™ packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board (PCB) directly underneath the device package, reducing the TJC down to 2.07°C/W. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in Reference [3]. Note that the PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. The PowerPad™ should be connected to the quiet ground of the circuit. Circuit Layout Recommendations In a power driver operating at high frequency, it is critical to minimize stray inductance to minimize overshoot/undershoots and ringing. The low output impedance of these drivers produces waveforms with high di/dt. This tends to induce ringing in the parasitic inductances. It is advantageous to connect the driver device close to the MOSFETs. It is recommended that the PGND and the AGND pins be connected to the PowerPad™ of the package with a thin trace. It is critical to ensure that the voltage potential between these two pins does not exceed 0.3 V. The use of schottky diodes on the outputs to PGND and PVDD is recommended when driving gate transformers. 9 UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 Additional Application Circuits Figure 2 shows the UCD7201 in a half-bridge converter design. The digital controller is performing the output voltage compensation and all supervisory functions. The isolation amplifier is made up of a linear opto-coupler configured for a gain of 1/10, so the output voltage is transformed to a level comparable with the ADC of the digital controller. VOUT VIN Bias Winding CS XFMR Bias Supply DIGITAL CONTROLLER ADC1 UCD7201PWP 1 NC NC 14 VCC 2 3V3 PVDD 12 GND 4 AGND VDD 13 PWMA 3 IN1 OUT1 11 PWMB 5 IN2 OUT2 10 6 CLF PGND 9 7 ILIM CS 8 ADC2 INTERRUPT or CCR PWM or GPIO Gate Drive Transformer (3 winding) ADC3 ADC4 Isolation Amplifier COMMUNICATION (Programming & Status Reporting) Figure 2. Half-Bridge Converter Figure 3 shows the UCD7201 in an analog only implementation of an intermediate bus converter. The ILIM pin of the UCD7201 is exponentially increased at start-up, which minimizes overshoot on the output voltage. The UCC28089 is a push-pull controller with fixed dead-time. The UCC28089 operates at a fixed duty cycle close to 100% so the circuit acts like a DC transformer linearly transforming the input voltage via the turns ratio of the transformer. VIN Bias Supply Bias Winding VOUT UCC28089 VDD 16 1 SYNC 1 NC UCD7201 NC 14 2 3V3 2 DIS GND 13 3 CT 4 CS 4 AGND PVDD 12 VDD 13 OUTA 15 3 IN1 OUT1 11 OUTB 14 5 IN2 OUT2 10 6 CLF PGND 9 7 ILIM CS 8 Figure 3. Intermediate Bus Converter 10 UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 Typical Characteristics UVLO THRESHOLDS vs TEMPERATURE 3V3 REFERENCE VOLTAGE vs TEMPERATURE 3.36 5.0 UVLO on 4.5 3.34 UVLO off 3V3 − Reference Voltage − V VUVLO − UVLO Thresholds − V 4.0 3.5 3.0 2.5 2.0 1.5 3.32 3.30 3.28 1.0 3.26 0.5 0.0 −50 UVLO hysteresis 3.24 −25 0 25 50 75 100 125 −50 t − Temperature − °C 0 25 50 75 t − Temperature − °C Figure 4. Figure 5. 3V3 SHORT CIRCUIT CURRENT vs TEMPERATURE SUPPLY CURRENT vs FREQUENCY (VDD = 5 V) 23.0 100 125 160 140 22.5 IDD − Supply Current − mA ISHORT_CKT − Short Circuit Current − mA −25 22.0 VDD = 4.75 V 21.5 VDD = 12 V 21.0 CLOAD = 10 nF 120 100 80 CLOAD = 4.7 nF 60 40 CLOAD = 2.2 nF 20.5 20 20.0 −50 CLOAD = 1 nF 0 −25 0 25 50 75 t − Temperature − °C Figure 6. 100 125 0 500 1000 1500 f − Frequency − kHz Figure 7. 11 UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 SUPPLY CURRENT vs FREQUENCY (VDD = 10 V) 280 320 240 280 CLOAD = 10 nF IDD − Supply Current − mA IDD − Supply Current − mA SUPPLY CURRENT vs FREQUENCY (VDD = 8 V) 200 160 CLOAD = 4.7 nF 120 80 CLOAD = 2.2 nF 240 CLOAD = 10 nF 200 160 CLOAD = 4.7 nF 120 80 40 CLOAD = 2.2 nF 40 CLOAD = 1 nF 0 0 500 1000 CLOAD = 1 nF 0 0 1500 500 Figure 8. Figure 9. SUPPLY CURRENT vs FREQUENCY (VDD = 12 V) SUPPLY CURRENT vs FREQUENCY (VDD = 15 V) 500 400 450 350 300 IDD − Supply Current − mA 400 IDD − Supply Current − mA 1500 f − Frequency − kHz f − Frequency − kHz CLOAD = 10 nF 250 200 CLOAD = 4.7 nF 150 100 CLOAD = 2.2 nF CLOAD = 10 nF 350 300 CLOAD = 4.7 nF 250 200 150 CLOAD = 2.2 nF 100 50 50 CLOAD = 1 nF CLOAD = 1 nF 0 0 500 1000 f − Frequency − kHz Figure 10. 12 1000 0 1500 0 1000 500 f − Frequency − kHz Figure 11. 1500 UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 INPUT THRESHOLDS vs TEMPERATURE OUTPUT RISE TIME AND FALL TIME vs TEMPERATURE (VDD = 12 V) 2.5 18.0 CLOAD = 2.2 nF 16.0 tR, tF − Rise and Fall Times − ns Input Rising VINPUT − Input Voltage − V 2.0 1.5 Input Falling 1.0 tR = Rise Time 14.0 12.0 10.0 tF = Fall Time 8.0 6.0 4.0 0.5 2.0 0.0 0.0 −50 −25 0 25 50 75 100 −50 125 −25 0 25 50 75 100 125 TJ − Temperature − °C TJ − Temperature − °C Figure 12. Figure 13. RISE TIME vs SUPPLY VOLTAGE FALL TIME vs SUPPLY VOLTAGE 65 45 40 55 35 45 tF − Fall Time − ns tR − Rise Time − ns CLOAD = 10 nF CLOAD = 4.7 nF 35 25 CLOAD = 10 nF 30 25 CLOAD = 4.7 nF 20 CLOAD = 2.2 nF CLOAD = 2.2 nF 15 15 CLOAD = 1 nF 10 CLOAD = 1 nF 5 5 5 7.5 10 12.5 15 5 7.5 10 12.5 VDD − Supply Voltage − V VDD − Supply Voltage − V Figure 14. Figure 15. 15 13 UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 IN to OUTx PROPAGATION DELAY RISING vs SUPPLY VOLTAGE IN to OUTx PROPAGATION DELAY FALLING vs SUPPLY VOLTAGE 25 tPD − Propagation Delay, Falling − ns tPD − Propagation Delay, Rising − ns 20 CLOAD = 10 nF 15 10 CLOAD = 4.7 nF 5 CLOAD = 2.2 nF CLOAD = 10 nF 20 15 CLOAD = 4.7 nF 10 CLOAD = 2.2 nF CLOAD = 1 nF CLOAD = 1 nF 5 0 7.5 10 12.5 15 7.5 10 12.5 15 VDD − Supply Voltage − V VDD − Supply Voltage − V Figure 16. Figure 17. DEFAULT CURRENT LIMIT THRESHOLD vs TEMPERATURE CS TO OUTx PROPAGATION DELAY vs TEMPERATURE 0.59 40 0.58 35 0.57 0.56 0.55 0.54 0.53 0.52 0.51 30 25 20 15 10 5 0 −50 −25 0 25 50 TJ − Temperature − °C Figure 18. 14 5 tPD − CS to OUTx Propagation Delay − ns VCS − Current Limit Threshold − V 5 75 100 125 −50 −25 0 25 50 75 TJ − Temperature − °C Figure 19. 100 125 UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 CS TO CLF PROPAGATION DELAY vs TEMPERATURE IN TO OUT PROPAGATION DELAY vs TEMPERATURE 35 50 30 40 tPD − Propagation Delay − ns tPD − CS to CLF Propagation Delay − ns 45 35 30 25 20 15 10 25 20 15 10 5 5 0 0 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 TJ − Temperature − °C TJ − Temperature − °C Figure 20. Figure 21. START-UP BEHAVIOR AT VDD = 12 V (INPUT TIED TO 3V3) SHUT DOWN BEHAVIOR AT VDD = 12 V (INPUT TIED TO 3V3) VDD (2 V/div) VDD (2 V/div) 3V3 (2 V/div) OUTx (2 V/div) t − Time − 40 µs/div Figure 22. 3V3 (2 V/div) OUTx (2 V/div) t − Time − 40 µs/div Figure 23. 15 UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 START-UP BEHAVIOR AT VDD = 12 V (INPUT SHORTED TO GND) SHUT DOWN BEHAVIOR AT VDD = 12 V (INPUT SHORTED TO GND) VDD (2 V/div) VDD (2 V/div) 3V3 (2 V/div) 3V3 (2 V/div) OUTx (2 V/div) OUTx (2 V/div) t − Time − 40 µs/div t − Time − 40 µs/div Figure 24. Figure 25. Output Voltage − 2 V/div OUTPUT RISE AND FALL TIME (VDD = 12 V, CLOAD = 10 nF) t − Time − 40 ns/div Figure 26. 16 UCD7201 www.ti.com SLUS645B – FEBRUARY 2005 – REVISED JULY 2005 REFERENCES 1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133. 2. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 3. Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004 RELATED PRODUCTS TEMPERATURE RANGE FEATURES Single Low Side ±4-A Driver with Independent CS 3V3, CS (1) (2) UCD7200 Dual Low Side ±4-A Drivers with Independent CS 3V3, CS (1) (2) UCD7230 ±4-A Synchronous Buck Driver with CS 3V3, CS (1) (2) UCD7500 Single Low Side ±4-A Driver with CS and 110-V High Voltage Startup 3v3, CS, HVS110 (1) (2) (3) UCD7600 Dual Low Side ±4-A Drivers with Independent CS and 110-V High Voltage Startup 3V3, CS, HVS110 (1) (2) (3) UCD7601 (1) (2) (3) (4) CURRENT SENSE LIMIT PER CHANNEL UCD7100 Dual Low Side ±4-A Drivers with Common CS and 110-V High Voltage Startup 3V3, CCS, HVS110 (1) (4) (3) UCD9110 Digital Power Controller for High Performance Single-loop Applications UCD9501 Digital Power Controller for High Performance Multi-Loop Applications 3V3 = 3.3-V linear regulator. CS = current sense and current limit function. HVS110 = 110-V high voltage startup circuit. CCS = Common current sense and current limit function. REVISION HISTORY DATE REVISION CHANGE DESCRIPTION 3/4/05 SLUS645 Initial release of preliminary datasheet. 4/1/05 SLUS645A Updated packaging information. 7/14/05 SLUS645B Initial release of production datasheet. Updated specification and application information. 17 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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