SN54ALS165, SN74ALS165 PARALLEL-LOAD 8-BIT REGISTERS SDAS157B – JUNE 1982 – REVISED DECEMBER 1994 • • • • • SN54ALS165 . . . J PACKAGE SN74ALS165 . . . D OR N PACKAGE (TOP VIEW) Complementary Outputs Direct Overriding Load (Data) Inputs Gated Clock Inputs Parallel-to-Serial Data Conversion Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs SH/LD CLK E F G H QH GND description The ′ALS165 are parallel-load 8-bit serial shift registers that, when clocked, shift the data toward serial (QH and QH) outputs. Parallel-in access to each stage is provided by eight individual direct data (A– H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The ′ALS165 have a clock-inhibit function and complemented serial outputs. 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLK INH D C B A SER QH CLK SH/LD NC VCC CLK INH SN54ALS165 . . . FK PACKAGE (TOP VIEW) E F NC G H 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 D C NC B A QH GND NC QH SER Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and the clock inhibit (CLK INH) input is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are enabled while SH/LD is low independently of the levels of the CLK, CLK INH, or serial (SER) inputs. NC – No internal connection The SN54ALS165 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS165 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS FUNCTION SH/LD CLK CLK INH L X X Parallel load H H X No change H X H L ↑ No change Shift† H ↑ L Shift† † Shift = content of each internal register shifts toward serial outputs. Data at SER is shifted into first register. H Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS165, SN74ALS165 PARALLEL-LOAD 8-BIT REGISTERS SDAS157B – JUNE 1982 – REVISED DECEMBER 1994 logic symbol† SRG8 C1 [LOAD] 1 SH/LD CLK INH CLK SER A B C D E F G H 15 ≥1 2 C2/ 10 2D 11 1D 12 1D 13 14 3 4 5 6 9 1D QH 7 QH † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. logic diagram (positive logic) A SH/LD CLK INH CLK SER 1 B 11 C 12 D 13 E 14 F 3 4 H 5 6 15 2 10 S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R Pin numbers shown are for the D, J, and N packages. 2 G POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 S C1 1D R S C1 1D R S C1 1D R 9 7 QH QH SN54ALS165, SN74ALS165 PARALLEL-LOAD 8-BIT REGISTERS SDAS157B – JUNE 1982 – REVISED DECEMBER 1994 typical shift, load, and inhibit sequences CLK CLK INH SER L SH/LD Data Inputs A H B L C H D L E H F L G H H H QH H H L H L H L H QH L L H L H L H L Inhibit Serial Shift Load absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS165 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS165 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS165, SN74ALS165 PARALLEL-LOAD 8-BIT REGISTERS SDAS157B – JUNE 1982 – REVISED DECEMBER 1994 recommended operating conditions SN54ALS165 SN74ALS165 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 High-level output current – 0.4 – 0.4 mA IOL fclock Low-level output current 4 8 mA 45 MHz High-level input voltage 2 Clock frequency 2 0 35 V 0 CLK high 14 11 CLK low 14 11 CLK low V V tw(CLK) (CLK) Pulse duration duration, CLK (see Figure 1) tw(load) tsu1 Pulse duration, SH/LD low 15 12 ns Setup time, clock enable (see Figure 1) 15 11 ns tsu2 tsu3 Setup time, parallel input (see Figure 1) 11 10 ns Setup time, serial input (see Figure 2) 11 10 ns tsu4 th Setup time, shift (see Figure 2) 15 10 ns TA Operating free-air temperature Hold time at any input 4 ns 4 – 55 125 ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VOL VCC = 4 4.5 5V IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V SN54ALS165 TYP† MAX MIN SN74ALS165 TYP† MAX MIN – 1.5 VCC – 2 – 1.5 VCC – 2 0.25 0.4 0.1 – 20 UNIT V V 0.25 0.4 0.35 0.5 0.1 V mA 20 20 µA – 0.1 – 0.1 mA – 112 mA – 112 – 30 ICC VCC = 5.5 V, See Note 1 12 24 12 24 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: With the outputs open, CLK INH and CLK at 4.5 V, and a clock pulse applied to SH/LD, ICC is measured first with the parallel inputs at 4.5 V, then with the parallel inputs grounded. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS165, SN74ALS165 PARALLEL-LOAD 8-BIT REGISTERS SDAS157B – JUNE 1982 – REVISED DECEMBER 1994 switching characteristics (see Figures 1, 2, and 3) FROM (INPUT) PARAMETER VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† SN54ALS165 SN74ALS165 TO (OUTPUT) MIN fmax tPLH MAX 35 tPHL tPLH SH/LD Any CLK Any H QH tPHL tPLH tPHL tPLH MIN MAX 45 MHz 4 23 4 20 4 23 4 22 3 14 3 13 3 15 3 14 3 14 3 13 3 18 3 16 2 15 3 16 2 17 QH H tPHL 3 17 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. UNIT ns ns ns ns PARAMETER MEASUREMENT INFORMATION 3.5 V (disable while clock is high) Vref CLK INH 0.3 V tsu1 3.5 V CLK Vref Vref Vref 0.3 V F and H Inputs (see Notes A and B) tw(CLK) tsu2 3.5 V Vref Vref Vref Vref 0.3 V tsu2 tw(load) tw(load) 3.5 V SH/LD Vref tPHL Vref tPLH tPHL Output QH Vref Vref tPLH Output QH tPHL tPLH NOTES: A. B. C. D. tw(CLK) Vref Vref Vref Vref Vref tPLH Vref tPHL Vref tPHL Vref tPLH Vref 0.3 V tPLH VOH Vref VOL tPHL VOH Vref VOL The remaining six data inputs and SER are low. Prior to test, high-level data is loaded into the H input. The input pulse generators have the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, tr = tf = 2 ns. Vref = 1.3 V Figure 1. Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ALS165, SN74ALS165 PARALLEL-LOAD 8-BIT REGISTERS SDAS157B – JUNE 1982 – REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION 3.5 V SH/LD Vref 0.3 V tsu4 3.5 V SER Vref 0.3 V tsu3 tsu3 3.5 V CLK Vref Vref 0.3 V tn NOTES: A. The eight data inputs and CLK INH are low. Results are monitored at QH at tn + 7. B. The input pulse generators have the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr = tf = 2 ns. C. Vref = 1.3 V Figure 2. Voltage Waveforms From Output Under Test CL (see Note A) Test Point RL NOTE A: CL includes probe and jig capacitance. Figure 3. Load Circuit for Switching Tests 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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