TI SN74LVC1G0832DBVR

SCES606 − SEPTEMBER 2004
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Input Hysteresis Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(Vhys = 250 mV Typ @ 3.3 V)
Can Be Used in Three Combinations:
− AND-OR Gate
− AND Gate
− OR Gate
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
A
GND
B
1
6
2
5
3
4
C
VCC
Y
YEP OR YZP PACKAGE
(BOTTOM VIEW)
B
GND
A
3 4
2 5
1 6
Y
VCC
C
description/ordering information
This device is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G0832 is a single 3-input positive AND-OR gate. It performs the Boolean function
Y + (A • B ) ) C in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
−40 C to 85°C
85 C
−40°C
SOT (SOT-23) − DBV
SOT (SC-70) − DCK
TOP-SIDE
MARKING‡
SN74LVC1G0832YEPR
Reel of 3000
____
SN74LVC1G0832YZPR
Reel of 3000
SN74LVC1G0832DBVR
Reel of 250
SN74LVC1G0832DBVT
Reel of 3000
SN74LVC1G0832DCKR
Reel of 250
SN74LVC1G0832DCKT
CDC_
DC_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2004, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
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1
SCES606 − SEPTEMBER 2004
description/ordering information (continued)
By tying one input to GND or VCC, the SN74LVC1G0832 offers two more functions. When C is tied to GND, this
device performs as a 2−input AND gate (Y = A • B). When A is tied to VCC, the device works as a 2−input OR
gate (Y = B + C). This device also works as a 2−input OR gate when B is tied to VCC (Y = A + C).
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUTS
B
C
OUTPUT
Y
X
X
H
H
H
H
X
H
X
L
L
L
L
X
L
L
A
X = Valid H or L
logic diagram (positive logic)
A
B
1
3
4
C
6
Y
FUNCTION SELECTION TABLE
LOGIC FUNCTION
FIGURE
2-Input AND Gate
1
2-Input OR Gate
2
Y = (A • B) + C
3
logic configurations
VCC
A
Y
A
B
B
1
6
2
5
3
4
Figure 1. 2−Input AND Gate
2
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Y
SCES606 − SEPTEMBER 2004
logic configurations (continued)
VCC
B
VCC
A
Y
C
B
1
6
2
5
3
4
C
Y
A
C
Y
1
6
2
5
3
4
C
Y
Figure 2. 2-Input OR Gate
VCC
A
B
A
Y
C
B
1
6
2
5
3
4
C
Y
Figure 3. Y = (A w B) + C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SCES606 − SEPTEMBER 2004
recommended operating conditions (see Note 4)
Operating
VCC
VIH
Supply voltage
High-level input voltage
VIL
Low-level input voltage
VO
Output voltage
Data retention only
High-level output current
∆t/∆v
Input transition rise or fall rate
5.5
5.5
2
5.5
0.7 × VCC
5.5
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0
0.35 × VCC
0
0.7
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
0
0.8
0
0.3 × VCC
0
VCC
−4
V
V
mA
−24
−32
4
8
16
VCC = 3 V
V
−8
−16
VCC = 3 V
UNIT
V
1.5
1.7
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.3 V
Low-level output current
1.65
5.5
VCC = 4.5 V
VCC = 1.65 V
IOL
MAX
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 1.65 V
VCC = 2.3 V
IOH
MIN
mA
24
VCC = 4.5 V
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
32
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
10
20
ns/V
5
TA
Operating free-air temperature
−40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCES606 − SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
IOH = −100 mA
IOH = −4 mA
1.65 V
VCC−0.1
1.2
2.3 V
1.9
IOH = −8 mA
IOH = −16 mA
VOH
IOL = 100 mA
IOL = 4 mA
3.8
0.1
1.65 V
0.45
2.3 V
0.3
0.4
3V
IOL = 24 mA
VI = 5.5 V or GND
0.55
0 to 5.5 V
Ioff
ICC
VI or VO = 5.5 V
VI = 5.5 V or GND,
0
∆ICC
Ci
One input at VCC − 0.6 V,
IO = 0
Other inputs at VCC or GND
1.65 V to 5.5 V
3 V to 5.5 V
VI = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
V
0.55
4.5 V
IOL = 32 mA
A B, or C
inputs
V
1.65 V to 5.5 V
IOL = 8 mA
IOL = 16 mA
UNIT
2.3
4.5 V
IOH = −32 mA
II
MAX
2.4
3V
IOH = −24 mA
VOL
TYP†
MIN
3.3 V
±5
mA
±10
mA
10
mA
500
mA
3.5
pF
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 4)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A, B, or C
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.7
14
2.4
7
1.7
5
1.2
3.4
UNIT
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF or
50 pF (unless otherwise noted) (see Figure 5)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A, B, or C
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.5
17.5
1.8
7.6
1.8
5.9
1.3
4
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
15
• DALLAS, TEXAS 75265
15
VCC = 3.3 V
TYP
16
VCC = 5 V
TYP
18
UNIT
pF
5
SCES606 − SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
CL
(see Note A)
VLOAD
Open
S1
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPZL
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
6
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SCES606 − SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
CL
(see Note A)
VLOAD
Open
S1
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPZL
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except, when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except, when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC1G0832DBVR
ACTIVE
SOT-23
DBV
6
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G0832DBVT
ACTIVE
SOT-23
DBV
6
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G0832DCKR
ACTIVE
SC70
DCK
6
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G0832DCKT
ACTIVE
SC70
DCK
6
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G0832YEPR
PREVIEW
WCSP
YEP
6
3000
None
Call TI
Call TI
SN74LVC1G0832YZPR
PREVIEW
WCSP
YZP
6
3000
None
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
6
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-3/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
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