ADS7882 www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008 12-BIT, 3-MSPS LOW POWER SAR ANALOG-TO-DIGITAL CONVERTER FEATURES 1 • • • • • • • • • • • 3-MHz Sample Rate, 12-Bit Resolution Zero Latency Unipolar, Pseudo Differential Input, Range: – 0 V to 2.5 V High-Speed Parallel Interface 69.5 dB SNR at 100 kHz I/P Power Dissipation 85 mW at 3 MSPS Nap Mode (10 mW Power Dissipation) Power Down (10 µW) Internal Reference Internal Reference Buffer 48-Pin TQFP Package DESCRIPTION The ADS7882 is a 12-bit 3-MSPS A-to-D converter with 2.5-V internal reference. The device includes a capacitor based SAR A/D converter with inherent sample and hold. The device offers a 12-bit parallel interface with an additional byte mode that provides easy interface with 8-bit processors. The device has a pseudo-differential input stage. The –IN swing of ±200 mV is useful to compensate for ground voltage mismatch between the ADC and sensor and also to cancel common-mode noise. With nap mode enabled, the device operates at lower power when used at lower conversion rates. The device is available in 48-pin TQFP package. APPLICATIONS • • • • • • Optical Networking (DWDM, MEMS Based Switching) Spectrum Analyzers High Speed Data Acquisition Systems High Speed Close-Loop Systems Telecommunication Ultra-Sound Detection BYTE SAR +IN −IN + _ Output Latches and 3-State Drivers CDAC Comparator 12/8-Bit Parallel Data Output Bus REFIN CLOCK REFOUT 2.5 V Internal Reference Conversion and Control Logic PWD/RST CONVST BUSY CS RD A_PWD 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) MODEL MAXIMUM INTEGRAL LINEARITY MAXIMUM DIFFERENTIAL LINEARITY NO MISSING CODES AT RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNATOR TEMPERATURE RANGE ADS7882 ±4 LSB at 12 bit ±4 LSB at 12 bit (±1 LSB at 10 bit) 10 48-Pin TQFP PFB –40°C to 85°C (1) ORDERING INFORMATION TRANSPORT MEDIA QUANTITY ADS7882IPFBT Tape and reel 250 ADS7882IPFBR Tape and reel 1000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT +IN to AGND –0.3 to +VA + 0.1 V -IN to AGND –0.3 to 0.5 V +VA to AGND –0.3 to 7 V +VBD to BDGND –0.3 to 7 V Digital input voltage to GND –0.3 to (+VBD + 0.3 V) V Digital output to GND –0.3 to (+VBD + 0.3 V) V Operating temperature range –40 to 85 °C Storage temperature range –65 to 150 °C 150 °C Junction temperature (TJmax) TQFP package Lead temperature, soldering (1) 2 (TJ Max–TA)/ θJA Power dissipation θJA Thermal impedance 86 °C/W Vapor phase (60 sec) 215 °C Infrared (15 sec) 220 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 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SLAS630 – DECEMBER 2008 SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 2.5 V, fsample = 3 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (1) Absolute input range +IN – (–IN) 0 Vref +IN –0.2 Vref +0.2 –IN –0.2 0.2 Input capacitance Input leakage current V V 27 pF 500 pA 12 Bits SYSTEM PERFORMANCE Resolution No missing codes 10 Integral linearity (2) –4 ±1 4 LSB (3) Differential linearity –4 ±1 4 LSB (3) Offset error (4) Gain error (4) Bits ±1 mV ±1.2 mV Common-mode rejection ratio With common mode input signal = 200 mVp-p at 1 MHz 60 dB Power supply rejection At FF0H output code, +VA = 4.75 V to 5.25 V , Vref = 2.50 V 80 dB SAMPLING DYNAMICS Conversion time Acquisition time +VDB = 5 V 280 +VDB = 3 V 280 +VDB = 5 V 53 +VDB = 3 V 53 nsec nsec Maximum throughput rate 3 MHz Aperture delay 2 nsec Aperture jitter 20 psec Step response 50 nsec Overvoltage recovery 50 nsec DYNAMIC CHARACTERISTICS Total harmonic distortion (5) VIN = 2.496 Vp-p at 0.1 MHz/2.5 Vref –79.5 dB SNR VIN = 2.496 Vp-p at 0.1 MHz/2.5 Vref 69.5 dB SINAD VIN = 2.496 Vp-p at 0.1 MHz/2.5 Vref 68.5 dB SFDR VIN = 2.496 Vp-p at 0.1 MHz/2.5 Vref 80.5 dB –3 dB Small signal bandwidth 50 MHz EXTERNAL REFERENCE INPUT Input VREF range Resistance 2.4 (6) 2.5 2.6 500 V kΩ INTERNAL REFERENCE OUTPUT Start-up time From 95% (+VA), with 1-µF storage capacitor on REFOUT to AGND VREF range IOUT = 0 Source current Static load Line regulation +VA = 4.75 V to 5.25 V Drift IOUT = 0 (1) (2) (3) (4) (5) (6) 120 2.425 2.5 msec 2.575 V 10 µA 1 mV 25 PPM/°C Ideal input span; does not include gain or offset error. This is endpoint INL, not best fit. LSB means least significant bit. Measured relative to actual measured reference. Calculated on the first nine harmonics of the input frequency. Can vary ±20%. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 3 ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com SPECIFICATIONS (continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 2.5 V, fsample = 3 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic family CMOS Logic level VIH IIH = 5 µA +VBD –1 +VBD +0.3 V VIL IIL = 5 µA –3 0.8 V VOH IOH = 2 TTL loads +VBD –0.6 +VBD V VOL IOL = 2 TTL loads 0 0.4 V V Straight Binary Data format POWER SUPPLY REQUIREMENTS +VBD Power supply voltage +VA 2.7 3.3 5.25 4.75 5 5.25 17 22 mA 85 110 mW 2 3 mA Supply current, +VA, 3 MHz sample rate Power dissipation, 3 MHz sample rate +VA = 5 V V NAP MODE Supply current, +VA Power-up time (7) 60 nsec POWER DOWN Supply current, +VA 2 2.5 µA Power down time (8) From simulation results 10 µsec Power up time 1-µF storage capacitor on REFOUT to AGND 25 msec Invalid conversions after power up or reset TEMPERATURE RANGE Operating free-air (7) (8) 4 –40 85 °C Minimum acquisition time for first sampling after the end of nap state must be 60 nsec more than normal. Time required to reach level of 2.5 µA. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 ADS7882 www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008 TIMING REQUIREMENTS All specifications typical at –40°C to 85°C, +VA = +5 V, +VBD = +5 V (1) (2) (3) (4) PARAMETER t(conv) Conversion time t(acq) Acquisition time MIN TYP MAX UNIT REF FIG. 280 ns 5 ns 5 ns 3 ns 1 53 SAMPLING AND CONVERSION START th1 Hold time CS low to CONVST high (with BUSY high) td1 Delay CONVST high to acquisition start 10 th2 Hold time, CONVST high to CS high with BUSY low 10 ns 1 th3 Hold time, CONVST low to CS high 10 ns 1 td2 Delay CONVST low to BUSY high ns 1 tw3 CS width for acquisition or conversion to start ns 2 td3 Delay CS low to acquisition start with CONVST high ns 2 tw1 Pulse width, from CS low to CONVST low for acquisition to start ns 2 td4 Delay CS low to BUSY high with CONVST low ns 2 2 4 5 40 (3) Quiet sampling time 20 2 4 5 20 40 25 ns CONVERSION ABORT ts1 Setup time CONVST high to CS low with BUSY high 15 ns 4 td5 Delay time CS low to BUSY low with CONVST high 20 ns 4 DATA READ td6 Delay RD low to data valid with CS low 25 ns td7 Delay BYTE high to LSB word valid with CS and RD low 25 ns 5 td9 Delay time RD high to data 3-state with CS low 25 ns 5 td11 Delay time end of conversion to BUSY low 20 ns 5 t1 Quiet sampling time RD high to CONVST low 20 ns 5 td8 Delay CS low to data valid with RD low 25 ns 5 td10 Delay CS high to data 3-state with RD low 25 ns 6 t2 Quiet sampling time CS low to CONVST low 25 ns 6 10 BACK-TO-BACK CONVERSION td12 Delay BUSY low to data valid ns 7, 8 tw4 Pulse width, CONVST high 63 ns 7, 8 tw5 Pulse width, CONVST low 20 ns 7 ns 10 ns 9 ns 9 POWER DOWN/RESET tw6 Pulse width, low for PWD/RST to reset the device tw7 Pulse width, low for PWD/RST to power down the device td13 Delay time, power up after PWD/RST is high (1) (2) (3) (4) 45 6140 7200 25 All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. See timing diagram. Quiet period before conversion start, no data bus activity including data bus 3-state is allowed in this period. All timings are measured with 20 pF equivalent loads on all data bits and BUSY pin. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 5 ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com PWD/RST A_PWD BYTE CONVST +VA CS RD AGND AGND +VA REFM REFM PIN ASSIGNMENTS 48 47 46 45 44 43 42 41 40 39 38 37 REFIN 1 36 BUSY REFOUT 2 35 BDGND NC 3 34 +VBD +VA 4 33 NC AGND 5 32 NC +IN 6 31 NC −IN 7 30 NC AGND 8 29 +VA 9 28 DB0 DB1 +VA 10 27 DB2 AGND 11 26 DB3 AGND 12 25 BDGND 24 +VBD DB5 DB4 DB6 DB7 DB8 DB9 DB11 DB10 AGND AGND +VA 13 14 15 16 17 18 19 20 21 22 23 NC − No connection PIN FUNCTIONS PIN NAME NO. PFB I/O DESCRIPTION 8-BIT BUS DATA BUS 16-BIT BUS BYTE = 0 BYTE = 1 BYTE = 0 DB11 16 O D11 (MSB) D3 D11 (MSB) DB10 17 O D10 D2 D10 DB9 18 O D9 D1 D9 DB8 19 O D8 D0 (LSB) D8 DB7 20 O D7 0 D7 DB6 21 O D6 0 D6 DB5 22 O D5 0 D5 DB4 23 O D4 0 D4 DB3 26 O D3 0 D3 DB2 27 O D2 0 D2 DB1 28 O D1 0 D1 DB0 29 O D0 (LSB) 0 D0 (LSB) CS 42 I Chip select. Active low signal enables chip operation like acquisition start, conversion start, bus release from 3-state. Refer to the timing diagrams for more details. CONVST 40 I Conversion start. The rising edge starts the acquisition. The falling edge of this input ends the acquisition and starts the conversion. Refer to the timing diagrams for more details. RD 41 I Active low synchronization pulse for the parallel output. When CS is low, this serves as the output enable and puts the previous conversion results on the bus. A_PWD 37 I Nap mode enable, active low CONTROL PINS 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 ADS7882 www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008 PIN FUNCTIONS (continued) PIN NAME NO. PFB I/O DESCRIPTION 8-BIT BUS DATA BUS BYTE = 0 16-BIT BUS BYTE = 1 BYTE = 0 PWD/RST 38 I Active low input, acts as device power down/device reset signal. BYTE 39 I Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Lower byte D[3:0] is folded back to high byte so D3 is available in D11 place. 36 O Status output. High when a conversion is in progress. +VBD 24, 34 – Digital power supply for all digital inputs and outputs. Refer to Table 3 for layout guidelines. BDGND 25, 35 – Digital ground for all digital inputs and outputs. Short to analog ground plane below the device. 4, 9, 10, 13, 43, 46 – Analog power supplies. Refer to Table 3 for layout guidelines. 5, 8, 11, 12, 14, 15, 44, 45 – Analog ground pins. Short to analog ground plane below the device. +IN 6 I Noninverting analog input channel –IN 7 I Inverting analog input channel REFIN 1 I Reference (positive) input. Needs to be decoupled with REFM pin using 0.1-µF bypass capacitor and 1-µF storage capacitor. REFOUT 2 O Internal reference output. To be shorted to REFIN pin when internal reference is used. Do not connect to REFIN pin when external reference is used. Always needs to be decoupled with AGND using 0.1-µF bypass capacitor. I Reference ground. Connect to analog ground plane. – No connection STATUS OUTPUT BUSY POWER SUPPLY +VA AGND ANALOG INPUT REFM NC 47, 48 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 7 ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com DESCRIPTION AND TIMING DIAGRAMS SAMPLING AND CONVERSION START There are three ways to start sampling. The rising edge of CONVST starts sampling with CS and BUSY being low (see Figure 1) or it can be started with the falling edge of CS when CONVST is high and BUSY is low (see Figure 2). Sampling can also be started with an internal conversion end (before BUSY falling edge) with CS being low and CONVST high before an internal conversion end (see Figure 3). Also refer to the section DEVICE OPERATION AND DATA READ IN BACK-TO-BACK CONVERSION for more details. A conversion can be started two ways (a conversion start is the end of sampling). Either with the falling edge of CONVST when CS is low (see Figure 1) or the falling edge of CS when CONVST is low (see Figure 2). A clean and low jitter falling edge of these respective signals triggers a conversion start and is important to the performance of the converter. The BUSY pin is brought high immediately following the CONVST falling edge. BUSY stays high throughout the conversion process and returns low when the conversion has ended. th2 th3 CS CONVST td1 td2 BUSY t(acq) Figure 1. Sampling and Conversion Start Control With CONVST Pin tw3 tw3 CS td4 CONVST td3 tw1 BUSY t(acq) Figure 2. Sampling and Conversion Start Control With CS Pin CS th1 tw5 CONVST tw4 BUSY td2 t(acq) Figure 3. Sampling Start With CS Low and CONVST High (Back-to-Back) 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 ADS7882 www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008 CONVERSION ABORT The falling edge of CS aborts the conversion while BUSY is high and CONVST is high (see Figure 4). The device outputs FE0 (hex) to indicate a conversion abort. td5 BUSY tsu1 CONVST CS RD 1111 1110 0000 D11−D0 Figure 4. Conversion Abort DATA READ Two conditions need to be satisfied for a read operation. Data appears on the D11 through D0 pins (with D11 MSB) when both CS and RD are low. Figure 5 and Figure 6 illustrate the device read operation. The bus is 3-stated if any one of the signals is high. t1 td2 tw5 CONVST t(conv) td1 + t(acq) BUSY td11 CS RD BYTE td6 D11−D0 td7 D11−4 & D3−0 td9 D3−0 Figure 5. Read Control via CS and RD There are two output formats available. Twelve bit data appears on the bus during a read operation while BYTE is low. When BYTE is high, the lower byte (D3 through D0 followed by all zeroes) appears on the data bus with D3 in the MSB. This feature is useful for interfacing with eight bit microprocessors and microcontrollers. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 9 ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com t2 CONVST td1 + t(acq) BUSY Conversion No N td2 CS BYTE td7 D11−4 & D3−0 D11−D0 Data For Conv. N−1 td10 D3−0 Data For Conv. N td8 Figure 6. Read Control Via CS and RD Tied to BDGND DEVICE OPERATION AND DATA READ IN BACK-TO-BACK CONVERSION Figure 7 and Figure 8 illustrate device operation in back-to-back conversion mode. It is possible to operate the device at any throughput in this mode, but this is the only mode in which the device can be operated at throughputs exceeding 2.83 MSPS (1/t(acq) min + t(conv) max + td11 max)). A conversion starts on the CONVST falling edge. The BUSY output goes high after a delay (td2). Note that care must be taken not to abort the conversion (see Figure 4) apart from timing restrictions shown in Figure 7 and Figure 8. The conversion ends within the conversion time, t(conv), after the CONVST falling edge. The new acquisition can be immediately started without waiting for the BUSY signal to go low. This can be ensured with a CONVST high pulse width that is more than or equal to (t0 – t(conv) + 10 nsec) which is tw4 for a 3-MHz operation. Sample N CONVST tw4 t(acq) tw5 Conversion N BUSY td12 t(conv) + td11 Data For Conversion N−1 D11−D0 (Data Read without Latency) t0 = 333 ns for 3 MSPS Operation Figure 7. Back-To-Back Operation With CS and RD Low 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 ADS7882 www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008 CS Sample N th1 CONVST tw4 t(acq) tw3 t(conv) + td11 Conversion N BUSY Data For Conversion N−1 td12 D11−D0 (Data Read without Latency) t0 = 333 ns for 3 MSPS Operation Figure 8. Back-To-Back operation With CS Toggling and RD Low NAP MODE The device can be put in nap mode following the sequences shown in Figure 9. This provides substantial power saving while operating at lower sampling rates. While operating the device at throughput rates lower than 2.54 MSPS, A_PWD can be held low (see Figure 9). In this condition, the device goes into the nap state immediately after BUSY goes low and remains in that state until the next sampling starts. The minimum acquisition time is 60 nsec more than t(acq) as defined in the timing requirements section. Alternately, A_PWD can be toggled any time during operation (see Figure 10). This is useful when the system acquires data at the maximum conversion speed for some period of time (back-to-back conversion) and it does not acquire data for some time while the acquired data is being processed. During this period, the device can be put in the nap state to save power. The device remains in the nap state as long as A_PWD is low with BUSY being low and sampling has not started. The minimum acquisition time for the first sampling after the nap state is 60 nsec more than t(acq) as defined in the timing requirements section. A_PWD (Held Low) BUSY SAMPLE (Internal) t(acq) + 60 ns NAP (Internal Active High) NOTE: The SAMPLE (Internal) signal is generated as described in the Sampling and Conversion Start section. Figure 9. Device Operation While A_PWD is Held Low Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 11 ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com A_PWD BUSY SAMPLE (Internal) t(acq) + 60 ns NAP (Internal Active High) NOTE: The SAMPLE (Internal) signal is generated as described in the Sampling and Conversion Start section. Figure 10. Device Operation While A_PWD is Toggling POWERDOWN/RESET A low level on the PWD/RST pin puts the device in the powerdown phase. This is an asynchronous signal. As shown in Figure 11, the device is in the reset phase for the first tw6 period after a high-to-low transition of PWD/RST. During this period the output code is FE0 (hex) to indicate that the device is in the reset phase. The device powers down if the PWD/RST pin continues to be low for a period of more than tw7. Data is not valid for the first four conversions after a power-up (see Figure 11) or an end of reset (see Figure 12). The device is initialized during the first four conversions. tw7 Valid Conversions PWD/RST First 4 Invalid Conversions BUSY 1 2 3 4 5 td13 D11−D0 1111 1110 0000 Power Down Phase RESET Phase Invalid Data Valid Data Figure 11. Device Power Down tw6 45 ns Valid Conversions PWD/RST First 4 Invalid Conversions BUSY D11−D0 1 2 3 4 5 1111 1110 0000 RESET Phase Invalid Data Valid Data Figure 12. Device Reset 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 ADS7882 www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008 TYPICAL CHARACTERISTICS (1) EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE HISTOGRAM (DC CODE SPREAD CLOSE TO ZERO INPUT) 11.24 4692 TA = 25°C Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 4500 f − Frequency − kHz 4000 ENOB − Effective Number of Bits − Bits 5000 3500 3000 2500 2000 1500 1000 500 308 0 28 11.22 11.20 11.18 11.16 11.14 11.12 11.10 fIN = 100 kHz Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 11.08 −40 29 −20 G001 SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE 70.5 SNR − Signal-to-Noise Ratio − dB SINAD − Signal-to-Noise and Distortion − dB 60 80 G002 71.0 fIN = 100 kHz Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 68.5 −20 0 20 40 60 TA − Free-Air temperature − °C fIN = 100 kHz Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 70.0 69.5 69.0 68.5 68.0 −40 80 G003 Figure 15. (1) 40 Figure 14. 69.0 68.0 −40 20 Figure 13. 70.0 69.5 0 TA − Free-Air temperature − °C Bin −20 0 20 40 60 TA − Free-Air temperature − °C 80 G004 Figure 16. At sample rate = 3 MSPS, Vref = 2.5 V external, unless otherwise specified. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 13 ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE SPURIOUS-FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 82.0 fIN = 25°C Throughput = 3 MSPS VA = 5 V VREF = 2.5 V −78.5 SFDR − Spurious-Free Dynamic Range − dB THD − Total Harmonic Distortion − dB −78.0 −79.0 −79.5 −80.0 −80.5 −81.0 −40 −20 0 20 40 60 81.0 80.5 fIN = 25°C Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 80.0 −40 80 −20 20 40 60 G005 Figure 17. Figure 18. EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY 80 G006 72 SINAD − Signal-to-Noise and Distortion − dB 11.5 11.3 11.1 10.9 TA = 25°C Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 10.7 1 TA = 25°C Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 71 70 69 68 67 10.5 10 fIN − Input Frequency − kHz 100 1 10 fIN − Input Frequency − kHz G007 Figure 19. 14 0 TA − Free-Air temperature − °C TA − Free-Air temperature − °C ENOB − Effective Number of Bits − Bits 81.5 100 G008 Figure 20. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 ADS7882 www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008 SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 72.0 −78.0 THD − Total Harmonic Distortion − dB SNR − Signal-to-Noise Ratio − dB 71.5 71.0 70.5 70.0 TA = 25°C Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 69.5 69.0 −78.5 −79.0 −79.5 −80.0 −80.5 −81.0 1 10 100 fIN − Input Frequency − kHz 1 10 100 fIN − Input Frequency − kHz G009 Figure 21. Figure 22. SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY OFFSET ERROR vs FREE-AIR TEMPERATURE G010 2.0 87.0 TA = 25°C Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 86.5 86.0 1.5 85.5 85.0 84.5 0.5 0.0 −0.5 84.0 −1.0 83.5 −1.5 83.0 1 Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 1.0 Offset Error − mV SFDR − Spurious-Free Dynamic Range − dB TA = 25°C Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 10 fIN − Input Frequency − kHz 100 −2.0 −40 G011 Figure 23. −20 0 20 40 60 TA − Free-Air temperature − °C 80 G012 Figure 24. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 15 ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com GAIN ERROR vs FREE-AIR TEMPERATURE INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 2.0 3 INL − Integral Nonlinearity − LSB 1.5 4 Throughput = 3 MSPS VA = 5 V VREF = 2.5 V Gain Error − LSB 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 −40 −20 0 20 40 60 0 −1 Min −2 −20 0 20 40 60 G013 Figure 25. Figure 26. DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE REFERENCE OUTPUT DRIFT vs FREE-AIR TEMPERATURE 80 G014 7 Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 2 1 Max 0 −1 Throughput = 3 MSPS VA = 5 V 6 Min −2 −3 5 4 3 2 1 0 −1 −20 0 20 40 60 TA − Free-Air temperature − °C −2 −40 80 G015 Figure 27. 16 Max TA − Free-Air temperature − °C Reference Output Drift − mV DNL − Differential Nonlinearity − LSB 1 −4 −40 80 4 −4 −40 2 −3 TA − Free-Air temperature − °C 3 Throughput = 3 MSPS VA = 5 V VREF = 2.5 V −20 0 20 40 60 TA − Free-Air temperature − °C 80 G016 Figure 28. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 ADS7882 www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008 POWER DISSIPATION vs SAMPLE RATE 90 PD − Power Dissipation − mW 80 70 60 50 40 30 20 TA = 25°C VA = 5 V VREF = 2.5 V 10 0 0 500 1000 1500 2000 2500 3000 Sample Rate − KSPS G017 Figure 29. DIFFERENTIAL NONLINEARITY DNL − Differential Nonlinearity − LSB 1.0 TA = 25°C Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 0.8 0.6 0.4 0.2 0.0 −0.2 −0.4 −0.6 −0.8 −1.0 0 1024 2048 3072 4096 Code G018 Figure 30. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 17 ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com INTEGRAL NONLINEARITY INL − Integral Nonlinearity − LSB 1.0 TA = 25°C Throughput = 3 MSPS VA = 5 V VREF = 2.5 V 0.8 0.6 0.4 0.2 0.0 −0.2 −0.4 −0.6 −0.8 −1.0 0 1024 2048 3072 4096 Code G019 Figure 31. FFT 0 TA = 25°C Throughput = 3 MSPS VA = 5 V VREF = 2.5 V −20 P − Power − dB −40 −60 −80 −100 −120 −140 −160 −180 0 300 600 900 1200 1500 f − Frequency − kHz G020 Figure 32. PRINCIPLES OF OPERATION The ADS7882 is a member of a family of high-speed successive approximation register (SAR) analog-to-digital converters (ADC). The architecture is based on charge redistribution, which inherently includes a sample/hold function. The conversion clock is generated internally. The conversion time is 200 ns max (at 5 V +VBD). The analog input is provided to two input pins: +IN and –IN. (Note that this is pseudo differential input and there are restrictions on –IN voltage range.) When a conversion is initiated, the difference voltage between these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. REFERENCE The ADS7882 has a built-in 2.5-V (nominal value) reference but can operate with an external reference. When an internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1-µF decoupling capacitor and a 1-µF storage capacitor between pin 2 (REFOUT) and pins 47, 48 (REFM). The internal reference of the converter is buffered . There is also a buffer from REFIN to CDAC. This buffer provides isolation between the external reference and the CDAC and also recharges the CDAC during conversion. It is essential to decouple REFOUT to AGND with a 0.1-µF capacitor while the device operates with an external reference. 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 ADS7882 www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008 PRINCIPLES OF OPERATION (continued) ANALOG INPUT When the converter enters hold mode, the voltage difference between the +IN and -IN inputs is captured on the internal capacitor array. The voltage on the –IN input is limited to between –0.2 V and 0.2 V, thus allowing the input to reject a small signal which is common to both the +IN and -IN inputs. The +IN input has a range of –0.2 V to (+Vref +0.2 V). The input span (+IN – (–IN)) is limited from 0 V to VREF. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, signal frequency, and source impedance. Essentially, the current into the ADS7882 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current (this may not happen when a signal is moving continuously). The source of the analog input voltage must be able to charge the input capacitance (27 pF) to better than a 12-bit settling level with a step input within the acquisition time of the device. The step size can be selected equal to the maximum voltage difference between two consecutive samples at the maximum signal frequency. (Refer to Figure 35 for the suggested input circuit.) When the converter goes into hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, both –IN and +IN inputs should be within the limits specified. Outside of these ranges, the converter's linearity may not meet specifications. Care should be taken to ensure that +IN and -IN see the same impedance to the respective sources. (For example, both +IN and –IN are connected to a decoupling capacitor through a 21-Ω resistor as shown in Figure 35.) If this is not observed, the two inputs could have different settling times. This may result in an offset error, gain error, or linearity error which changes with temperature and input voltage. DIGITAL INTERFACE TIMING AND CONTROL Refer to the SAMPLING AND CONVERSION START section and the CONVERSION ABORT section. READING DATA The ADS7882 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when CS and RD are both low. There is a minimal quiet sampling period requirement around the falling edge of CONVST as stated in the timing requirements section. Data reads or bus three-state operations should not be attempted within this period. Any other combination of CS and RD 3-states the parallel output. Refer to Table 1 for ideal output codes. Table 1. Ideal Input Voltages and Output Codes (1) DESCRIPTION ANALOG VALUE BINARY CODE HEX CODE Full scale Vref – 1 LSB 1111 1111 1111 FFF Midscale Vref/2 1000 0000 0000 800 Midscale – 1 LSB Vref/2 – 1 LSB 0111 1111 1111 7FF Zero 0V 0000 0000 0000 000 (1) Full-scale range = Vref and least significant bit (LSB) = Vref/4096 The output data appears as a full 12-bit word (D11–D0) on pins DB11–DB0 (MSB–LSB) if BYTE is low. READING THE DATA IN BYTE MODE The result can also be read on an 8-bit bus for convenience by using pins DB11–DB4. In this case two reads are necessary; the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB11–DB4, and then bringing BYTE high. When BYTE is high, the lower bits (D3–D0) followed by all zeros are on pins DB11–DB4 (refer to Table 2). These multi-word read operations can be performed with multiple active RD signals (toggling) or with RD tied low for simplicity. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 19 ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com Table 2. Conversion Data Read Out DATA READ OUT BYTE DB11–DB4 DB3–DB0 High D3–D0, 0000 All zeroes Low D11–D4 D3–D0 Also refer to the DATA READ and DEVICE OPERATION AND DATA READ IN BACK-TO-BACK CONVERSION sections for more details. Reset Refer to the POWERDOWN/RESET section for the device reset sequence. It is recommended to reset the device after power on. A reset can be issued once the power has reached 95% of its final value. PWD/RST is an asynchronous active low input signal. A current conversion is aborted no later than 45 ns after the converter is in the reset mode. In addition, the device outputs a FE0 code to indicate a reset condition. The converter returns back to normal operation mode immediately after the PWD/RST input is brought high. Data is not valid for the first four conversions after a device reset. Powerdown Refer to the POWERDOWN/RESET section for the device powerdown sequence. The device enters powerdown mode if a PWD/RST low duration is extended for more than a period of tw7. The converter goes back to normal operation mode no later than a period of td13 after the PWD/RST input is brought high. After this period, normal conversion and sampling operation can be started as discussed in previous sections. Data is not valid for the first four conversions after a device reset. Nap Mode Refer to the NAP MODE section in the DESCRIPTION AND TIMING DIAGRAMS section for information. 20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 ADS7882 www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008 APPLICATION INFORMATION LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7882 circuitry. As the ADS7882 offers single-supply operation, it is often used in close proximity with digital logic, micro-controllers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve acceptable performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to the end of sampling (within quiet sampling time) and just prior to latching the output of the analog comparator during the conversion phase. Thus, driving any single conversion for an n-bit SAR converter, there are n+1 windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS7882 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and 1-µF storage capacitor are recommended from REFIN (pin 1) directly to REFM (pin 48). The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are too close to the grounding point of a micro-controller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a 5-V power supply plane that is separate from the connection for +VBD and digital logic until they are connected at the power entry point onto the PCB. Power to the ADS7882 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 3 for the placement of capacitor. In addition to a 0.1-µF capacitor, a 1-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors, all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Table 3. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE CONVERTER ANALOG SIDE SUPPLY PINS Pairs of pins that require a shortest path to decoupling capacitors (4,5), (9,8), (10,11), (13, 15), (43, 44) (46, 45) Pins that require no decoupling 14, 12 Analog 5 V CONVERTER DIGITAL SIDE (24, 25), (34, 35) +VA 0.1 µF 1 µF ADS7882 AGND AGND 0.1 µF REFOUT External Reference from REF5025 or REF3225 REFIN 1 µF 0.1 µF REFM AGND 21 Ω Analog Input Circuit +IN 21 Ω −IN Figure 33. Using External Reference Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 21 ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com Analog 5 V +VA 0.1 µF 1 µF ADS7882 AGND AGND REFOUT REFIN 0.1 µF 1 µF REFM AGND 21 Ω +IN Analog Input Circuit 21 Ω −IN Figure 34. Using Internal Reference 130 pF 604 Ω Signal Input, Bipolar, "1.25 V 2.5 V DC 3 kΩ 604 Ω _ 100 Ω THS4031 12 Ω 21 Ω +IN + 21 Ω 150 pF ADS7882 −IN 1 kΩ 1 nF AGND AGND Figure 35. Typical Analog Input Circuit for Bipolar Signal 50 W _ Signal Input Unipolar 0 V–2.5 V THS4031 + 12 W 21 W 150 pF 21 W +IN ADS7882 –IN Figure 36. Typical Application Input Circuit for Unipolar Signal 22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 ADS7882 www.ti.com ........................................................................................................................................................................................... SLAS630 – DECEMBER 2008 GPIO CS GPIO BYTE GPIO CONVST ADS7882 Microcontroller P[7:0] DB[11:4] RD RD INT BUSY Figure 37. Interfacing With Microcontroller Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 23 PACKAGE OPTION ADDENDUM www.ti.com 1-Jan-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS7882IPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7882IPFBT ACTIVE TQFP PFB 48 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7882IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS7882IPFBT TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7882IPFBR TQFP PFB 48 1000 346.0 346.0 33.0 ADS7882IPFBT TQFP PFB 48 250 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. 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