LSI/CSI
LS7031
UL
®
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
(631) 271-0400 FAX (631) 271-0405
A3800
6 DECADE MOS UP COUNTER WITH 8 DECADE LATCH AND MULTIPLEXER
DESCRIPTION:
The LS7031 is a monolithic, ion implanted MOS, 6 decade up counter. The circuit includes latches, a multiplexer, leading zero blanking
and BCD data outputs.
CLOCK GENERATOR
The clock for the six decade counter (digit positions 3-8) is formed
from the internal ‘OR’ combination of B4/D2 and B8/D2 if LS7031
is used with external prescaling counters. When operated in this
fashion the maximum allowable propagaton delay between B4/D2
(H-L) and B8/D2 (L-H), measured at Vss - 1V, is 10ns. If used as
a straight six decade counter, clock pulses may be applied to
inputs B4/D2 or B8/D2 with the unused input held low. In either mode
of operation total pulse width must be minimum 62ns. See Block
Diagram.
6 DECADE UP COUNTER
The six decade ripple through counter increments on the negative
edge of the input count pulse. Maximum ripple time is 12µs
(999999 to 000000). Maximum count frequency is 7.5MHz.
December 2002
CONNECTION DIAGRAM - TOP VIEW
DIGIT
STROBE
OUTPUTS
SCAN RESET INPUT
1
40
OSC. INPUT
MSD STROBE 8
2
39
SCAN INPUT
ST R O BE 7
3
38
N.C.
ST R O BE 6
4
37
B1/D1
ST R O BE 5
5
36
B2/D1
ST R O BE 4
6
35
N.C.
34
B4/D1
33
B8/D1
32
N.C.
10
31
B1/D2
11
30
B2/D2
OVERFLOW OUTPUT 12
29
B4/D2
OVERFLOW INPUT 13
28
B8/D2
14
27
V SS
V GG
ST R O BE 3
7
ST R O BE 2
8
LSD STROBE 1
DECIMAL POINT INPUT
BLANK OUTPUT
DECADE 8 OUTPUT,
D8
9
LSI
FEATURES:
• DC to 7.5 MHz Count Frequency
• Multiplexed BCD Outputs
• DC to 500kHz Scan Frequency
• +4.75V to +15V Operation (VDD-VSS)
• Compatible with CMOS Logic
• High Input Noise Immunity
• Ability to Latch External BCD Data in the two LSD Positions
• Leading Zero Blanking with Decimal Point and Overflow Controls
• All inputs protected
• Low Power Dissipation
• 40 Pin DIP - See Figure 1
LS7031
INPUT TO
DECADE 1
LATCH
INPUT TO
DECADE 2
LATCH
DECADE 7 OUTPUT,
D7
15
26
DECADE 6 OUTPUT,
D6
16
25
N.C.
B8
17
24
N.C.
B4
18
23
V DD
B2
19
22
RESET COUNTER INPUT
B1
20
21
LOAD LATCH INPUT
BCD
DATA
OUTPUTS
FIGURE 1
DIGIT STROBES
Timing of Digit Strobes is arranged such that both edges of strobe
are guardbanded by a minimum 400ns within valid BCD data when
scan frequency is 100kHz or less. The guardband is a minimum of
RESET
200ns at 250kHz scan frequency. At 500kHz only negative edge of
All 6 counter decades are reset to zero when Reset input is brought Strobe is guaranteed to be within valid BCD data by a minimum
low for a minimum of 4µs. The Overflow flip-flop is reset at the
200ns.
same time. Reset must be high for a minimum of 1µs before next
valid count can be recorded.
OVERFLOW
The Overflow flip-flop sets on the first negative transition of the OverSCAN OSCILLATOR AND COUNTER
flow Input and remains set until Reset is brought low. Data is transThe scan counter is driven by an internal oscillator whose
ferred from Overflow flip-flop to Overflow Latch when Load is brought
frequency is determined by a capacitor connected between
low. A high at the Overflow Latch causes display to unblank. OverOscillator input and Scan input. An external scan clock applied
flow Output is output of Overflow Latch. MSB outputs of Decades
to Scan input can also drive the scan counter. Scan counter
6, 7, 8 are available for use as Overflow Input.
advances on negative edge of scan clock.
The counter scans from MSD to LSD. When Scan Reset input is
LATCHES
brought high the scan counter is forced to MSD state. Internal
Eight decades of latch are provided, two for storage of the two
synchonization guarantees proper scanning no matter when Scan external least significant decade counters and the remaining 6 for inReset is brought low relative to scan clock. Maximum scan
ternal counter outputs. All latches when Load signal is brought low
frequency is 500kHz.
for a minimum of 4µs and kept low until a minimum of 12µs has
elapsed from previous negative edge of count pulse (ripple time).
DECIMAL POINT
Storage of valid data occurs when Load signal is high for a minimum
A high at the Decimal Point input resets the Blanking flip-flop
of 1µs before next negative edge of count pulse or reset. Data is
causing the display to unblank. Decimal Point should be brought
transferred from Overflow flip-flop to Overflow latch at the same time.
high at start of digit time which has active Decimal Point.
7031-121102-1
BLANKING
Leading zero blanking is employed. At start of each MSD to LSD
scan, display is blanked until a non-zero digit or active decimal
point is encountered. Display unblanks during LSD time and whenever Overflow output is high. When Scan Reset is applied, display
blanks to prevent display damage.
Blanking information is available at Blank output.
POWER SUPPLIES
+4.75V to +15V single power supply operation is obtained when
VGG and VDD are tied together. Inputs and outputs are CMOS
compatible and Minimum Input Noise Immunity of 25% of power
supply is guaranteed except for Decade 1 and 2 inputs.
(All inputs are TTL compatible at +4.75V to +5.25V operation.)
With VGG at -12V, VDD at OV and Vss at +5V all inputs are TTL
and CMOS compatible. All outputs are CMOS compatible and
BCD and BLANK outputs also provide standard TTL compatibility. In addition, Overflow Output is low power TTL compatible.
In either mode outputs swing between VDD and Vss.
BCD DATA
Data is available in multiplexed BCD format. BCD data can be
readily demultiplexed using Digit Strobes as latch enable signals.
MAXIMUM RATINGS
PARAMETER
Storage Temperature
Operating Temperature
Voltage (any pin to Vss)
SYMBOL
Tstg
TA
Vmax
VALUE
-65 to +150
-25 to +70
-30 to +0.5
UNITS
°C
°C
V
DC ELECTRICAL CHARACTERISTICS
(VDD = VGG= OV, Vss = +4.75 to +15V, -25°C ≤ TA ≤ +70°C unless otherwise specified.)
PARAMETER
SYMBOL
MIN
Operating Supply Current
Idds
(fC = 7.5MHz)
Input Noise Immunity
Low and High
Vni
25%
(Vss-VDD)
EXTERNAL
Input
Voltage
“0"
Vil
Vss - 20
DECADE
Input
Voltage
“1"
Vih
Vss - 1.0
INPUTS
{
D6, D7, D8
OF, BCD
Blank
(See Note 1)
{
MAX
15
UNITS
mA
-
V
Vss - 3.95
Vss
V
V
Output Voltage “0"
Output Voltage “1"
Vol
Voh
Vss - 1.0
+0.2
-
V
V
Output Voltage “0"
(sinking 10µA)
Vol
-
+0.5
V
-
0.05
0.25
0.90
2.0
3.0
3.0
4.5
-
mA
mA
mA
mA
mA
mA
mA
Output Current “1"
Segment
and
Strobe
Outputs
(See Note 2)
Vss = 4.75V(Voh = Vss - 0.5V)
(Voh = Vss - 1V)
(Voh = Vss - 4V)
Vss = 10V (Voh = Vss - 2V)
(Voh = Vss - 3V)
Vss = 15V (Voh = Vss - 2V)
(Voh = Vss - 3V)
NOTE 1: Current Sink = Same as segment and strobe outputs.
Current Source = N/A at Voh = Vss - 0.5V for Vss = +4.75V
35µA at Voh = Vss -1V for Vss = +4.75V
40% of segment and strobe outputs at all other specified operating points.
NOTE 2: Limit segment current to 6mA maximum.
The following inputs have internal pull down resistors to VDD with maximum sink current of 5µA at Vss input.
Scan Reset
B1/D1
B1/D2
Decimal
B2/D1
B2/D2
Overflow
B4/D1
B4/D2
B8/D1
B8/D2
TTL COMPATIBLE OUTPUTS:
SCAN OSCILLATOR CAPACITANCE
POWER SUPPLIES: Vss = +5V ± 5%, VDD = 0V, VGG = -12V ± 5%
OUTPUT LEVELS: “1" Level ≥ Vss - 0.5V (sourcing 100µA)
“0" Level ≤ 0.4V (sinking 1.6mA)
“1" Level ≥ Vss -.5V (sourcing 40µA)
“0" Level ≤ 0.4V (sinking .18mA)
}
}
BLANK AND BCD
DATA OUTPUTS
OVERFLOW
OUTPUT
All other outputs as specified for single power supply, Vss = +15V operation.
Inputs as specified for single power supply, Vss = +5V ± 5% operation.
7031-110201-2
TYPICAL OSCILLATOR FREQUENCY
50pF
100pF
470pF
4.75V
40.0 kHz
22.2 kHz
5.0 kHz
10V
24.2kHz
14.8kHz
3.6kHz
15V
22.2 kHz
13.8 kHz
3.5 kHz
ELECTRICAL CHARACtERISTICS:
(VDD = VGG = OV, Vss = +4.75 to +15V, -25˚C ≤ TA ≤ +70˚C unless otherwise specified.)
PARAMETER
Count Test and Count frequency
(Vss = +5V ± 5%)
(Vss = +10V)
(Vss = +15V)
Scan frequency
SYMBOL
MIN
MAX
UNITS
fc, ftc
fc, ftc
fc, ftc
fsc
DC
DC
DC
DC
7.5
6
5
500
MHz
MHz
MHz
kHz
Count Pulse Width
(Pulse applied to B4/D2 or B8/D2;
‘OR’ combination ofB4/D2 and B8/D2)
(Vss = +5V ± 5%)
(Vss = +10V)
(Vss = +15V)
**Propagation Delay
(B4/D2(H-L) to B8/D2 (L-H) at
Vss -1.0V)
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62
83
100
-
ns
ns
ns
Count Ripple Time
Load Pulse Width
Load Removal Time
Reset Pulse Width
Reset Removal Time
tcr
tlpw
tlr
trpw
trr
Overlap
4
4
-
10
1
1
ns
µs
µs
µs
µs
Rise and Fall Time
Count Pulse
Reset Pulse
Test Count Pulse
trfc
trfr
trftc
-
4
4
80
µs
µs
µs
tgb
400
-
ns
tgb
200
-
ns
tgb
200
-
ns
*Strobe Guard Band time
(fSC ≤ 100kHz ≤ 250kHz)
*Strobe Guard Band time
(100kHz ≤ fSC ≤ 250kHz)
*Strobe Guard Band time
(250kHz ≤ fSC≤ 500kHz)
negative edge only
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
*Defines the minimum time from strobe edges to switching BCD data.
PRESCALE
DIGIT 2
PRESCALE
DIGIT 1
BCD
750MHz
tgb
75MHz
BCD CNTR 1
BCD CNTR 2
tgb
1
2
4
1
8
2
4
8
7.5MHz
STROBE
B1/D1 - B8/D1
B1/D1 - B8/D1
FIGURE 2. GUARD BANDED STROBE
LS7031
DIGIT STROBES
1
Vss - 1.0
DIGIT DRIVERS
B4/D2
tpr
BLANK
Vss - 1.0
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7031-110201-3
8
BCD TO SEVEN
SEGMENT
DECODER/DRIVER
B8/D2
B4/D2
or
B8/D2
4
(LSD)
(MSD)
**Propagation Delay and Pulse Width
2
8 DIGIT DISPLAY
FIGURE 3. TYPICAL APPLICATION
DECIMAL POINT
INPUT
10
27 Vss
8 DIGIT STROBE OUTPUTS
SCAN RESET INPUT
(RESET TO MSD)
9
8
7
6
5
4
3
26 VGG
2
BLANKING
F/F
1
LSD
MSD
23 VDD
S
OUTPUT
BUFFERS
R
Q
11 BLANK OUT
NZ
OSC. INPUT
40
OSCILLATOR
OR
BUFFER
R
C
LSD
8 STATE STATIC SCAN
COUNTER & DECODED
MSD
39
SCAN INPUT
8
1
3
2
7
4
B1
B1
B2
B2
B2
B4
B4
B4
B4
B8
B8
B8
B8
MUX
GATE
1 2 4 8
G
MUX
GATE
1 2 4 8
G
MUX
GATE
1 2 4 8
G
MUX
GATE
1 2 4 8
G
B1
B1
B2
1 2 4 8
G
6
5
B1
MUX
GATE
1 2 4 8
G
B4
G
B1
20
B2
B4
19 BCD
DATA
OUTPUT
18
B8
17
B8
1 2 4 8
1 2 4 8
MUX
GATE
DATA
OUTPUT
BUFFER
B2
MUX
GATE
G
MUX
GATE
OVERFLOW
12 OUTPUT
4 BIT
LATCH
ST
4 BIT
LATCH
ST
4 BIT
LATCH
ST
4 BIT
LATCH
ST
4 BIT
LATCH
ST
4 BIT
LATCH
ST
4 BIT
LATCH
ST
4 BIT
LATCH
ST
ST
LOAD
LATCH
21
INPUT
1 BIT
LATCH
13 OVERFLOW
INPUT
1 2 4 8
BCD
C
COUNTER
R
RESET
INPUT 22
37 36 34 33
B1 B2 B4 B8
DIGIT ONE
1 2 4 8
C
BCD
COUNTER
R
1 2 4 8
BCD
C
COUNTER
R
1 2 4 8
C
BCD
COUNTER
R
1 2 4 8
C
BCD
COUNTER
R
1 2 4 8
C
BCD
COUNTER
R
C
R
31 30 29 28
B1 B2 B4 B8
DIGIT TWO
16
FIGURE 4. LS7031 BLOCK DIAGRAM
D6 OUTPUT
15
D7 OUTPUT
14
D8 OUTPUT
OVFLW
F/F