LSI/CSI UL ® LS7061/7063 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 Aug. 1998 32 BIT/DUAL 16 BIT BINARY UP COUNTER WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS PIN ASSIGNMENT - TOP VIEW B4 OUT 23 B5 OUT B3 OUT 3 22 B0 IN B6 IN 4 21 B1 IN B2 OUT 5 20 B6 OUT B5 IN 6 19 B2 IN B1 OUT 7 18 B7 OUT B4 IN 8 17 B3 IN B0 OUT (COUNT) B7 IN LS7061 24 2 V DD (+V) 1 LSI FEATURES: • DC to 15 MHz Count Frequency • Byte Multiplexer • DC to 1 MHz Scan Frequency • +4.75V to +5.25V Operation (VDD-VSS) • Latch Provided for External High Speed Counter Byte, Effectively Extending Count Frequency to 3.84GHz • Three-State Data Outputs, Bus and TTL Compatible • Inputs TTL and CMOS Compatible • Unique Cascade Feature Allows Multiplexing of Successive Bytes of Data in Sequence in Multiple Counter Systems • LS7061, LS7063 (DIP); LS7061-S, LS7063-S (SOIC) (See Figures 1 & 2) DESCRIPTION: The LS7061/LS7063 is a monolithic, ion implanted MOS Silicon Gate, 32 bit/dual 16 bit up counter. The IC includes 40 latches, multiplexer, eight three-state binary data output drivers and output cascading logic. 9 16 TEST COUNT R E S E T 10 15 SCAN RESET/LOAD CASCADE ENABLE OUT 11 14 ENABLE Vss (-V) 12 13 SCAN FIGURE 1 DESCRIPTION OF OPERATION: COUNT B - LS7063 Count pulses may be applied to the last 16 bits of the binary counter through this input. The counter advances on the negative transition of these pulses. RESET All 32 counter bits are reset to zero when RESET is brought low for a minimum of 1µs. RESET must be high for a minimum of 300ns before next valid count can be recorded. COUNT B must be held low when RESET is brought low to ensure proper reset of Counter B for LS7063. TEST COUNT - LS7061 Count pulses may be applied to the last 16 bits of the binary counter through this input, as long as Bit 16 of the counter is a low. The counter advances on the negative transition of these pulses. This input is intended to be used for test purposes. 7061/63-083198-1 V DD (+V) 1 24 B4 OUT (COUNTA) B7 IN 2 23 B5 OUT B3 OUT 3 22 B0 IN B6 IN 4 21 B1 IN B2 OUT 5 20 B6 OUT B5 IN 6 19 B2 IN 18 B7 OUT 17 B3 IN LS7063 COUNT - LS7061, COUNT A - LS7063 Input count pulses to the 32 (first 16) bit counter may be applied through this input. This input is the most significant bit of the external data byte. PIN ASSIGNMENT - TOP VIEW LSI 32 (16) BIT BINARY UP COUNTER - LS7061 (LS7063) The 32 (16) bit static ripple through counter increments on the negative edge of the input count pulse. Maximum ripple time is 4µs (2µs) - transition count of 32 (16) ones to 32 (16) zeros. Guaranteed count frequency is DC to 15MHz. See Figure 8A (8B) for Block Diagram. B1 OUT 7 B4 IN 8 B0 OUT 9 16 COUNT B 10 15 SCAN RESET/LOAD CASCADE ENABLE OUT 11 14 ENABLE Vss (-V) 12 13 SCAN RESET FIGURE 2 LATCHES - LS7061 (LS7063) 40 bits of latch are provided, eight for storage of the contents of a high speed external prescaling counter and the remaining 32 for the contents of the counter data. All latches are loaded when the LOAD input is brought low for a minimum of 1µs and kept low until a minimum of 4µs (2µs) has elapsed from previous negative edge of count pulse (ripple time). Storage of valid data occurs when LOAD is brought high for a minimum of 250ns before next negative edge of count pulse or RESET. SCAN COUNTER AND DECODER The scan counter is reset to the least significant byte position (State 1) when SCAN RESET input is brought low for a minimum of 1µs. The scan counter is enabled for counting as long as the ENABLE input is held low. The counter advances to the next significant byte position on each negative transition of the SCAN pulse. When the scan counter advances to State 6 it disables the Output Drivers and stops in that state until SCAN RESET is again brought low. SCAN When the scan counter is enabled, each negative transition of this input advances the scan counter to its next state. When SCAN is low the Data Outputs are disabled. When SCAN is brought high the Data Outputs are enabled and present the latched counter data corresponding to the present state of the scan counter. Therefore, in microprocessor applications, the Data Output Bus may be utilized for other activities while new data is propagating to the outputs. This positive SCAN pulse can be viewed as a "Place the next byte on my bus" instruction from the microprocessor. Minimum positive and negative pulse widths of 500ns for the SCAN signal are required for scan counter operation. ENABLE When this input is high, the scan counter and the Data Outputs are disabled. When ENABLE is low, the scan counter and Data Outputs are enabled for normal operation. Transition of this input should only be made while the SCAN input is in a low state in order to prevent false clocking of the scan counter. CASCADE ENABLE This output is normally high. It transitions low and stays low when the scan counter advances to State 6. In a multiple counter system this output is connected to the ENABLE input of the next counter in the cascade string. The SCAN input and SCAN RESET/LOAD input are carried to all the counters in the "Cascade". Counter 1 then presents its bytes of data to the Output Bus on each positive transition of the SCAN pulse as previously discussed. When State 6 of Counter 1 is achieved, Counter 2 presents its data to the Output Bus. This sequence continues until all counters in the cascade have been addressed. See Figure 5 for an illustration of a 3 device cascade design. This output is TTL and CMOS compatible. THREE-STATE DATA OUTPUT DRIVERS The eight Data Output Drivers are disabled when either ENABLE input is high, the scan counter is in State 6, or the SCAN input is low. The Output Drivers are TTL and Bus compatible. SCAN RESET/LOAD When this input is brought low for a minimum of 1µs, the scan counter is reset to State 1, the least significant byte position, and the latches are simultaneously loaded with new count information. tRSCPW SCAN RESET ENABLE tRSCR SCAN tSCPW tSCPW ST1 (int.) ST2 (int.) ST3 (int.) ST4 (int.) ST5 (int.) ST6 (int.) ENABLE (int.) t DCE t DCE ENABLE (int.) CASCADE ENABLE DATA OUTPUTS t DOD t DOE valid LSB valid LSB+1 valid LSB +2 valid valid LSB+3 MSB FIGURE 3. SCAN COUNTER & DECODER OUTPUTS TIMING DIAGRAM 7061/63-083198-2 ABSOLUTE MAXIMUM RATINGS: PARAMETER StorageTemperature Operating Temperature Voltage (any pin to VSS) SYMBOL TSTG TA VIN VALUE -55 to +150 0 to +70 +10 to -0.3 UNIT °C °C V DC ELECTRICAL CHARACTERISTICS: (VDD = +5V ± 5%, VSS = 0V, TA = 0˚C to + 70˚C unless otherwise noted.) PARAMETER Power Supply Current SYMBOL IDD Min - MAX 15 UNIT mA Input High Voltage Input Low Voltage VIH VIL +3.5 0 VDD +0.6 V V CONDITIONS At Maximum Operating Frequency VDD = Max, Outputs No Load - Output High Voltage CASCADE ENABLE VOH VDD-0.2 +2.4 - V V IO = 0, VDD = Min IO = -100µA, VDD = Min +2.4 +2.0 - V V IO = -260µA, VDD = Min IO = -750µA, VDD = Min - +0.2 +0.4 V V IO = 0, VDD = Min IO = 1.6mA, VDD = Min +0.4 V IO = 1.6mA, VDD = Min IOL 3.0 4.8 7.3 5.7 4.0 2.2 - 1 mA mA mA mA mA mA µA VO = +1.2V, VDD = Min VO = +0.8V, VDD = Min VO = +0.4V, VDD = Min VO = +1.2V, VDD = Min VO = +0.8V, VDD = Min VO = +0.4V, VDD = Min VO = +.4V to +2.4V,VDD = Min CIN COUT ILI - 6 12 1 pF pF µA TA = 25˚C, f = 1MHz TA = 25˚C, f = 1MHz VDD = Max IIH IIL IIH - -2.5 -5 5 µA µA µA VDD = Max, VIH = +3.5 VDD = Max, VIL = 0 VDD = Max, VIH = +3.5 IIL - 1 µA VDD = Max, VIL = 0 B0 - B7 Output Low Voltage CASCADE ENABLE VOL B0 - B7 Output Source Current B0 - B7 Outputs Output Sink Current B0 - B7 Outputs Output Leakage Current B0 - B7 (Off State) Input Capacitance Output Capacitance Input Leakage Current ENABLE, RESET, SCAN Input Current *SCAN RESET/LOAD **B0-B7, COUNT B, TEST COUNT Isource Isink *Input has internal pull-up resistor to VDD ** Inputs have internal pull-down resistor to VSS The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7061/63-090198-3 DYNAMIC ELECTRICAL CHARACTERISTICS: (Refer to Figure 3, Timing Diagram) (VDD = +5V ± 5%, VSS = 0V, TA = 0˚C to +70˚C unless otherwise noted.) PARAMETER Count Frequency (All Count inputs) Count Pulse Width (All Count Inputs) SYMBOL fc MIN DC MAX 15 UNIT MHz tCPW 30 - ns Measured at 50% point, Max tr, tf = 10ns Count Rise & Fall time (Pins 2, 16) tr, tf - 30 µs - Count Ripple Time (Pins 2 - LS7061) tCR - 4 µs Transition from32 ones to 32 zeros from negative edge of count pulse Count Ripple Time (Pin 13 - LS7061) (Pins 2,13 - LS7063) RESET Pulse Width (All Counter Stages Fully Reset) tCR - 2 µs tRPW 500 - ns Transition of 16 bits from all ones to all zeros from negative edge of count pulse Measured at 50% point Max tr, tf = 200ns tRR - 250 ns SCAN Frequency SCAN Pulse Wildth fSC tSCPW 500 1 - MHz ns SCAN RESET/LOAD Pulse Width (All latches loaded and Scan Counter Reset to Least Significant Byte) tRSCPW 1 - µs SCAN RESET/LOAD Removal Time (Reset Removed from Scan Counter; Load Command Removed From Latches) tRSCR - 250 ns Measured from SCAN RESET/ LOAD at VIH Output Disable Delay Time (B0 - B7) tDOD - 200 ns Output ENABLE Delay Time (B0 - B7) tDOE - 200 ns Output Delay Time CASCADE ENABLE tDCE - 300 ns Transition to Output High Impedance State Measured From Scan at VIL or ENABLE at VIH Transition to Valid On State Measured from Scan at VIH and ENABLE at VIL; Delay to Valid Data Levels for COL =10pF and one TTL Load or Valid Data Currents for High Capacitance Loads Negative Transition from Scan at VIL and ST5 of Scan Counter or Positive Transition From SCAN RESET/LOAD at VIL to Valid Data Levels for COL = 10pF and one TTL Load RESET Removal Time (Reset Removed From All Counter Stages) 7061/63-083198-4 CONDITIONS - Measured from RESET signal at VIH Measured at 50% point Max tr, tf = 100ns Measured at 50% point Max tr, tf = 200ns tRPW tRPW RESET tRR + tCPW tRSCR tRR+tCPW COUNT LOAD tCPW tCR tCPW tRSCPW FIGURE 4. COUNTER TIMING DIAGRAM OUTPUT DATA BUS A CE EN SC RESET SC B CE EN SC RESET SC C CE EN SC RESET SC ENABLE SCAN RESET SCAN FIGURE 5. 7061/63-083198-5 ILLUSTRATION OF A 3 DEVICE CASCADE END OF SCAN SCAN RESET ENABLE SCAN CASCADE ENABLE A CASCADE ENABLE B CASCADE ENABLE C (END OF SCAN) 1 DATA BYTE ON BUS PACKAGE 2 3 4 5 1 2 A 3 4 5 1 2 B 3 4 C FIGURE 6. TIMING DIAGRAM FOR THE 3 DEVICE CASCADE FIGURE 7. APPLICATION EXAMPLE: HIGH SPEED DIFFERENTIAL ENERGY ANALYZER LS7061 OR LS7063 DETECTOR VOLTAGE DISCRIMINATORS PRESCALERS SCAN EN RADIATION PULSE Pulse voltage proportional to energy of radiation CE B U S EN CE EN CE CASCADE ENABLE NOTE : The processor subtracts counts from successive counters to determine the differential energy spectrum 7061/63-083198-6 PROCESSOR 5 FIGURE 8A. LS7061 BLOCK DIAGRAM CASCADE ENABLE DATA OUT 11 LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 V DD 1 +V V SS 12 -V ENABLE SCAN 9 13 15 SCAN RESET/LOAD ST2 ST1 ST3 ST4 5 3 24 23 20 18 ST6 6 STATE STATIC SCAN COUNTER AND DECODER C SC (STOPS IN STATE 6 UNTIL SCAN RESET CAUSES RESET TO STATE ONE) R SC 14 7 ENABLE THREE STATE EN OUTPUT DRIVERS 8 BITS ST5 8 BIT MUX BUS MUX GATE G G LOAD 8 BIT LATCH LOAD MUX GATE G 8 BIT LATCH B0 LOAD B7 G 8 BIT LATCH B0 8 BIT BINARY COUNTER C MUX GATE B7 8 BIT LATCH LOAD B7 B0 8 BIT BINARY COUNTER C R MUX GATE G 8 BIT LATCH B0 8 BIT BINARY COUNTER C R LOAD MUX GATE B7 8 BIT BINARY COUNTER C R R 10 22 B0 19 RESET 4 8 B2 17 B4 6 B6 2 B3 B5 B7 21 B1 16 (COUNT) TEST COUNT DATA IN FIGURE 8B. CASCADE ENABLE LS7063 BLOCK DIAGRAM DATA OUT 11 LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 V DD 1 +V V SS 12 -V ENABLE SCAN 9 6 STATE STATIC SCAN COUNTER AND C SC DECODER (STOPS IN STATE 6 UNTIL SCAN RESET R SC CAUSES RESET TO STATE ONE) 14 13 SCAN RESET/LOAD 15 ST1 ST2 ST3 ST4 7 5 3 24 23 20 18 ST6 ENABLE THREE STATE OUTPUT DRIVERS EN 8 BITS ST5 8 BIT MUX BUS MUX GATE G G 8 BIT LATCH LOAD LOAD B0 MUX GATE 8 BIT LATCH B7 8 BIT BINARY COUNTER C R G LOAD B0 MUX GATE G 8 BIT LATCH LOAD B7 B0 8 BIT BINARY COUNTER C R 16 22 B0 8 19 21 B1 B2 17 B3 B4 4 6 B5 DATA IN B6 COUNT B 2 B7 (COUNT A) 8 BIT LATCH B7 8 BIT BINARY COUNTER C R MUX GATE G LOAD B0 MUX GATE 8 BIT LATCH B7 8 BIT BINARY COUNTER C R 10 RESET