SN74ALS845 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SDAS233A – DECEMBER 1983 – REVISED JANUARY 1995 • • • • • • 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Provides Extra Bus-Driving Latches Necessary for Wider Address/Data Paths or Buses With Parity Buffered Control Inputs to Reduce dc Loading Effects Power-Up High-Impedance State Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs DW OR NT PACKAGE (TOP VIEW) OE1 OE2 1D 2D 3D 4D 5D 6D 7D 8D CLR GND description 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC OE3 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q PRE LE This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. Because the clear (CLR) and preset (PRE) inputs are independent of the clock (CLK) input, taking CLR low causes the eight Q outputs to go low. Taking PRE low causes the eight Q outputs to go high. When both PRE and CLR are taken low, the outputs follow the preset condition. The buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a normal logic state (high or low levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. The output enables do not affect the internal operation of the latches. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. The -1 version of the SN74ALS845 is identical to the standard version, except that the recommended maximum IOL for the -1 version is increased to 48 mA. The SN74ALS845 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS PRE CLR OE1 OE2 OE3 LE D OUTPUT Q L X L L L X X H H L L L L X X L H H L L L H L L H H L L L H H H H H L L L L L Q0 X X X X H X X Z X X X H X X X Z X X H X X X X Z Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALS845 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SDAS233A – DECEMBER 1983 – REVISED JANUARY 1995 logic symbol† OE1 & 1 2 EN OE2 OE3 23 14 PRE 11 CLR LE 1D 2D 3D 4D 5D 6D 7D 8D 13 3 S2 R C1 22 1D 2 4 21 5 20 6 19 7 18 8 17 9 16 10 15 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE1 OE2 1 2 23 OE3 PRE CLR LE 14 11 13 S2 1D C1 3 1D 2 R To Seven Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 22 1Q SN74ALS845 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SDAS233A – DECEMBER 1983 – REVISED JANUARY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions VCC VIH Supply voltage VIL IOH Low-level input voltage High-level input voltage MIN NOM MAX 4.5 5 5.5 2 UNIT V V 0.8 V High-level output current – 2.6 mA IOL Low level output current Low-level 24 48‡ mA tw Pulse duration tsu th Setup time, data before LE↓ CLR or PRE low 35 LE high 20 ns 10 Hold time, data after LE↓ ns 5 TA Operating free-air temperature ‡ Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VCC = 4.5 V, IOH = – 2.6 mA IOL = 12 mA VCC = 4.5 V MIN VCC – 2 2.4 IOL = 24 mA IOL = 48 mA‡ IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO¶ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V ICC VCC = 5.5 V TYP§ MAX UNIT – 1.2 V V 3.2 0.25 0.4 0.35 0.5 0.35 0.5 20 – 30 V µA – 20 µA 0.1 mA 20 µA – 0.1 mA – 112 mA Outputs high 21 36 Outputs low 41 67 Outputs disabled 25 42 mA ‡ Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V § All typical values are at VCC = 5 V, TA = 25°C. ¶ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALS845 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SDAS233A – DECEMBER 1983 – REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPLH tPHL PRE CLR Q tPZH tPZL OE Q tPHZ tPLZ OE Q VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX† MIN MAX 2 13 4 18 5 21 8 26 6 22 6 24 3 16 5 18 1 11 2 12 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns SN74ALS845 8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SDAS233A – DECEMBER 1983 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V Data Input tw th tsu 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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