SN74BCT29821 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCBS021D – FEBRUARY 1989 – REVISED NOVEMBER 1993 • • • • DW OR NT PACKAGE (TOP VIEW) State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) 3-State Buffer-Type Outputs Drive Bus Lines Directly Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT) OE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND description This 10-bit bus-interface flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q CLK The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs will be true to the data (D) inputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enable (OE) does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74BCT29821 is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 SN74BCT29821 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCBS021D – FEBRUARY 1989 – REVISED NOVEMBER 1993 logic symbol† OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1 13 2 logic diagram (positive logic) EN OE C1 23 1D 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 CLK 1 13 1Q C1 2Q 3Q 1D 2 23 1Q 1D 4Q 5Q 6Q 7Q To Nine Other Channels 8Q 9Q 10Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . – 0.5 V to 5.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. recommended operating conditions MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IIK Low-level input voltage 0.8 V Input clamp current –18 mA IOH IOL High-level output current – 24 mA Low-level output current 48 mA TA Operating free-air temperature 70 °C 2–2 High-level input voltage 2 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V SN74BCT29821 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCBS021D – FEBRUARY 1989 – REVISED NOVEMBER 1993 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 4.5 V, VOH VCC = 4 4.5 5V VOL II VCC = 4.5 V, VCC = 5.5 V, IIH IIL VCC = 5.5 V, VCC = 5.5 V, IOS‡ IOZH VCC = 5.5 V, VCC = 5.5 V, IOZL ICCL VCC = 5.5 V, VCC = 5.5 V, ICCH ICCZ Ci MIN II = –18 mA IOH = – 15 mA 2.4 IOH = – 24 mA IOL = 48 mA TYP† MAX UNIT –1.2 V 3.3 V 2 0.42 VI = 7 V VI = 2.7 V –10 VI = 0.5 V VO = 0 –75 VO = 2.7 V VO = 0.5 V 0.55 V 0.1 mA –75 µA – 0.2 mA – 250 mA 20 µA – 20 µA Outputs open 25 35 mA VCC = 5.5 V, VCC = 5.5 V, Outputs open 6 10 mA 2 6 mA VCC = 5 V, VCC = 5 V, VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V Outputs open Co † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 5.5 pF 7 pF timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C MIN MAX 125 MIN MAX UNIT 0 125 MHz fclock tw Clock frequency 0 Pulse duration, CLK high or low 7 7 ns tsu th Setup time, data before CLK↑ High or low 7 7 ns Hold time, data after CLK↑ High or low 1 1 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Note 2) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C MIN TYP MIN 125 CLK Q OE Q OE Q tPLZ NOTE 2: Load circuits and voltage waveforms are shown in Section 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT MAX 125 MHz 1.5 7.5 10 1.5 12 1.5 6.5 9 1.5 10 2 7.5 10 2 12 2 9 12 2 13 2 5 7 2 8 2 5 7 2 8 ns ns ns 2–3 SN74BCT29821 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCBS021D – FEBRUARY 1989 – REVISED NOVEMBER 1993 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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