October 1998 ML2037* 500kHz, Serial Input, Programmable Sine Wave Generator with Digital Gain Control GENERAL DESCRIPTION FEATURES The ML2037 is a precision programmable sine wave generator with a frequency range of DC to 500kHz. The device is capable of generating a wide frequency range of low distortion sine waves with no external passive components. The frequency of the sine wave output is programmed by a 16-bit word that is loaded through a serial input. The sine wave output frequency is determined by the programmed value and the clock frequency. The clock frequency is derived from either an external crystal connected to the device or an external clock input to provide a stable and accurate frequency reference. ■ Programmable output frequency: DC to 400kHz—using a crystal DC to 500kHz—using an external digital clock ■ 3-wire SPI compatible serial interface with double buffered latch for programming the frequency ■ Digital gain control for programming output amplitude ■ SYNC input for synchronization of multiple sine waves ■ Shutdown pin for sleep mode ■ Single 5V power supply operation The sine wave output of the ML2037 is filtered and has a programmable amplitude that is digitally programmed in 0.5V steps. The maximum amplitude is 2.0VP-P centered at a 2.5V level. The device functions from a single 5V power supply and has a shutdown pin to put the device into a low power mode that disables the output. A sync input is provided to allow the synchronization of more than one device in a system. * This Part Is End Of Life As Of August 1, 2000 BLOCK DIAGRAM 11 AVCC 9 16 13 AVCC SHDN 14 G0 15 G1 AGND REFERENCE DVCC CLK IN 8-BIT DAC CRYSTAL OSCILLATOR D GND 1 5 8 12 D GND CLK OUT 3 S ENABLE ÷2 GAIN CONTROL & SMOOTHING FILTER OUT 10 8 PHASE ACCUMULATOR 512 POINT SINE LOOK-UP TABLE 16 16-BIT DATA LATCH 7 S CLK 16 4 S DATA IN 16-BIT SHIFT REGISTER 6 2 SYNC 1 ML2037 PIN CONFIGURATION ML2037 16-Pin PDIP (P16) 16-Pin Wide SOIC (S16W) D GND 1 16 DVCC SYNC 2 15 G1 CLK OUT 3 14 G0 S CLK 4 13 CLK IN D GND 5 12 AVCC S DATA IN 6 11 AVCC S ENABLE 7 10 OUT SHDN 8 9 A GND TOP VIEW PIN DESCRIPTION PIN NAME FUNCTION 1, 5 D GND Ground connection for the digital sections of the IC. 2 SYNC 3 NAME FUNCTION 9 A GND Ground reference for analog sections of the IC and reference for OUT. Synchronization input. Holding this pin low stops the sine wave output, and resets the phase to zero. 10 OUT Sine wave output. The amplitude of the sine wave will vary around a 2.5V DC level. CLK OUT Output of the internal high frequency clock generator. fCLK OUT = ½fCLK IN. 11,12 AVCC Power supply for the analog sections of the IC. 4 S CLK Serial data clock input. Serial data is clocked into the shift register on falling edges of S CLK. 13 CLK IN 6 S DATA IN Serial data input for programming the output frequency. Input of the internal high frequency clock generator. This pin is either driven from an external clock input or connected to a crystal for use with the internal oscillator. 14 G0 7 S ENABLE Serial interface enable control. A logic high on this pin allows data to be entered into the latch. Output gain control. Works with G1 to set the output amplitude to one of four different full scale ranges. 15 G1 8 SHDN A logic high on this pin causes the output of the generator to shut off and places the IC in a low power standby mode. Output gain control. Works with G0 to set the output amplitude to one of four different full scale ranges. 16 DVCC Power supply for the digital sections of the IC. 2 PIN ML2037 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Lead Temperature (Soldering, 10 sec) ..................... 260ºC Thermal Resistance (qJA) Plastic DIP ....................................................... 80ºC/W SOIC .............................................................. 105ºC/W AVCC, DVCC ................................................................................. 7V Voltage on any other pin .... AGND - 0.3V to AVCC + 0.3V Input Current ........................................................ ±25mA Junction Temperature .............................................. 150ºC Storage Temperature Range ...................... –65ºC to 150ºC OPERATING CONDITIONS Temperature Range ML2037CX ................................................. 0ºC to 70ºC ML2037IX ............................................... -40ºC to 85ºC AVCC, DVCC Range .................................. 4.75V to 5.25V ELECTRICAL CHARACTERISTICS Unless otherwise specified, AVCC = DVCC = 4.75V to 5.25V, SHDN = 0V, CLK IN = 25.6MHz (crystal) or 32MHz (external clock), CL = 50pF, RL = 1kW, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS OUTPUT HD SND Harmonic Distortion 20Hz to 31.25kHz -45 dB (2nd and 3rd Harmonic) 31.25kHz to 500kHz -40 dB Signal to Noise + Distortion 1kHz to 31.25kHz, fOUT BW < 31.25kHz -45 dB 31.35kHz to 500kHz, fOUT BW < 500kHz -40 dB Gain Error PSRR fOUT<125kHz, AVCC = 5V, G1=1, G0=1 C Suffix ±0.15 dB fOUT<125kHz, AVCC = 5V, G1=1, G0=1 I Suffix ±0.25 dB 125kHz<fOUT<500kHz, AVCC = 5V, G1=1, G0=1 Both ±0.5 dB Idle Noise SHDN = 5V 500 µVrms Power Supply Rejection Ratio 200mVP-P, fOUT = 0 - 100kHz -40 dB DC Output Voltage Peak-to-Peak Output Voltage 2.4 2.6 V G1 = 0, G0 = 0 0.5 VP-P G1 = 0, G0 = 1 1.0 VP-P G1 = 1, G0 = 0 1.5 VP-P G1 = 1, G0 = 1 1.88 2.0 2.12 VP-P 1.5 V OSCILLATOR CLK IN Input Low Voltage CLK IN Input High Voltage CLK IN Input Low Current External Clock CLK IN Input High Current External Clock 3.5 V -250 µA 250 CLK IN Input Capacitance CLK IN Maximum Frequency CLK OUT to CLK IN Frequency Ratio 12 External Clock pF 32 0.49 µA MHz 0.5 0.51 3 ML2037 ELECTRICAL CHARACTERISTICS SYMBOL (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS OSCILLATOR (Continued) tR CLK OUT Rise Time CL = 25pF, See Timing Diagram 2 8 ns tF CLK OUT Fall Time CL = 25pF, See Timing Diagram 2 8 ns 1.0 V LOGIC VIL Input Low Voltage VIH Input High Voltage DVCC - 1 V IIL Input Low Current -1 µA IIH Input High Current VOL Output Low Voltage IOL = -2mA VOH Output High Voltage IOH = 2mA fS CLK Serial Clock Frequency 1 µA 0.4 V 4.0 V 0.01 10 MHz tPW Serial CLock Pulse Width 40 ns tSSD S DATA IN Setup Time 10 ns tHSD S DATA IN Hold Time 10 ns tSSENS S ENABLE Setup Time 30 ns tSSENH S ENABLE Hold Time 50 ns tDSEN Delay from S ENABLE to Stable Output fCLK IN = 32MHz 500 ns Delay from SYNC to Output Start fCLK IN = 32MHz 500 ns AVCC Current fCLK IN = 16MHz 35 45 mA fCLK IN = 32MHz 40 50 mA 10 µA tDSYNC SUPPLY AICC SHDN = 5V DICC DVCC Current fCLK IN = 16MHz 10 14 mA fCLK IN = 32MHz 16 20 mA 30 µA SHDN = 5V Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. tPW tPW S CLK tSSD S DATA IN tHSD D0 D1 D2 D14 D15 tSSENH tSSENS S ENABLE Timing Diagram 1. fCLK IN CLK IN fCLK OUT CLK OUT Timing Diagram 2. 4 tR tF ML2037 FUNCTIONAL DESCRIPTION The ML2037 is composed of a programmable frequency generator, a sine wave generator, a crystal oscillator, and a digital interface. The functional block diagram is shown in Figure 1. The output filter smooths the analog output by removing the high frequency sampling components. The resultant voltage on VOUT is a sinusoid with the second and third harmonic distortion components at least 40dB below the fundamental. PROGRAMMABLE FREQUENCY GENERATOR The programmable frequency generator produces a digital output whose frequency is determined by a 16-bit digital word. The frequency generator is composed of a phase accumulator which is clocked at ½fCLK IN. The value stored in the data latch is added to the phase accumulator every two cycles of CLK IN. The frequency of the analog output is equal to the rate at which the accumulator overflows and is given by the following equation: fOUT = 0 5 fCLKIN ´ D15 ® D0 DEC 22 2 (1) Where (D15–D0) is the decimal value of the programming word. The frequency resolution and the minimum frequency are the same and can be calculated using: DfMIN = fCLKIN 222 (2) When fCLK IN = 25MHz, DfMIN = 5.96Hz (±2.98Hz). Lower output frequencies are obtained by using a lower clock frequency. The maximum frequency output can be easily calculated with the following equation: fOUT( MAX) = fCLKIN 26 (3) When fCLK IN = 25MHz, fOUT(MAX) = 391kHz. Higher frequencies, up to 500kHz, are obtained by using an external clock, where 25MHz < fCLK IN < 32MHz. Due to the phase quantization nature of the frequency generator, spurious tones can be present in the output in the range of –50dB relative to fundamental. The energy from these tones is included in the signal to noise + distortion specification (SND) given in the electrical table. The frequency of these tones can be very close to the fundamental, and it is not practical to filter them out. SINEWAVE GENERATOR The sinewave generator is composed of a sine lookup table, an 8-bit DAC, an output smoothing filter, and an amplifier. The sine lookup table is addressed by the phase accumulator. The DAC is driven by the output of the table and generates a staircase representation of a sine wave. The ML2037 has a 2-bit (G1, G0) digital gain control. With the gain input equal to logic 00, the sine wave amplitude is equal to 0.5VP-P. Incrementing the gain control input increases the output amplitude in 0.5V steps to a maximum of 2.0VP-P. The output amplitude is accurate to within ±0.5dB over the frequency range. G1 G0 P–P OUTPUT AMPLITUDE 0 0 1 1 0 1 0 1 .5V 1.0V 1.5V 2.0V The analog section is designed to operate over a frequency range of DC to 500kHz and is capable of driving 1kW, 50pF loads at the maximum amplitude of 2.0VP-P. The sine wave output is typically centered about a 2.5V DC level, so for a 2VP-P sine wave, the output will swing from 1.5V to 3.5V. CRYSTAL OSCILLATOR The crystal oscillator generates an accurate reference clock for the programmable frequency generator. The internal clock can be generated with a crystal or external clock. If a crystal is used, it must be placed between CLK IN and DGND. An on-chip oscillator will then generate the internal clock. No other external components are required. The crystal should be a parallel resonant type with a frequency between 5MHz to 25.6MHz. It should be placed physically as close as possible to CLK IN and DGND, to minimize trace lengths. The crystal must have the following characteristics: • Parallel resonant type • Frequency: 5MHz to 25.6MHz • Maximum ESR: 120W @ 5 to 10MHz, 80W @10 to 15MHz, and 50W @ 15 to 25.6MHz • Drive level: 500µW • Typical load capacitance: 18 - 20pF • Maximum case capacitance: 7pF The frequency of oscillation will be a function of the crystal parameters and board capacitance. In general, 5 ML2037 16-BIT SHIFT REGISTER S DATA IN (16 BITS) • • • 16-BIT DATA LATCH S ENABLE (16 BITS) • • • ••• – – A16 A0 A20 A15 BINARY PHASE ACCUMULATOR 21-BIT ADDER B0–B20 SUM (21 BITS) • • • fREF 21-BIT LATCH Q0 LEAST SIGNIFICANT (12 BITS) ••• SIGN BIT PHASE SAMPLES (7 BITS) CLK IN CRYSTAL OSCILLATOR Q20 ••• INPUT TO QUADRANT COMPLEMENTOR QUADRANT BIT T= QUADRANT COMPLEMENTER ÷2 • • • (7 BITS) SIGN BIT READ-ONLY MEMORY (128 X 7) SIGN COMPLEMENTOR fREF SIGN BIT INPUT TO D/A CONVERTER SIGN BIT 8-BIT DIGITAL-TO-ANALOG CONVERTER G1 G0 GAIN CONTROL & LOW-PASS FILTER SINEWAVE OUTPUT Figure 1. Detailed Block Diagram of the ML2037. 6 PICTORIAL PRESENTATION OF DIGITAL DATA INPUT TO OUTPUT LATCH OUTPUT LATCH • • • (7BITS) INPUT TO ROM INPUT TO SIGN COMPLEMENTOR • • • (7 BITS) • • • (7 BITS) 1 fREF INPUT TO LOW-PASS FILTER (ANALOG SIGNAL) OUTPUT OF LOW-PASS FILTER (ANALOG SIGNAL) ML2037 FUNCTIONAL DESCRIPTION (Continued) microprocessor crystals meet the above requirements, but it is recommended to test the selected crystal in circuit to insure proper operation. Suitable crystals can be purchased from the following suppliers: ECS, Inc. FOX Electronics M-TRON Industries An external clock can drive CLK IN directly if desired. The frequency of this clock can be anything from 0 to 32MHz. However, at clock frequencies below 5MHz, the sine wave output begins to exhibit "staircasing". The ML2037 has a clock output that can be used to drive other external devices. The CLK OUT output is a buffered output from the oscillator which runs at one half the frequency of CLK IN. SERIAL DIGITAL INTERFACE The digital interface consists of a shift register and data latch. The serial 16-bit data word on S DATA IN is clocked into a 16-bit shift register on falling edges of the serial shift clock, S CLK. The LSB should be shifted in first and the MSB last as shown in Timing Diagram 1. The data that has been shifted into the shift register is loaded into a 16bit data latch on the falling edge of S ENABLE. To insure that true data is loaded into the data latch from the shift register, the S ENABLE falling edge should occur before the S CLK transitions high to low. S ENABLE should be high while shifting data into the shift register. Note that all data is entered and latched on edges, not levels, of S CLK and S ENABLE. Upon power up, the data in the latch is indeterminate. It is therefore recommended to initialize the frequency data as part of a power up routine. SYNCHRONIZATION When the SYNC pin is held high, the sine wave generator operates normally. Pulling this pin low causes the sine wave output to be interrupted and resets the phase back to zero. The sine wave output goes to the 2.5V DC level approximately 1µs after the SYNC input goes low. Switching the SYNC pin back to a high level starts the sine wave going again from zero phase. The delay from when the SYNC goes high to the start of the sine wave is about 500ns, as shown in Figure 2. If several generator chips are driven from the same clock, the SYNC input allows them to be phase synchronized to any value. Figure 3 gives an example of how a microcontroller can be used with two ML2037s to generate two sine waves that are 90º out of phase. SHUTDOWN The SHDN input provides a means to power down the analog section and the internal clock of the sine wave generator. When in the power down mode the part will draw only 10µA of input current and the output will go to zero approximately 500ns after the SHDN pin goes high. Switching the SHDN back to a low level allows the sine wave to resume at the last programmed frequency. The delay from when the SHDN goes low to when the sine wave resumes is about 200µs. The use of the power down mode allows power management for portable applications or for gating the internal oscillator for low noise applications. POWER SUPPLIES The analog circuitry in the device is powered from 5V (AVCC) and is referenced to AGND. The digital circuits in the device can also powered from the same 5V supply (DVCC to DGND). It is recommended that AGND and DGND be connected together close to the device and have a good connection back to the power source. It is recommended that the power supplies to the device should be bypassed by placing decoupling capacitors from AVCC to AGND and DVCC to DGND as physically close to the device as possible. SNYC 500ns 1 µs OUT Figure 2. SYNC Pin Timing. 7 ML2037 CLOCK OSCILLATOR CLK IN S DATA IN OUT S CLK S ENABLE SYNC ML2037 CLK IN S DATA IN µCONTROLLER OUT S CLK S ENABLE SYNC ML2037 Figure 3. Synchronizing Two ML2037 Sine Wave Generators. 8 ML2037 PHYSICAL DIMENSIONS inches (millimeters) Package: P16 16-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 16 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) PIN 1 ID 1 0.02 MIN (0.50 MIN) (4 PLACES) 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) SEATING PLANE 0.016 - 0.022 (0.40 - 0.56) 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S16W 16-Pin Wide SOIC 0.400 - 0.414 (10.16 - 10.52) 16 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.090 - 0.094 (2.28 - 2.39) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.009 - 0.013 (0.22 - 0.33) 9 ML2037 ORDERING INFORMATION © Micro Linear 1998. PART NUMBER TEMPERATURE RANGE PACKAGE ML2037CP (OBS) 0°C to 70°C 16-Pin PDIP (P16) ML2037CS (OBS) 0°C to 70°C 16-Pin Wide SOIC (S16W) ML2037IP (OBS) -40°C to 85°C 16-Pin PDIP (P16) ML2037IS (EOL) -40°C to 85°C 16-Pin Wide SOIC (S16W) is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 10 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com DS2037-01