April 1997 ML4813* Flyback Power Factor Controller GENERAL DESCRIPTION FEATURES The ML4813 is a PWM controller designed for use in a discontinuous "flyback" or "buck-boost" type power factor correction (PFC) system for low power, low cost applications. ■ Precision buffered 5V reference ■ Extra op-amp for output voltage instrumentation amplifier The circuit includes a precision reference, oscillator, error amplifier, over-voltage comparator, over-current comparator, and an extra op-amp as well as a high current output. In addition, start-up is simplified by an under-voltage lockout circuit. ■ Overcurrent comparator for switch protection ■ Soft start and under-voltage lockout for easy low surge off-line starting ■ 1A peak current Totem-pole output drive ■ Overvoltage comparator eliminates output "runaway" due to load removal ■ Large oscillator amplitude for better noise immunity In a typical application, the ML4813 functions as a voltage mode regulator. By maintaining a constant duty cycle, the current follows the input voltage, making the impedance of the entire circuit appear purely resistive. With the flyback circuit, power factors of 0.99 are easily achievable with a small output inductor and a minimum of external components. * This Part Is End Of Life As Of August 1, 2000 BLOCK DIAGRAM VFB 4 - 5V ERROR AMPLIFIER OA OUT 7V 6 OA+ 8 + + 60µA - SOFT START 7 OAVREF 2 14 ILIMIT 1 + 1V + 5.6V OVP COMPARATOR 13 OUT S Q R Q 12 - COMP 3 VCC 32V - OVP 5 UNDERVOLTAGE LOCKOUT CURRENT LIMIT COMPARATOR PWR GND 11 + CT PWM COMPARATOR 16 RT GND OSCILLATOR 9 15 SYNC 10 1 ML4813 PIN CONFIGURATION ML4813 16-Pin PDIP (P16) 16-Pin SOIC (S16W) ILIMIT 1 16 CT SOFT START 2 15 GND COMP 3 14 VREF VFB 4 13 VCC OVP 5 12 OUT OA OUT 6 11 PWR GND OA- 7 10 SYNC OA+ 8 9 RT TOP VIEW PIN DESCRIPTION PIN NAME FUNCTION 1 ILIMIT Current limit sense pin which is normally connected to the sense resistor. When ILIMIT exceeds 1V, the PWM cycle is terminated 2 3 SOFT START COMP Connection for the soft start capacitor Output of error amplifier and input to the PWM comparator 4 VFB Control loop feedback voltage 5 OVP Overvoltage comparator input 6 OA OUT Output of the uncommitted op amp 7 2 OA- Inverting input of the uncommitted op amp 8 OA+ Non-inverting input of the uncommitted op amp PIN NAME FUNCTION 9 RT Connection for the oscillator timing resistor 10 SYNC Input for synchronizing the oscillator to an external source 11 PWR GND Return for the high current output transistors 12 OUT High current driver output 13 VCC Power supply input 14 VREF Buffered reference output 15 GND Analog signal ground 16 CT Connection for the oscillator timing capacitor ML4813 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Current ....................................................... 40mA OUT Current ............................................................. ±1A OUT Energy (capacitive load, per cycle) .................... 5µJ COMP Sink Current ............................................... 10mA CT Charging Current ................................................. 5mA Analog Input Voltage (pins 1, 3-8) .... GND - 0.3V to 5.5V Junction Temperature .............................................. 150ºC Storage Temperature Range ..................... –65ºC to 150ºC Lead Temperature (Soldering, 10 sec) ..................... 260ºC Thermal Resistance (qJA) PDIP ................................................................ 88ºC/W SOIC .............................................................. 105ºC/W OPERATING CONDITIONS Temperature Range ML4813CX ................................................ 0ºC to 70ºC ML4813IX ............................................... -40ºC to 85ºC ELECTRICAL CHARACTERISTICS Unless otherwise specified, RT = 14kW, CT = 1nF, TA = Operating Temperature Range (Notes 1, 2) PARAMETER CONDITIONS MIN TYP MAX UNITS 97 104 kHz OSCILLATOR Initial Accuracy Tj = 25ºC 90 Voltage Stability 12V < VCC < 18V 0.3 Temperature Stability Total Variation Line, temp % 2 88 108 Ramp Valley % kHz 1.0 Ramp Peak 4.3 V V RT Voltage 4.8 5.0 5.2 V Discharge Current Tj = 25ºC, V(CT) = 2V 7.5 8.4 9.3 7.2 8.4 9.5 mA 0.8 1.4 2.0 V 350 800 µA 4.95 5.00 5.05 V 6 20 mV 3 20 mV V(CT) = 2V SYNC Threshold SYNC Bias Current mA REFERENCE Output Voltage (VREF) Line Regulation Tj = 25ºC, IREF = 1mA 12V < VCC < 25V Load Regulation 1mA < IREF < 20mA Temperature Stability Total Variation Line, load, temp Output Noise 10Hz to 10kHz 0.4 4.9 5.1 50 Long Term Stability Tj = 125ºC, 1000 hours Short Circuit Current VREF = GND -30 % V µV 5 25 mV -85 -180 mA 3 ML4813 ELECTRICAL CHARACTERISTICS (cont.) PARAMETER CONDITIONS MIN TYP MAX UNITS ERROR AMPLIFIER Input Offset Voltage -15 Input Bias Current -0.1 15 -1.0 mV µA Open Loop Gain 1V < COMP < 5V 60 75 dB PSRR 60 70 dB Output Sink Current COMP = 1.1V, VFB = 6.2V 2 12 mA Output Source Current COMP = 5V, VFB = 4.8V -0.5 -1.0 mA Output High Voltage ICOMP = -0.5mA, VFB = 4.8V 5.3 6.4 V Output Low Voltage ICOMP = 2mA, VFB = 6.2V 12V < VCC < 25V 0.5 Unity Gain Bandwidth 1.0 1.0 V MHz UNCOMMITTED OP AMP Input Offset Voltage -10 Input Bias Current -0.1 Input Offset Current -350 Open Loop Gain PSRR Output High Voltage ICOMP = -10mA Output Low Voltage RL = 10kW 10 mV -2.0 µA 350 nA 90 dB 80 125 dB 6.5 8 V 200 500 mV 1.0 1.2 V -2 -15 µA ILIMIT COMPARATOR Input Trip Point 0.8 Input Bias Current Propogation Delay Time 150 ns OVP COMPARATOR Input Trip Point 5.4 5.55 Hysteresis 100 Input Bias Current -0.3 5.7 V mV 3 181A 5.5 V -10 µA PWM COMPARATOR Input Common Mode Range -0.2 Input Bias Current -2 Propogation Delay Time 150 ns SOFT START Soft Start Current 4 VSOFT START = 1V 40 65 90 µA ML4813 ELECTRICAL CHARACTERISTICS (cont.) PARAMETER CONDITIONS MIN TYP MAX UNITS 0.1 0.4 2.2 V OUTPUT Output Low Voltage IOUT = 10mA IOUT = 200mA 1.2 VCC = 8V, IOUT = 5mA Output High Voltage IOUT = -20mA IOUT = -200mA Rise/Fall Time 0.1 13 12 CL = 1000pF 0.8 V V 13.6 V 13.4 V 50 ns UNDERVOLTAGE LOCKOUT Start-up Threshold 15 16.3 17.5 V Shutdown Threshold 9 10.1 11.2 V VREF Good Threshold 4.4 V SUPPLY Start-up Current VCC = 14V 0.9 Operating Current Shunt Regulator Voltage ICC = 30mA 25 1.5 mA 20 30 mA 30 34 V Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: VCC is raised above the UVLO start-up threshold, then returned to 15V. 5 ML4813 FUNCTIONAL DESCRIPTION OSCILLATOR 90% 10 t OSC = t RAMP + t DEADTIME 8 85% 1nF 10nF 5 80% RT (kΩ) The oscillator period can be described by: 2nF 3 70% 20nF (1) 2 MAXIMUM DUTY CYCLE (%) The ML4813 oscillator charges the external capacitor (CT) with a current (ISET) equal to 5/RSET. When the capacitor voltage reaches the upper threshold, the comparator changes state and the capacitor discharges to the lower threshold through Q1. While the capacitor is discharging, Q2 provides a high pulse. 5nF where: t RAMP = CT ISET and: t DEADTIME = 1 10 (2) 100 1000 OSCILLATOR FREQUENCY (kHz) Figure 1. Oscillator Timing Resistance vs. Frequency CT 8.4mA - ISET (3) A graph showing the relationship between RT, CT, the oscillator frequency, and maximum duty cycle is given in Figure 1. A pulse of a duration shorter than tDEADTIME from an external frequency source set to a higher frequency than fOSC can be applied to pin SYNC to synchronize the oscillator. RSYNC and CSYNC shorten longer pulses, as shown in Figure 2. EXTERNAL CLOCK CSYNC SYNC 10 ISET RSYNC RT 9 RT OUTPUT DRIVER STAGE 16 The ML4813 output driver is a 1A peak output high speed totem-pole circuit designed to quickly drive capacitive loads such as MOSFET gates. See Figure 3 for the output saturation characteristics for sourcing and sinking current. CT ISET CT + 8.4mA 5.6V - ERROR AMPLIFIER The ML4813 error amplifier is a high open loop gain, wide bandwidth amplifier. See Figure 4 for the gain and phase plot. CLOCK UN-COMMITTED OP-AMP The ML4813 contains an uncommitted op amp which is normally configured as a differencing amplifier to sense the output voltage. The output voltage in the flyback configuration is not ground referenced. The op amp in the ML4813 is a PNP input amplifier similar to the LM324 but with an open emitter class A output stage. TD RAMP PEAK V(CT) RAMP VALLEY Figure 2. Oscillator Block Diagram REFERENCE The reference output voltage versus output current characteristic is shown in Figure 5. UNDERVOLTAGE LOCKOUT On power-up, the ML4813 is in the UVLO condition; 6 output low and quiescent current low. The ML4813 becomes operational when VCC reaches 16V. When VCC drops below 10V, the UVLO condition is re-imposed. During UVLO, the VREF pin is off, making it usable as a "flag" for starting up a down-stream PWM converter. ML4813 15 SOURCE SATURATION LOAD TO GROUND SINK SATURATION LOAD TO VCC 3 2 1 GND 0 0 200 400 AVOL, Open Loop Gain (dB) 13 80 -30 60 -60 40 -90 PHASE 20 GAIN 0 -120 Excess Phase (degrees) OUTPUT SATURATION VOLTAGE (V) 14 0 100 VCC = 15V 80µs PULSED LOAD 120Hz RATE VCC -150 800 600 OUTPUT CURRENT (mA) -20 Figure 3. Output Saturation Voltage vs. Output Current 10 100 1k 10k 100k 1M -180 10M Figure 4. Error Frequency Amplifier Open Loop (Hz) Gain and Phase vs. Frequency 0 25 -4 20 ICC (mA) ∆VREF (mV) -8 -12 15 10 -16 5 -20 -24 0 20 40 60 80 100 120 IREF (mA) Figure 5. Reference Load Regulation vs. Output Current 0 0 10 20 30 40 VCC (V) Figure 6. Supply Current vs. Supply Voltage 7 ML4813 APPLICATIONS The ML4813 is used to implement a discontinuous mode flyback (buck-boost) power factor regulator as shown in Figure 7. This topology is particularly well suited for low power applications such as fluorescent ballasts and low power switching supplies. It is also a useful topology when there is a requirement for the output voltage to be lower than the peak input voltage, or where an isolated output is required. This is not possible with a boost topology, where the output voltage must always be higher than the maximum peak of the input voltage range. The typical input range for the flyback power factor regulator is from 90VAC to 260VAC. The regulator operates in the discontinuous current conduction mode. The inductor energy stored during the ON time of the power switch Q is completely delivered to the output capacitance during the OFF time. Under steady state conditions, the inductor current at the beginning of the ON time starts to ramp-up from 0 Amps to a value that is determined by the instantaneous value of the input full wave rectified voltage; the ON time as it is set by the error amplifier and the PWM comparator; and finally by the inductor itself. The expression for the inductor peak current is given by: 05 IL q = 05 VIN q t ON (4) L Where: IL(q) = instantaneous peak inductor current tON = Power MOSFET "ON" time VIN(q) = VP sin q = Instantaneous input voltage VP = Input peak voltage Figure 8 shows the relationship between the low frequency envelope and the high frequency inductor current. Note that for clarity the scale between the two RFI FILTER RL1 L1 C1 – ML4813 CONTROLLER + VS VOUT+ D1 RH2 Q1 RS RL2 Figure 7. Simplified Application Circuit waveforms has not been preserved. Normally for 60Hz input line and 100kHz switching frequency, each half of the sine wave contains approximately 833 high frequency triangular waveforms. The envelope of the peaks of the switch current, which in this case represents the current drawn from the input source, has a sinewave shape. This relationship is shown as: 05 IL q = IP sin q (5) By combining (4) and (5), the following useful relationship is obtained: t ON = L IP 2 VRMS INDUCTOR CURRENT SINUSOIDAL PEAK ENVELOPE SWITCH CURRENT AVERAGE CURRENT Figure 8. Switch and Line Currents in the Flyback PFC Circuit 8 VOUT- RH1 (6) ML4813 APPLICATIONS (Continued) Note that VIN(q) = VP x sin(q) and that VP = 1.414 x VRMS. The average value of the input triangular current is: 05 IAVG q = t ON IP sin q 2T (7) Where IAVG is the average value of the switch current (the value of the current at the input of the regulator after filtering), and T is the period of the switch cycle. Substitution of (6) into (7) yields: 05 IAVG q = L IP 2 sin q 2828 . T VRMS (8) Equation (8) clearly shows that the average value of the switch current is sinusoidal and in phase with the input voltage. The peak value of the average current is: L IP 2 sin q 2828 . T VRMS IAVG(PEAK) = (9) 2 PIN VRMS (10) Rearranging equations (9) and (10) to solve for PIN yields: PIN = L IP 2 f 4 (11) For optimum performance and the lowest inductor peak currents, the inductor current should be at the verge of continuity at the lowest operating voltage point and at full load. This can be satisfied if: IP VIN VOUT f L VIN + VOUT 1 6 (12) Finally, (11) and (12) can be combined to derive an upper bound for the inductor value that will guarantee that the regulator always stays in the discontinuous mode of operation. If the regulator were to operate in the continuous mode the average input current would not be sinusoidal. V V L ! 2 f P 1V IN IN OUT IN + VOUT "# 6 #$ INPUT BYPASS CAPACITANCE The triangular high frequency current is bypassed by an input capacitor (CIN). This should be a high quality film capacitor with low ESR value for minimum losses and heating. Polyester, polypropylene or x-type (for line side) are good candidates. Typical values, depending on the power level, can range anywhere from 330nF to 1.5µF. The next filtering stage of the RFI filter has an inductor as an input to isolate CIN from the other capacitors which may be present at the input circuit. Note that CIN can be on either side of the bridge rectifier. The preferred location for low crossover distortion is on the input side. The ripple voltage across this capacitor is: VC0P -P5 = Also: IAVG(PEAK) = Several core materials are candidates for the inductor, such as powder iron, gapped ferrites, moly permalloy, etc. There are no particular restrictions on the inductor except that the inductance is the correct value and the losses are acceptable. 2 (13) FLYBACK INDUCTOR CALCULATION Equation (13) gives the upper bound for the inductor value for any set of specified operating conditions. Normally, a few iterations may be required for finalizing the value to correct for second or third order effects. This means that a good initial value for the inductor is probably 10 to 20% lower than the value calculated by the right hand side expression in (13). D C f IN PIN 2PIN Lf CIN f VIN (14) Where VC(P-P) is the peak to peak worst case high frequency capacitor voltage, and D is the switch duty cycle. The RFI filter that follows CIN has to be able to attenuate VC(P-P) to the levels set by the relevant regulatory specifications. INPUT TRANSIENT OVERVOLTAGE PROTECTION Careful examination of the power circuits reveals that there is no large capacitance at the input of the regulator. The only capacitance present is that of the RFI filter capacitors. These capacitors have a combined value in the range of a few microfarads, and their ability to absorb and minimize any line induced transients is almost nonexistent. Transients can also occur under sudden load removal. If the line impedance is inductive, hazardous drain-source voltages may be generated leading to the destruction of the power MOSFET. To keep this from happening, a transient over-voltage protection device should be installed such that enough safety margin is allowed for the power MOSFET. A good rule of thumb is: BVDSS > VCLAMP + VOUT( OVP) (15) Where BVDSS is the drain-source breakdown voltage for the MOSFET, VCLAMP is the activation or clamping voltage of the over-voltage transient protector, and VOUT(OVP) is the maximum output voltage which is set by the OVP function of the controller. THE OUTPUT CIRCUIT The output circuit for this topology, although nonisolated, does not share the same ground with the power circuit. Therefore connecting the two grounds with the measuring leads of instruments should be avoided. 9 LINE INPUT 10 VR1 275V R25 3.83kΩ 1% R14 402kΩ 1% R13 402kΩ 1% F1 3A C12 4.7µF R14 402kΩ 1% R13 402kΩ 1% R18 200Ω R17 806kΩ 1% R24 100kΩ C13 220nF C1 680nF 630V R12 4.02kΩ 1% L2 500µH L1 500µH CT OUT OVP RT OA+ ML4813 SYNC OA- PWR GND VCC VFB OA OUT VREF GND COMP SOFT START ILIMIT C2 680nF 630V R11 1.8kΩ SYNC C11 100nF C10 6.8nF R23 2kΩ C7 1nF R22 2kΩ R4 1Ω Figure 9. 80W Flyback Power Factor Regulator Using the ML4813 R5 1Ω R10 100Ω R3 10Ω C9 1µF R6 1Ω R7 1Ω L3 R8 1Ω R9 1Ω Q1 MTH8N60 R2 4.3kΩ D5 1N4148 C3 10nF 1kV ENHANCEMENT CIRCUIT C8 1000µF D8 1N4148 D9 22V Q2 IRF821 R14 402kΩ 1% C14 100nF Q3 2N2222 START-UP CIRCUIT R1 220kΩ R13 402kΩ 1% C4 330µF 250V D7 MUR460 C5 10nF 1kV D6 MUR460 - VOUT + ML4813 ML4813 APPLICATIONS (Continued) The extra op amp provided in the ML4813 can be used to sense the output voltage for regulation and overvoltage conditions. This op amp is connected as a difference amplifier with its output referenced to PWR GND. Resistors RH1, RH2, RL1, RL2 are used to scale down the voltage. VOLTAGE The output voltage "rides" on the input voltage when the (+) output is measured with respect to PWR GND as shown in Figure 10. 200V VOUT+ VOUT VOUT- PWR GND Normally, RH1 = RH2 = RH and RL1 = RL2 = RL. The voltage designated as VS in Figure 7 is given by: VS = VOUT RL RH + RL (16) The output capacitance should be calculated such that it has the required output ripple at the worst case operating point. In addition, the ESR should be sufficiently low to prevent excessive dissipation due to RMS currents. The first criterion can be met by choosing the value of the output capacitor based on the following: C OUT PIN 2pfL DVR VOUT (17) Where: COUT = Total output capacitance PIN = Total input power DVR = Peak output capacitor ripple voltage fL = Line frequency times 2 (120 for 60Hz line) OUTPUT DIODE The output diode can be a "fast" or ultrafast' type depending on the operating frequency. Reverse recovery losses are low since under normal operating conditions, the regulator operates in discontinuous current mode. The diode should be rated to handle the maximum output current. The resulting power dissipation will be the forward drop of the diode times the output current. POWER SWITCH If a power MOSFET is used, it should be sized for the required efficiency. Lower RDS(ON) devices will yield lower losses, but if they are operated at high frequencies (100kHz), higher charge dumping losses will be experienced. The RMS current value through the power FET and the sensing resistor is: L IP 3 fL 4.24 VRMS r Ê= sin k 1 2 kp r Figure 10. Output Voltage with Respect to PWR GND Where: IRMS = Total RMS current through the power MOSFET fL = Line frequency times 2 (120 for 60Hz line) r = fSWITCH/fL Table 1 is provided to assist in calculating (18). When the power switch is a bipolar transistor (constant VCE drop), then the power dissipation produced can be calculated by: PD = The second criterion for the selection of the output capacitor can be satisfied by choosing a component with adequately low ESR value that can safely bypass the RMS currents. IRMS = TIME (15) 0.9 PIN VCE VRMS (19) Where: PD = Power dissipation in the transistor VRMS = RMS value of the minimum input voltage VCE = Forward drop of the power transistor r fSWITCH (kHz) r 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 167 250 333 417 500 583 667 750 833 917 1000 1083 1167 1250 1333 1417 1500 1583 1667 Ê= sin 2 k 1 kp r 9.1 11.2 12.9 14.4 25.8 17.1 18.3 19.4 20.4 21.4 22.4 23.3 24.2 25.0 25.7 26.5 27.3 28.0 28.9 Table 1. Constants for Calculating IRMS (Equation 18) 11 ML4813 APPLICATIONS (Continued) OFF-LINE START-UP AND BIAS SUPPLY GENERATION A fast starting circuit is included in Figure 9. MOSFET Q2 quickly charges the ML4813 VCC capacitor (C8) when the supply is initially turned on. This allows the supply to come on less than 1 second after AC power is applied. A simpler start-up circuit may be used which replaces the active circuit with a 39kW, 2W resistor but starts more slowly (up to 15 seconds under low line conditions). Systems which do not require quick starting can reduce cost with the latter start-up method. R12 R14' OA+ VOUT+ VOUT- + OA OUT TO ERROR AMP AND OVP – R15' R17 OA- R25 R18 POWER FACTOR ENHANCEMENT Some combinations of line and load may exhibit distortion of the input current waveform. This distortion is usually caused by the inductor "ringing" with the CDS of the power MOSFET, resulting in a non-zero inductor current at the beginning of the next cycle. This ringing can be dampened by using R2 and D7 as shown in Figure 9. Applications which can get by with slightly worse power factor can eliminate these components. Figure 11. Ground Referencing the Op Amp Output OVP ML4813 ADJUSTING THE OUTPUT VOLTAGE RB The error amplifier creates an error voltage from the difference between the output voltage presented at OA OUT and the 5V internal reference. Since the output voltage is not ground referenced, the ML4813's internal op amp is connected as an instrumentation amplifier as shown in Figure 11. RA OA OUT Figure 12. Setting OVP at > 1.12 x VOUT The output voltage is set by resistors which determine the relationship between (VOUT+ - VOUT-) and the output of the op amp. For the following discussion, R15' = R15 + R16 and R14' = R13 + R14. The differencing amplifier depends on the following relationships: COMP C13 R14'= R15' VFB R12 = R25 + (R17 || R18) OVP Then: VOUT = 5V + R18 R15’ R14’ + 1 R17 + R18 R15’+R25 R12 RD VOUT @ 1000 R18 R17 + R18 R + R R A B B OA OUT Figure 13. Setting OVP at < 1.12 x VOUT (21) The overvoltage comparator has a threshold that is set for 1.12 x VOUT when OVP and OA OUT are connected directly. Figure 12 shows the connection for setting an OVP trip point higher than 1.12 x VOUT, where: VOVP @ 112 . VOUT R24 (20) Since R25 is a low value compared to R15', the second term reduces to approximately 1. The third term is set at approximately 200. Equation (20) can be reduced to: 12 ML4813 (22) Figure 15 shows OVP set for a voltage lower than 1.12 x VOUT where: VOVP @ 112 . VOUT RD + R24 RD (23) ML4813 APPLICATIONS (Continued) INDUCTOR INFORMATION L3 is the flyback inductor and also provides the operating power for the control circuitry. A gapped ferrite pot core was chosen for this application for it's modest high frequency losses with high ripple current operation. Some possible choices are: Manufadurer Part # Magnetics Inc. F43019 Phillips 3019 PL00-3F3 Phillips 3019 PA125-3C8 Total Gap NP 0.05" 0.05" 0.07" 32 32 38 The first 2 cores are sold ungapped and require the use of a .025. spacer to gap the center leg to yield a total gap length of 0.05". If an ungapped core is used, a "shorted turn" should be employed as shown in Figure 14 to prevent radiated EMI. The third core listed is sold with its center ieg pre-gapped (0.07" total) so that the outside of the core closes completely, providing shielding without a shorted turn. NS should be 3 turns. All windings are #24AWG wire. SHORTED TURN (COPPER FOIL) 0.25" SPACER WINDINGS Figure 14. EMI Shielding for Ungapped Cores Inductors L1 and L2 are constructed using a powdered iron. This is a suitable material for these inductors since the high frequency ripple currents (and resulting flux excursions) are much less severe than for L3. The core selected is a MicroMetals T68-26D with 80 turns or #24AWG wire. 13 ML4813 PHYSICAL DIMENSIONS inches (millimeters) Package: P16 16-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 16 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) PIN 1 ID 1 0.02 MIN (0.50 MIN) (4 PLACES) 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) SEATING PLANE 0.016 - 0.022 (0.40 - 0.56) 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S16W 16-Pin Wide SOIC 0.400 - 0.414 (10.16 - 10.52) 16 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.090 - 0.094 (2.28 - 2.39) 14 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.009 - 0.013 (0.22 - 0.33) ML4813 ORDERING INFORMATION © Micro Linear 1996 PART NUMBER TEMPERATURE RANGE PACKAGE ML4813CP (EOL) ML4813CS (Obsolete) 0°C to 70°C 0°C to 70°C 16-Pin PDIP (P16) 16-Pin SOIC (S16W) ML4813IP (Obsolete) ML4813IS (Obsolete) -40°C to 85°C -40°C to 85°C 16-Pin PDIP (P16) 16-Pin SOIC (S16W) is a registered trademark of Micro Linear Corporation. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565761; 5,592,128; 5,594,376. Japan: 2,598,946; 2,619,299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. DS4813-01 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 15