PRELIMINARY DATA SHEET
MICRONAS
Edition July 25, 2001
6251-433-1PD
MAS 3506D
WorldSpace
Broadcast Channel
Audio Decoder
MICRONAS
MAS 3506D
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
4
4
4
1.
1.1.
1.2.
Introduction
Features of the MAS 3506D
System Overview
7
7
7
7
8
8
8
8
8
9
9
9
9
9
9
10
10
11
12
2.
2.1.
2.2.
2.2.1.
2.2.1.1.
2.2.1.2.
2.2.2.
2.2.3.
2.2.4.
2.3.
2.4.
2.4.1.
2.4.2.
2.4.3.
2.4.4.
2.5.
2.5.1.
2.5.2.
2.5.3.
Functional Description of the MAS 3506D
Overview
Firmware (Internal Program ROM)
Broadcast Channel Synchronization
Broadcast Channel Timing
Buffer-Controlled Loop
Broadcast Channel Demultiplexing
MPEG Audio Decoding
Baseband Processing
Clock Management
Power Supply Concept
Internal Voltage Monitor
DC/DC Converter
Stand-by Functions
Start-up Sequence
Interfaces
Broadcast Channel (BC) Input Interface
Parallel Input Output Interface (PIO)
Audio Output Interface
13
13
13
13
13
14
15
3.
3.1.
3.1.1.
3.1.2.
3.1.3.
3.2.
3.3.
16
16
16
16
18
18
19
19
19
19
20
23
28
3.3.1.
3.3.2.
3.3.3.
3.3.4.
3.3.5.
3.3.6.
3.3.7.
3.3.8.
3.3.9.
3.3.10.
3.4.
3.5.
3.5.1.
Controlling
I2C-Access
Device Address
I2C Registers and Subaddresses
Conventions for the Command Description
I2C Control Register (Subaddress 6Ahex)
I2C-Data Register (Subaddresses 68hex and 69hex)
and the MAS 3506D DSP-Command Syntax
Data Formats
Run and Freeze (Codes 0hex to 1hex)
Select Service Component (Code 5hex)
Read Ancillary MPEG Data (Code 6hex)
Read SCH-Data (Code 8hex)
Write Register (Code 9hex)
Write Memory (Codes Ahex and Bhex)
Read Register (Code Dhex)
Read Memory (Codes Ehex and Fhex)
Default Read
Control Registers
Control and Status Memory
Volume Matrix
2
Micronas
PRELIMINARY DATA SHEET
MAS 3506D
Contents, continued
Page
Section
Title
30
30
31
33
33
33
33
33
33
34
34
35
35
35
36
37
37
37
39
40
41
42
43
43
44
46
4.
4.1.
4.2.
4.3.
4.3.1.
4.3.2.
4.3.3.
4.3.4.
4.3.5.
4.3.6.
4.3.7.
4.3.8.
4.3.9.
4.4.
4.5.
4.6.
4.6.1.
4.6.2.
4.6.3.
4.6.3.1.
4.6.3.2.
4.6.3.3.
4.6.3.4.
4.6.3.5.
4.6.4.
4.6.5.
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Descriptions
Power Supply Pins
DC/DC Converter Pins
Control Lines
Parallel Interface Control Lines
Parallel Interface Data Lines
Voltage Supervision And Other Functions
Serial Input Interface
Serial Output Interface
Miscellaneous
Pin Configuration
Internal Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Characteristics
I2C Characteristics
Timing of PIO-Signals
I2S Bus Characteristics – SDI
I2S Characteristics – SDO
Firmware Characteristics
DC/DC Converter Characteristics
Typical Performance Characteristics
52
5.
Data Sheet History
Micronas
3
MAS 3506D
WorldSpace Broadcast Channel Audio Decoder
1. Introduction
PRELIMINARY DATA SHEET
– Low power dissipation (30 mW at fs ≤ 12 kHz,
46 mW at fs ≤ 24 kHz, 86 mW at fs > 24 kHz at
2.7 V)
– Supply voltage range: 2.7 V to 3.6 V
The WorldSpace system is a satellite-based digital
radio service for direct-to-home transmission of digital
radio programs. The coverage areas of this service are
Africa, South America, and parts of Asia.
– Adjustable built-in DC/DC up-converter for one-cell
and two-cell battery operation (typically down to
Vbat = 0.9 V)
The MAS 3506D is the source decoder of Micronas’
StarMan chip set that is designed for the reception of
WorldSpace signals. The MAS 3506D extracts one
Service Component (SC) of an incoming digital WorldSpace Broadcast Channel (BC) and decodes
MPEG 1/2/2.5 Layer 31) encoded audio data contained in the selected Service Component. The Service Control Header (SCH) information from the
Broadcast Channel is accessible via the embedded
fast mode serial control interface. The MAS 3506D
provides digital audio data output in I2S and similar formats. An embedded digital buffer-controlled loop
recovers the sampling frequency of the audio signal
and generates a synchronized 24.576 MHz clock signal which is used as an oversampling clock for D/A
converters. A block diagram of the MAS 3506D is
shown in Figure 1–2 on page 5.
– Power-off function
1)
MPEG 2.5 is a compatible extension of MPEG 2
audio, defined in ISO/IEC 13818-3.2 that covers
additionally very low sampling frequencies down to
8 kHz.
1.1. Features of the MAS 3506D
– Single-chip WorldSpace Broadcast Channel bitstream demultiplexer
– Adjustable power supply supervision
1.2. System Overview
The Micronas StarMan chip set consists of the channel
decoder DRD 3515A and the MPEG Layer 3 audio
decoder MAS 3506D. All essential analog and digital
building blocks for WorldSpace reception are provided
by the chip set. Together with an L-band tuner and an
appropriate microcontroller this set creates a complete
StarMan radio receiver (Figure 1–1)
Aux1/2
AM/FM
(analog)
Receiver,
Tape Player
MAS 3506D
I2S
BC
SC-out
WorldSpace
Tuner
IF input
DRD 3515A
analog out
I2C
– ISO MPEG 1/2/2.5 Layer 3 decoder
– ISO MPEG compliance tests passed
– Data processing by a high-performance RISC DSP
core (MASC)
System
Controller
– Download feature provides additional functionality
– Self-synchronized operation
– Output audio data delivered (in various formats) via
an I2S bus (SDO)
– Digital volume control and stereo channel mixer
– Automatic soft-mute function
– WorldSpace SCH-data output via I2C interface
– MPEG ancillary data provided via I2C interface
– Status information accessible via PIO pins or I2C
– “CRC Error”, “MPEG Frame Synchronization” and
“BC-Frame-Synchronization” indicators
– Power management for reduced power consumption at lower sampling frequencies
4
Fig. 1–1: Standard application of the StarMan chip set
Since the DRD 3515A also contains an audio amplifier
for headphone or small loudspeaker operation, only a
minimum of external components is necessary. The
additional inputs for analog signals (e.g. conventional
AM/FM receiver, tape etc.) make the amplifier accessible to these audio sources and thus considerably simplify the design of complete radio receivers.
The analog audio output of the WorldSpace signal can
be connected to an external stereo amplifier for higher
power or quality. Also a digital audio signal in standard
I2S format is provided for high-end applications that
may require an external D/A converter.
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
The complete WorldSpace Broadcast Channel (BC) is
available as a serial output signal from the DRD 3515A
and provides full access to all WorldSpace data. The
additional Service Component (SC) output of the
DRD 3515A may be useful in applications where a
data and an audio channel are transmitted simultaneously. In this case, the data component is directed
to the SC output. This function is independent from the
audio Service Component extraction in the
MAS 3506D.
14.725 MHz
to DRD 3515A
24.576 MHz
BC in
Service Control Header data are available via I2C controller interface from the MAS 3506D. (N.B. The Time
Slot Control Channel data are available only from the
DRD 3515A.)
RCLK
OCLK
Serial
Input
Interface
Clock
Synthesizer
I2C
Interface
Service Component
Extraction from Broadcast Channel
to µC
Parallel
Interface
MPEG 1/2/2.5 Layer 3
Audio Decoding
Audio
Data out
Serial
Output
Interface
Buffer-Controlled Loop
DC/DC
Converter
VDD
20-Bit RISC DSP
Fig. 1–2: Block diagram of the MAS 3506D
Micronas
5
MAS 3506D
Fig. 1–3: Complete WorldSpace receiver block diagram
6
BCDout
To optional BC processing
BCC
SCDout
To optional SC processing
SCC
SCW
BCDin
BC data input from ext. processing
BCenable
Satellite
Antenna
14.725 MHz
1
CLKI
Pol.Switch
RClk
Double Superhet
L-Band Tuner
2
QPSK Dem.
and Timing
Recovery
2nd IF
FEC
and TDM
Demux
3
24.576 MHz
Digital Audio
C
SC Extr.
BufferMPEG
controlled
Layer 3
Clock
Decoder
Synthesizer
4 OClk
D/A and
Analog Audio
DRD3515A
FM/AM
Antenna
Input
Buffer
PUP
Output Buffer
DC/DC
Converter
DCEN
≥ 3.0 V
MAS3506D
WSEN
B
Mono
SCI-Control Bus
Stereo
FM/AM Demod.
Left
Right
regulated Voltage (3 V)
Line
LCD
A
µC
Keys
WRDY
PUP
Micronas
PRELIMINARY DATA SHEET
Audio Out
MAS 3506D
PRELIMINARY DATA SHEET
2. Functional Description of the MAS 3506D
2.2. Firmware (Internal Program ROM)
2.1. Overview
The firmware of the MAS 3506D operates on the
Broadcast Channel signal generated by the
DRD 3515A. The MAS 3506D firmware processes the
input signal in four steps.
The hardware of the MAS 3506D consists of a highperformance RISC Digital Signal Processor (DSP) and
appropriate interfaces for WorldSpace Broadcast
Channel decoding (see Figure 2–1). The internal processor works with a memory word length of 20 bits and
an extended range of 32 bits in its accumulators. The
instruction set of the DSP is highly optimized for audio
data compression and decompression. Thus, only very
small areas of internal RAM and ROM are required. All
the data input and output actions are based on a ’noncycle-stealing’ background DMA that does not cause
any computational overhead (except for some initialization). The overall function of the MAS 3506D can be
altered by downloading up to 1 kWord of program
code into the internal RAM and executing this code
instead of the built-in firmware ROM code1). Dedicated
clock management hardware supports synchronization
on the transmitted data signal. A DC/DC step-up converter has been integrated for efficient battery-based
operation. Fig. 2–1 shows the building blocks of the
MAS 3506D.
1)
– Broadcast Channel synchronization
– Broadcast Channel demultiplexing
– MPEG audio decoding
– Frame synchronization and decoding error signals
are provided at output pins of the MAS 3506D.
2.2.1. Broadcast Channel Synchronization
The MAS 3506D analyzes the incoming BC bitstream
and detects the Service Control Header (SCH) preamble. If the preamble is found, the BC-SYNC signal
(available at a MAS 3506D output pin) indicates that
the MAS 3506D is in synchronized state. If synchronization is lost, the MAS 3506D automatically resets the
BC-SYNC signal and performs an audio soft-mute until
the next SC-header is detected.
Detailed information about downloading is provided
in combination with the MAS 3506D software development package or together with the MAS 3506D
software modules available from Micronas.
to DRD 3515A
OCLK
SCH
Synchronization
BC input
Digital Audio
output
SCH
buffer
Clock
Synthesizer
Volume
Matrix
Service
Component
Selection
MPEG 1/2/2.5 Layer 3
Decoder
Configuration
Registers
Layer 3
Status
Data Buffer
Ancillary
Data
to µC
(I2C)
Fig. 2–1: Functional overview of the MAS 3506D
Micronas
7
MAS 3506D
PRELIMINARY DATA SHEET
2.2.1.1. Broadcast Channel Timing
2.2.2. Broadcast Channel Demultiplexing
The incoming Broadcast Channel bitstream has a
framing with a period between Prime Rate Channel
Preambles (PRCP) of
The Service Control Header that directly follows the
SCH-preamble in the BC bitstream is made accessible
to the controller after it has been detected. Its availability is indicated by the BC-FRAME-SYNC signal. Information about the content of the Broadcast Channel is
given in the Service Control Header data. The controller may select the number of the Service Component
that is to be passed to the internal MPEG audio
decoder. By default, always Service Component “0” is
decoded by the MAS 3506D. An implemented
autoscan mode can be selected that skips non-audio
Service Components.
prcpt = 432 ms
During one frame the transmission of the BC is interrupted by a gap prcpgap of:
prcpgap = 2.5 ms
The data transmission is interrupted by a second gap
mfpgap with a duration of
mfpgap = 1.2 ms
2.2.3. MPEG Audio Decoding
that is synchronous with the Master Frame Preamble
(MFP) cycle with a period of:
The MPEG 1/2/2.5 Layer 3 decoder performs the
audio decoding. The steps for decoding are:
– Synchronization
mfpt = 138 ms
– Side information extraction
Both cycles mfpt and prcpt have a least common multiple at 9936 ms. These gaps are independent of the
number of Prime Rate Channels (PRC) n that create
the considered Broadcast Channel.
– Huffman decoding
– Synthesis filter bank
– Ancillary data extraction
The bit rates and sampling rates that are supported by
the MAS 3506D are listed in Table 2–1.
2.2.1.2. Buffer-Controlled Loop
For the recovery of the audio sample clock, a buffercontrolled loop is used that operates on the incoming
Broadcast Channel bit stream. The buffer control loop
characteristic suppresses the effects of these gaps on
the stability of the generated audio sample frequency
by more than 40 dB. Thus, no audible jitter is introduced to the derived reference clock for the D/A converter (see section 2.3. "Clock Management").
The step response of the buffer-controlled loop is plotted in Figure 2–2 with respect to different number of
PRCs. The settling time for the buffer-controlled loop is
about 10 s.
Table 2–1: Sampling frequencies and bit rates
Sampling Freq. in kHz
Bit rates in kBit/s
48, 32, 24, 16, 12, 8
128, 112, 96, 80, 64, 56,
48, 40, 32, 24, 16, 8
Frame synchronization and decoding error signals are
provided at output pins of the MAS 3506D.
2.2.4. Baseband Processing
0.12
A digital volume control matrix is applied to the digital
stereo audio data. This matrix may also perform additional balance control and a simple kind of stereo
basewidth enhancement. The four factors LL, LR, RL,
and, RR are adjustable via the controller with 20 bit
resolution (see Fig. 3–2 on page 28).
0.1
0.08
0.06
0.04
0.02
4.3
8.6
13
17
21
t/s
Fig. 2–2: buffer-controlled loop step response
8
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
2.3. Clock Management
The complete StarMan chip set is driven by a single
crystal with a nominal frequency of 14.725 MHz.
The DRD 3515A contains the crystal oscillator and an
appropriate clock buffer to generate the clock signal
RClk. This RClk signal is used as reference clock for
the MAS 3506D by an internal clock synthesizer that
generates an internal system clock of 24.576 MHz.
This synchronized clock frequency is passed back to
the DRD 3515A for use in its embedded audio D/A
converter.
2.4. Power Supply Concept
The MAS 3506D offers an embedded controlled DC/
DC converter for battery based power supply concepts. It works as an up-converter.
2.4.1. Internal Voltage Monitor
An internal voltage monitor compares the input voltage
at the VSENS pin with an internal reference value that
is adjustable via I2C bus. The PUP output pin should
be observed by the controller. It becomes inactive
when the voltage at the VSENS pin drops below the
programmed value of the reference voltage.
It is important that the WSEN must not be activated
before the PUP signal is generated. The PUP signal
thresholds are listed in Table 3–10 on page 20. The
internal voltage monitor will be activated with a high
level at Pin DCEN.
current variation and the ESR determines the high-frequency amplitude seen on the output voltage. The
Schottky diode should have a low voltage drop VD for
a high overall efficiency of the DC/DC converter. The
current rating of the diode should also be greater than
2.5 times the DC output current. The VSENS pin has
to be always connected to the output voltage.
2.4.3. Stand-by Functions
A high level at pin WSEN enables both, the DSP
including the I2C-block and the DC/DC-converter. If
the DSP-functions (audio decoding) are not needed,
the DC/DC-converter may remain active to supply
other parts of the radio. This mode is entered by setting DCEN to “high” and WSEN to “low”. No I2C control
is possible in this mode.
2.4.4. Start-up Sequence
The DC/DC converter starts from a minimum input
voltage of 0.9 V. There should be no output load during startup. WSEN must be “low”. The start-up script
should be as follows:
1. Start the DC/DC-converter with a high signal (VDD,
AVDD) at pin DCEN.
2. Wait until PUP goes “high”.
3. It is recommended to wait at least one millisecond to
guarantee that the output voltage has settled.
4. The controller may now enable the DSP with a
“high” signal at pin “WSEN”.
Please also refer to Figure 2–3.
2.4.2. DC/DC Converter
The DC/DC converter of the MAS 3506D is used to
generate a fixed power supply voltage even if the chip
set is powered by battery cells in portable applications.
The DC/DC converter is designed for the application of
1 or 2 batteries or NiCd cells as shown in Fig. 2–5
which shows the standard application circuit. The DC/
DC converter is switched on by activating the DCEN
pin. Its output power is sufficient for supplying the complete radio receiver.
µController
Note: Connecting DCEN directly to VDD leads to
unexpected states of the DCCF register.
WSEN > 2 V
A 22 µH inductor is required for the application. The
important specification item is the inductor saturation
current rating, which should be greater than 2.5 times
the DC load current. The DC resistance of the inductor
is important for efficiency. The primary criterion for
selecting the output filter capacitor is low equivalent
series resistance (ESR), as the product of the inductor
Micronas
DSP
operation
≥1
DC/DC
On
> 0.9 V
DCEN
button
Fig. 2–3: DC/DC operation
9
MAS 3506D
PRELIMINARY DATA SHEET
2.5. Interfaces
tSICLK
The MAS 3506D uses an I2C control interface, a serial
input interface for the Broadcast Channel, and a digital
audio output interface for the decoded audio data (I2S
or similar). Additionally, a general-purpose parallel I/O
interface (PIO) may be used for monitoring and modeselection tasks. The PIO lines are controlled by the
internal firmware.
Vh
VlI
BCC→(SIC)
Vh
7 6 5 4 3 2 1 0
VI
2.5.1. Broadcast Channel (BC) Input Interface
BCD→(SID)
The BC input interface consists of the three pins SIC,
SII, and SID. For WorldSpace operation the SII pin is
always to be connected to VSS. The Broadcast Channel input signal format is shown in Figure 2–4. The
data values are latched with the falling edge of the SIC
signal. The input interface is asynchronous and
accepts data streams generated by the DRD 3515A
BC output.
tbw
Fig. 2–4: Schematic timing of the SDI (BC) input
The BC input can be switched to an alternate port.
This function is controlled by input pin PI18. For more
details please see Section 3.1.3. on page 13
L
CLKI
VDD
optional
filter
AVDD
22 µH
DCSO
Start-up
oscillator
DCSG
+
−
DC/DC
converter
Start-up
oscillator
64...94
x2
DCEN
32...47
voltage
monitor
+32
DCCF
8ehex
9 10
0...15
Power-On
Push Button
PUP
COUT
330 µF
Low ESR
+
CIN
330 µF
VIN ≥ 0.9 V
−
10 kΩ
WSEN
VSENSE
16
VSS
AVSS
10 nF
47 kΩ
47 kΩ
µController
Fig. 2–5: DC/DC converter connections
10
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
2.5.2. Parallel Input Output Interface (PIO)
The parallel interface of the MAS 3506D consists of
the lines PI0..PI4, PI8, PI12..PI19:
Table 2–2: PIO input and output pin assignment
during MPEG decoding
PIO
Pin
Name
Comment
PI19
BC-FRAME-TOGGLE
(O)
0
1
Output level toggled each BCFRAME
PI18
BCINENABLE
(I)
0
1
PI13
BC-FRAME-SYNC
(O)
0
1
P12
BC-SYNC
(O)
0
1
PI8
MPEG-CRC-ERROR
(O)
0
1
PI4
MPEG-FRAME-SYNC
(O)
0
1
PI3
(I)
start of new frame
unsynched
synched to BC
no error
CRC-error or sync
lost
sync to a new
MPEG frame
AUD-SW
May be used to
monitor a signal
indicating switching between
Headphone and
Loudspeaker
mode.
Reserved
The PI-pins may
be monitored by
reading the PIO
register (see
Table 3–10)
(I)
PI2,
PI1,
PI0
enables SI* inputs
enables SI inputs
These signals are used to indicate the status of the
Broadcast Channel and the MPEG Layer 3 decoder.
The PIO pin status is also accessible via I2C interface
(see Table 3–10).
Micronas
11
MAS 3506D
PRELIMINARY DATA SHEET
2.5.3. Audio Output Interface
The audio output interface of the MAS 3506D is a
standard serial audio interface. The interface is configurable by software to work in 16-bit/sample and 32-bit/
sample mode. The default setup is a 16-bit mode
which is also the default setting for the DRD 3515A.
The 32-bit/sample mode is provided for high-resolution
D/A converters that expect more than 16-bit/sample
input data. The embedded D/A-converter of the
DRD 3515A is also capable of decoding the 32-bit/
sample format and provides a slightly better S/N performance in this mode1). The audio output interface
timing is shown in Figure 2–6 and Figure 2–7.
1)
If the 32-bit mode is selected and the D/A converter
of the DRD 3515A is still connected, it also has to
be switched to 32-bit I2S mode.
DAD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
left 16-bit audio sample
DAI
right 16-bit audio sample
timing detail
DAI
DAD
Vh
Vl
Vh
15
0
Vl
Fig. 2–6: Schematic timing of the digital audio output interface in 16-bit/sample mode
31
0 31
left 32-bit audio sample
DAI
Vh
0
right 32-bit audio sample
timing detail
Vl
DAD
Vh
Vl
1
0
31
Fig. 2–7: Schematic timing of the digital audio output interface in 32-bit/sample mode
12
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
3. Controlling
3.1.3. Conventions for the Command Description
3.1. I2C-Access
The description of the various controller commands
uses the following formalism:
Communication between the MAS 3506D and the
external controller is done via an I2C slave interface.
3.1.1. Device Address
The device addresses are 3ahex for writing (DW) and
3bhex for reading (DR), respectively. I2C clock synchronization is used to slow down the bus if required.
Table 3–1: I2C device address bits
A6
A5
A4
A3
A2
A1
A0
write/
read
0
0
1
1
1
0
1
0/1
3.1.2. I2C Registers and Subaddresses
The interface uses one level of subaddresses. The
MAS 3506D interface has 3 subaddresses allocated
for the corresponding I2C-registers.
Table 3–2: I2C subaddresses
SubI2Caddress Register
Function
68hex
data_write
Controller writes to
MAS 3506D data register
69hex
data_read
Controller reads from
MAS 3506D data register
6ahex
control
Controller writes to
MAS 3506D control register
The address 6ahex is used for basic control, i.e. reset
and task select. The other addresses are used for data
transfer from/to the MAS 3506D.
The I2C-control and data registers of the MAS 3506D
are 16 bits wide, the MSB is denoted as bit [15]. Transmissions via I2C-bus have to take place in 16-bit words
(two byte transfers, MSB sent first); thus for each register access two 8-bit data words must be sent/
received via I2C-bus.
– Abbreviations used in the following descriptions:
a address
d data value
n count value
o offset value
r register number
x don’t care
– Memory addresses like D1:89f are always in hexadecimal notation.
– A data value is split into 4-bit nibbles which are
numbered beginning with 0 for the least significant
nibble.
– Data values in nibbles are always shown in hexadecimal notation.
– A hexadecimal 20-bit number d is written, e.g. as
d = 17c63hex, its five nibbles are
d0 = 3hex, d1 = 6hex, d2 = chex, d3 = 7hex, and d4 =
1hex.
– Variables used in the following descriptions:
DW
3ahex
I2C-device write
I2C-device read
DR
3bhex
data register write
data_write 68hex
data register read
data_read 69hex
control register write
control
6ahex
– Bus signals
S Start
P Stop
A ACK = Acknowledge
N NAK = Not acknowledge
W Wait = a wait time (≤ 4 ms) may occur
– Symbols in the telegram examples
<
Start condition
>
Stop
dd
data byte
xx
ignore
All telegram digits are hexadecimal, data originating
from the MAS 3506D are grayed.
Example:
<3a 68 dd dd>
write data to DSP
<3a 69 <3b dd dd > read data from DSP
Figure 3–1 shows I2C bus protocols for read and write
operations of the interface; the read operation requires
an extra start condition and repetition of the I2C-device
address with the read command (DR). Fields with signals/data originating from the MAS 3506D are marked
by a gray background. Note that in some cases the
data reading process must be concluded by a NAK
condition.
The MAS 3506D firmware scans the I2C interface periodically and checks for pending or new commands.
Micronas
13
MAS 3506D
PRELIMINARY DATA SHEET
3.2. I2C Control Register (Subaddress 6Ahex)
The commands are then executed by the DSP during
its normal operation without any loss or interruption of
the incoming data or outgoing audio data stream.
However, due to some time critical firmware parts, a
certain latency time for the response has to be
expected at the locations marked with a “W” (= wait).
The theoretical worst case response time does not
exceed 4 ms. However, the typical response time is
less than 0.5 ms.
S
DW
W
A
control
A
d3,d2
A
d1,d0
W
A
P
The I2C control register is a write-only register. Its
main purpose is the software reset of the MAS 3506D.
The software reset is done by writing a 16-bit word to
the MAS 3506D with bit 8 set. The 4 least significant
bits are reserved for task selection. The task selection
is only useful in combination with download software.
In the standard application these bits must always be
set to 0.
Table 3–3: Control register data bit assignment1)
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
x
x
x
x
x
x
x
R
0
0
0
0
T3 T2 T1 T0
1) x = don’t care, R = reset, T3...T0 = task selection
Example: I2C write access
S
DW (3ahex)
W
A
data_write (68hex)
A
high byte data
A
data_read (69hex)
A
S
A
low byte data
W
A
N
P
P
Example: I2C read access
S
DW (3ahex)
W
DR (3bhex)
high byte data
SDA
SCL
S
1
0
P
A
W
A
low byte data
W
W = Wait
A = Acknowledge (Ack)
N = Not Acknowledge (NAK)
S = Start
P = Stop
Fig. 3–1: I2C-bus protocol for the MAS 3506D. Signals originating from the MAS 3506D are grayed.
14
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
3.3. I2C-Data Register (Subaddresses 68hex and
69hex) and the MAS 3506D DSP-Command
Syntax
DSP-commands consist of a “Code” which is sent to to
I2C-data register together with additional parameters.
The I2C data register is used to communicate with the
internal firmware of the MAS 3506D. It is readable
(subaddress “data_read”) and writable (subaddress
“data_write”) and also has a length of 16 bits. The data
transfer is done with the most significant bit (m) first.
Table 3–4: Data register bit assignment
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
m
l
A special command language is used that allows the
controller to access the DSP-registers and RAM-cells
and thus monitor internal states, set the parameters for
the DSP-firmware, control the hardware, and even provide a download of alternative software modules. The
S
DW
W
A data_write A Code,... A
...,...
A
...
Table 3–5 gives an overview over the different commands which the DSP-core may receive. The “Code”
is always the first data nibble transmitted after the
“data_write” byte.
The control interface is also used for low-bit-rate data
transmission, i.e. MPEG-embedded ancillary data and
the WorldSpace Service Control Header. These data
are available in a specified memory area of the
MAS 3506D after successful decoding. The synchronization between controller and the MAS 3506D will be
done by observing the BC-FRAME-SYNC and MPEGFRAME-SYNC signals in register c8hex or at the corresponding pins.
Table 3–5: Basic controller command codes for the MAS 3506D
Code
(hex)
Command
Function
0
Run
Start execution of an internal program. Run with start address 0hex means
freeze the operating system
1
Run Config
Start execution of an internal program and switch config RAM to P-RAM
5
Select SC
Select the Service Component
6
Read Ancillary Data
Read MPEG ancillary data
8
Read SCH-Data
Read Service Control Header
9
Write Register
An internal register of the MAS 3506D can directly be written to by the controller
a, b
Write Memory
A block of the DSP memory can be written to by the controller. (This feature
may be used to download alternate programs.)
d
Read Register
The controller can read an internal register of the MAS 3506D
e, f
Read Memory
A block of the DSP memory can be read by the controller
Micronas
15
MAS 3506D
PRELIMINARY DATA SHEET
3.3.1. Data Formats
3.3.3. Select Service Component (Code 5hex)
The internal data word size is 20 bits. All RAMaddresses can be accessed in a 20-bit mode via I2Cbus. Because of the 16-bit width of the I2C-data register the full transfer of all 20 bits requires two 16-bit I2Cwords. Some commands only access the lower 16 bits
of a cell. For fast access of internal DSP-states the
processor core also has an address space of 256 data
registers.
The internal data format is a 20 bit two’s complement
denoted “r”. If in some cases a fixed point notation “v”
is necessary. The conversion between the two forms
of notation is done as follows:
S
A data_write A
a3,a2
A
a1,a0
5,0
A
0,0
W
A
0,0
A
0,d0
W
A
P
1) send command (Read D0)
W
DW
W
A data_write A
6,o2
A
o1,o0
W
A
W
A
W
N
P
2) get ancillary data values
3.3.2. Run and Freeze (Codes 0hex to 1hex)
W
A data_write A
Select the (zero-based) service component with the
number d = d0. The number of available service components is to be taken from the SCH information. A
maximum of 8 service components are allowed in one
Broadcast Channel. SC-selection is also possible by
writing to memory cell D1:7ef (see Table 3–11 on
page 23).
S
DW
W
3.3.4. Read Ancillary MPEG Data (Code 6hex)
r = v*524288.0+0.5; (−1.0 ≤ v < 1.0)
v = r/524288.0; (−524288 < r < 524287)
S
DW
S
A
DW
W
A data_read A
S
DR
d3,d2
P
W
A
A
d1,d0
....repeat for n data values....
The Run command causes the start of a program part
at address a = (a3,a2,a1,a0). Note that nibble a3 is
also the command code (see Table 3–5) and thus it is
restricted to certain values. This command is especially used to start alternate code or downloaded code
from a RAM-area that has been configured as program
RAM.
Example 1: Start program execution at address
345hex:
<3a 68 03 45>
Freeze is a special run command with start address 0.
It suspends all normal program execution. The operating system will enter an idle loop so that all registers
and memory cells can be watched. This state is useful
for operations like downloading code or contents of
memory cells because the internal program cannot
overwrite these values. This freezing will be required if
alternative software is downloaded into the internal
RAM of the MAS 3506D.
d3,d2
A
d1,d0
P
The availability of new ancillary data is indicated by the
MPEG-FRAME-SYNC signal in register c8hex or at the
corresponding pin. Ancillary data are available every
24 to 32 ms depending on the sample rate of the
MPEG-bitstream. The instruction parameters are
embedded in the 3 nibbles o2..o0. The 6 MSBs indicate the address offset counted in 16-bit words where
the read-out of the ancillary data shall start. The 6
LSBs indicate the number of 16-bit words that are to
be transmitted by MAS 3506D.
Table 3–6: Arrangement of o-bits
11
10
9
8
o2
address offset
7
o1
6
5
4
3
2
1
0
o0
number of 16-bit words
Freeze has the following I2C protocol:
<3a 68 00 00>
The entry point of the default software will be accessed
automatically after a reset, thus issuing a Run or
Freeze command is only necessary for starting downloaded software or special program modules which are
not part of the standard set.
16
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MAS 3506D
PRELIMINARY DATA SHEET
The data values that are returned are organized in the
following table:
Telegram example:
First get the content of ’Number of ancillary bits’:
Table 3–7: Content of ancillary data field
Offset
Content
0
Bit 17..32 of MPEG header1)
1
Bit 12..16 of MPEG header
2)
2
Number of ancillary data bits
3
Last 16 bits of ancillary data
...
≤28
<3a
68
60 81>
device write ( I2C-address)
data write
code 6hex, offset 2, count 1:
Get number of ancillary bits
<3a 69 <3b
dd dd >
initiate reading
and read number of bits
Calculate number of words to be read from the number
of bits received (e.g. 20 bits require two words).
<3a
68
60 c2>
device write (I2C-address)
data write
code 6hex, offset 3, count 2:
Read two words from offset 3.
<3a 69 <3b
dd dd
dd dd >
initiate reading
and read two words
First 16 bits of ancillary data
1) see address D1:7f6 in Table 3–11 on page 23
2) see address D1:7f5 in Table 3–11 on page 23
The ancillary data values are copied in the reverse
order into this data field where the last bit received is
place at bit 0 of the data word at offset 3. The number
of data words with content can be calculated as follows:
int [(NumberOfAncillaryBits-1)/16] + 1
Limitations:
– The maximum number of data words that can be
read out are 28.
– The upper limit for ancillary data bitrate is 9600 bps.
– The ancillary data are only valid for 6 ms after the
MPEG-FRAME-SYNC signal.
Memory example:
The MPEG bitstream contains 20 bits of ancillary data
with the content f0f08hex. Then the ancillary data field
content will be:
Table 3–8: Ancillary data example
Offset
Content
0
Bit 17..32 of MPEG header
1
Bit 12..16 of MPEG header
2
14hex (number of anc bits)
3
0f08hex (bit-order reversed)
4
xxxfhex
Micronas
17
MAS 3506D
PRELIMINARY DATA SHEET
3.3.5. Read SCH-Data (Code 8hex)
Common Parameters with Command-Code 8hex
1) send command (Read D0)
Often the four nibbles defining start address and
amount to be transmitted (8hex, o2, o1, o0) may have
the following values:
S
DW
W
A data_write A
8,o2
A
o1,o0
W
A
P
2) get SCH-values
S
DW
W
A data_read A
S
DR
d3,d2
W
A
– 80 04: Read 16 bytes (= 8 words, 6 LSBs = 4)
from the beginning (offset = 0, 6 MSBs = 0) of the
SCH (i.e. everything from the beginning up to ADF2)
A
d1,d0
W
A
W
N
....repeat for n data values....
d3,d2
A
d1,d0
– 81 01: Read 4 bytes (= 2 words, 6 LSBs = 1) starting at 16 bytes (= 8 words, 6 MSBs = 4) offset (i.e.
one Service Component Control Field SCCF)
P
The availability of Service Control Header data is indicated by the related status registers or the BCFRAME-SYNC. The instruction parameters are
embedded in the 3 nibbles o2..o0. The 6 MSBs indicate half of the address offset counted in 16-bit words
where the read out of the SCH data shall start. The 6
LSBs indicate half of the number of 16-bit words that
are to be transmitted by the MAS 3506D.
– 81 05: Read 20 bytes (= 10 words, 6 LSBs = 5)
starting at 16 bytes (= 8 words, 6 MSBs = 4) offset
(i.e. 5 Service Component Control Fields SCCF)
3.3.6. Write Register (Code 9hex)
S
DW
W
A data_write A
Example:
If 4 words starting with SCH-word 10 shall be read out
the command parameters o2..o0 have to be set to:
Table 3–9: SCH-command example
11
10
9
8
o2
0
7
6
5
4
o1
0
0
1
0
3
2
1
0
0
1
0
o0
1
0
0
0
5
2
5 means offset of
(10 16-bit-words)/2
2 means amount of
(4 16-bit-words)/2
9,r1
A
r0,d4
W
A
d3,d2
A
d1,d0
W
A
P
The
controller
writes
the
20-bit
value
(d = d4,d3,d2,d1,d0) into the MAS 3506D register
(r = r1,r0). A list of registers needed for control purposes is given in Table 3–10 on page 20.
Example: Writing the value 81234hex into the register
with the number aahex:
<3a 68 9a a8 12 34>
Thus the command sequence that is to be sent to the
MAS 3506D is:
<3a
68
81 42>
device write (MAS 3506D I2C-address)
data write
code 8hex, 4 words from offset word 10
The data read sequence is then initialized by
DW (MAS 3506D write address)
data read
DR (MAS 3506D read address)
<3a
69
<3b
Then the MAS 3506D will send the SCH-values
dd
dd
dd
dd
dd
dd
dd
dd >
SCH10.h, SCH10.l
SCH11.h, SCH11.l
SCH12.h, SCH12.l
SCH13.h, SCH13.l
where SCHx.h/l refers to the high/low part of the xth
word of the SCH.
18
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
3.3.7. Write Memory (Codes Ahex and Bhex)
3.3.9. Read Memory (Codes Ehex and Fhex)
The memory areas D0 and D1 can be written by using
the codes ahex and bhex, respectively.
The MAS 3506D has 2 memory areas called D0 and
D1 using the codes ehex and fhex for their read commands, respectively.
S
DW
x,x
W
A data_write A
A
x,d4
W
A
a,0
A
0,0
W
A
n3,n2
A
n1,n0
W
A
a3,a2
A
a1,a0
W
A
d3,d2
A
d1,d0
W
1) send command (Read D0)
S
DW
W
A data_write A
A
....repeat for n data values....
x,x
A
x,d4
W
A
d3,d2
A
d1,d0
W
A
P
e,0
A
0,0
W
A
n3,n2
A
n1,n0
W
A
a3,a2
A
a1,a0
W
A
W
A
W
N
P
2) get register value
S
With the Write D0/D1 Memory command n 20-bit
memory cells in D0 can be initialized with new data.
DW
W
x,x
A
A data_read A
x,d4
W
A
S
DR
d3,d2
A
W
A
d1,d0
....repeat for n data values....
x,x
A
x,d4
W
A
d3,d2
A
d1,d0
P
Example: Write 80234hex to D1:456 has the following
I2C protocol:
write D1 memory
1 word to write
start address
value = 80234hex
<3a 68 b0 00
00 01
04 56
00 08
02 34>
The Read D0/D1 Memory command gives the controller access to all 20 bits of the memory cells of the
MAS 3506D. The telegram for reading 3 words starting
at location D1:100 is
<3a 68 f0 00 00 03 01 00>
<3a 69 <3b xx xd dd dd
xx xd dd dd xx xd dd dd >
3.3.8. Read Register (Code Dhex)
1) send command
S
DW
W
A data_write A
d,r1
A
r0,0
W
A
P
3.3.10.Default Read
2) get register value
S
DW
x,x
W
A
A data_read A
x,d4
W
A
S
DR
d3,d2
A
W
S
A
d1,d0
W
N
P
The MAS 3506D has an address space of 256 DSPregisters. Some of the registers (r = r1,r0 in the figure
above) are direct control inputs for various hardware
blocks, others control the internal program flow. In
Table 3–10, the registers of interest are described in
detail. In contrast to memory cells, registers cannot be
accessed as a block but must always be addressed
individually.
DW
W
A data_read A
S
DR
W
A
d3,d2
A
d1,d0
W
N
P
The Default Read command immediately returns the
lower 16 bits of the main status cell (“Status”) of the
MAS 3506D and may be used to poll the processor
status. The meaning of the returned bits is given in the
description of control memory cell D1:7ee in Table 3–
11 on page 23.
Example:
Read the content of the register c8hex:
<3a 68 dc 80>
<3a 69 <3b xx xd dd dd >
Micronas
define register
and read
19
MAS 3506D
PRELIMINARY DATA SHEET
Note! Registers not given in the tables must not be
written.
3.4. Control Registers
The registers displayed in the following table can be
read and written via I2C commands described (see
Section 3.3.6. and Section 3.3.8.).
Table 3–10: Control Registers
Address
(hex)
R/W
Function
Default
(hex)
Name
8e
W
DC/DC-Converter Frequency and Voltage
08000
DCCF
2
The I C protocol is working only if the processor is active
(WSEN = 1). However, the setting for the DCCF register will
remain active if the WSEN line is deasserted.
DC/DC-Converter Frequency
The frequency is controlled with bits 13...10 and 8.
Setting
bit [13:10]
Frequency/kHz
bit [8] = 0
Frequency/kHz
bit [8] = 1
11
11
11
11
10
10
10
10
01
01
01
01
00
00
00
00
156
160
163
167
171
175
179
184
188
194
199
204
210
216
223
230
128
245
253
263
272
283
295
307
320
335
351
368
387
409
433
460
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
The divider for the CLKI input is determined by the content of the
DCCF register. This register allows 32 settings of the DC/DC converter clock frequency fdc:
f CKLI
f SW = -----------------------2 ⋅ (m + n)
n ∈ {0, 15} , m ∈ { 16, 32 }
(EQ 1)
In order to reduce interference noise in AM-reception, the oscillator
frequency may be adjusted in 16 steps in order to allow the system
controller to select a base frequency that does not interfere with an
other application. The following algorithm may be used to select an
appropriate value for DCCF:
20
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
Table 3–10: Control Registers, continued
Address
(hex)
R/W
Function
Default
(hex)
int selectfrequency(double fstation) {
double fq,fdiv;
double fqmax = 0;
int imax = 0;
for (int i=0;i<16;i++) {
fdiv = 14725000/(2*(32+i));
fq = fstation/fdiv;
fq = fabs(fq-floor(fq)-0.5)*fdiv;
if (fq > fqmax) imax = i;
}
return imax;
}
8e
continued
Name
DCCF
continued
Modifications to this algorithm are applicable. It may be useful to
finish this procedure if fqmax reaches a certain minimum value, or
a preprocessed table for all possible AM-carrier frequencies may
be stored in ROM for the controller.
DC/DC-Converter Voltage
The output voltage is selected with bits 16...14 and 9. There is a
threshold between the output voltage of the DC/DC converter and
the internal voltage monitor. The PUP signal becomes inactive
when the output drops below the monitor voltage.
Micronas
Setting
bit [16:14] and [9]
DC/DC-Converter
Output Voltage/V
Internal Monitor
Voltage/V
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
3.57
3.46
3.35
3.25
3.14
3.04
2.94
2.83
2.73
2.63
2.52
2.42
2.32
2.22
2.12
2.02
3.38
3.27
3.16
3.06
2.95
2.85
2.75
2.64
2.54
2.44
2.33
2.23
2.13
2.03
1.93
1.82
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
21
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PRELIMINARY DATA SHEET
Table 3–10: Control Registers, continued
Address
(hex)
R/W
Function
Default
(hex)
c8
R
PIO-Register
Name
PIO
The PIO-register is used to monitor the actual status of the PIOpins for both, PIO-output and PIO-input lines. Bit 0 of the PIO register corresponds to pin PI0, bit 1 to PI1 etc. Due to the latency of
the MAS 3506D only slow events (>1 ms) can be monitored.
Please also refer to Section 4.6.3.2.
bit [19]
BC-FRAME-TOGGLE
Output level toggles with each BC-frame,
tframe = 432 ms
bit [18]
BCENABLE
0
use SID*, SII*, SIC*
1
use SID, SII, SIC
bit [13]
BC-FRAME-SYNC
0
cleared after SCH-read operation
1
start of new frame
bit [12]
BC-SYNC
0
unsynchronized
1
synchronized to BC
bit [8]
Decoding-ERROR
0
no error
1
error or sync lost
bit [4]
MPEG-FRAME-SYNC
0
cleared after anciliary data were read
1
sync to a new MPEG-frame
bit [3]
AUD-SW
This bit may be used to monitor a signal
from the headphone jack that indicates
switching between headphone and
loudspeaker mode.
bit [2:0]
22
These three free input lines return the
state logic level of the respective PIOpins. They may be used as a port
expansion of the controller.
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
3.5. Control and Status Memory
Note! Memory cells not given in the tables must not be
written.
The memory cells given in the following sections may
be read (Section 3.3.9.) or written (Section 3.3.7.) in
order to observe or control the operation of the
MAS 3506D.
Table 3–11: Control and status memory cells
Address
(hex)
R/W
Function
Default
D1:7ee
R
Main Status Indicator of the BC-Decoder
Name
Status
The Status cell returns global status information about the WorldSpace decoder. Its value is also returned by the ‘Default Read’
command as described in Section 3.3.10.
bit [15:12] BRI
0
1...8
Bit Rate Index
Reserved
n*16 kbit/s
bit [11:8]
Zero-based number of available Service
Components
1 SC available
...
8 SCs available
NSC
0
...
7
bit [7:4]
reserved
bit [3]
MCRC
0
1
MPEG CRC Error
no CRC-error in the last BC-frame
CRC-error occured in the last BC-frame
bit [2]
MFS
0
1
MPEG frame sync indication
no MPEG synchronisation
MPEG synchronisation
bit [1]
BCS
0
1
Broadcast Channel frame sync indication
no BC synchronisation
BC synchronisation
While the signals MPEG-FRAME-SYNC and BC-FRAME-SYNC in
the PIO-register c8hex rise with the beginning of each frame, the
signals MFS and BFS are stable as long as a valid bitstream is
received.
bit [0]
Micronas
S
0
1
Synchronized state
not in synchronized state (e.g. no bitstream)
MAS 3506D is synchronized and decoding
23
MAS 3506D
PRELIMINARY DATA SHEET
Table 3–11: Control and status memory cells, continued
Address
(hex)
R/W
Function
Default
D1:7ef
R/W
Service Component Selection (0..7) and Decoding Control
bit [15]
OutputMute
0
normal operation
1
mute output
bit [14]
AutoScan Autoscan function
0
disable autoscan function
1
enable autoscan function,
skip non-audio SCs
bit [13]
BCChange Broadcast Channel Change
0
cleared on SCH-rescynchronization
1
clears all previous SCH-information
Name
NumSC
Setting this bit clears all previous SCH-information and thus prepares the MAS 3506D for a BC-change. This ensured the availability of the correct SCH-data for the new BC.
bit [12]
MPEGResync
0
allows resynchronization only after
SCH-detection
1
MPEG-resynchronization enabled
bit [11:3]
bit [2:0]
reserved, set to 0
SC
0
...
7
D1:7f0
R/W
Zero-based number of audio Service
Component to be decoded
decode SC 1
decode SC 8
Counter for Broadcast Channel Frames
bit [15:0]
BCCount
BCFrameCnt
Counter for the decoded Broadcast
Channel frames
The BCFrameCnt ist incremented by one for each successfully
decoded BC-frame (432 ms) since reset. This address is writable,
thus the controller may reset/preset the content at any time to an
arbitrary value.
D1:7f1
R/W
Counter for MPEG Frames
bit [15:0]
MPEGFrameCnt
Counter for the decoded MPEG-frames
MPEGFrameCnt
The MPEGFrameCnt ist incremented by one for each successfully
decoded MPEG-frame (24...72 ms) since reset. This address is
writable for a reset/preset.
24
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
Table 3–11: Control and status memory cells, continued
Address
(hex)
R/W
Function
D1:7f3
R
System Error Indication
bit [10:0]
Default
Name
ErrorCode
ErrorCode Last error of WorldSpace decoding
1xxhex
Buffer problem, causes a firmware reset:
100hex
101hex
ErrorInputTimeOut: Input time-out
ErrorServicePreambleWrong: Service
preamble wrong
ErrorBufferOverflow: Input buffer overflow
ErrorBufferUnderrun: Buffer underflow
ErrorOutputTimeout: Output time-out
ErrorBitrateIntexChanged: Bitrate index
has changed
ErrorNoLayer3SyncNextFram: No synchronization found in input bitstream
102hex
103hex
104hex
105hex
106hex
2xxhex
BC-error, causes a BC-resynchronization:
100hex
ErrorSCToDecodeOutOfRange: SC to
decode is not available
ErrorSCTypeWrong: SC has no audio
ErrorStartBCSync: The controller has
indicated a BC-change (signal BCChange)
101hex
1ffhex
3xxhex
MPEG-error, causes an MPEGresynchronization:
300hex
ErrorSCToDecodeUserChange: A new SC
was selected
Error:
Error:
Error: Sampling rate changed
301hex
302hex
303hex
If an error occurs during decoding of the Broadcast Channel bitstream a number describing the error will be copied into this memory cell. The content always keeps a value corresponding to the
last detected error.
D1:7f4
R/W
Counter for All Decoding Errors
bit [15:0]
ErrorCnt
ErrorCnt
Counter for all decoding errors
The ErrorCnt is incremented by one for each decoding error since
reset. This address is writable for a reset/preset. This counter is
valuable for long-time observations. For identification of the last
error see D1:7f3
Micronas
25
MAS 3506D
PRELIMINARY DATA SHEET
Table 3–11: Control and status memory cells, continued
Address
(hex)
R/W
Function
Default
D1:7f5
R
Bits 12..16 of MPEG-Header
Name
MPEGStatus1
The MPEGStatus1 memory cell provides a direct copy of bits
16...12 of the acual MPEG-header. This cell will be updated immediatley after the MPEG-header has beed read from the bitstream.
bit [12:8]
Copy of bits 16...12 of the MPEG-header
bit [12:11] MPEGID
00
01
10
11
Bits 13 and 12 of the MPEG-header
MPEG 2.5
reserved
MPEG 2
MPEG 1
bit [10:9]
Layer
00
01
10
11
Bits 11 and 10 of the MPEG-header
reserved
Layer 1*
Layer 2*
Layer 3
bit [8]
Protection
0
CRC-protected
1
no CRC
bit [7]
reserved
bit [6:2]
private bits
bit [1]
CRC Error
0
no error
1
a CRC-error has occured
bit [0]
0
1
26
Invalid Frame
normal operation
an invalid frame has occured
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
Table 3–11: Control and status memory cells, continued
Address
(hex)
R/W
Function
Default
D1:7f6
R
Bit 32...17 of MPEG-Header
Name
MPEGStatus2
The MPEGStatus2 memory cell provides a direct copy of bits
32...17 of the acual MPEG-header. This cell will be updated immediately after the MPEG-header has beed read from the bitstream.
MPEG 1
Layer 3
MPEG 2.5
Layer 3
free
8
16
24
32
40
48
56
64
80
96
112
128
144*
160*
reserved
free
8
16
24
32
40
48
56
64
80
96
112
128
144*
160*
reserved
bit[15:12]
Datarate in kbit/s
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
free
32
40
48
56
64
80
96
112
128
160*
192*
224*
256*
320*
reserved
bit[11:10]
Sampling frequency/kHz
00
01
10
11
44.1*
48
32
reserved
22.05*
24
16
reserved
bit[9]
padding bit
bit[8]
private bit
bit[7:6]
bit[5:4]
Micronas
MPEG 2
Layer 3
Mode
00
01
10
11
11.025*
12
8
reserved
stereo
joint stereo
dual channel
reserved
Joint stereo: Mode extension
intensity stereo
00
off
01
on
10
off
11
on
bit[3]
Copyright
0
not protected
1
protected
bit[2]
Original/Copy
0
copy
1
original
ms_stereo
off
off
on
on
27
MAS 3506D
PRELIMINARY DATA SHEET
Table 3–11: Control and status memory cells, continued
Address
(hex)
R/W
Function
D1:7f6
continued
D1:7f7
bit[1:0]
R/W
Emphasis
00
01
10
11
bit [19:0]
D1:7f9
bit [19:0]
LL
00000
LR
00000
RL
80000
RR
left → right gain
LR
right → left gain
RL
Right ➔ Right Gain
R/W
80000
left → left gain (please refer to Sections
3.3.1. and 3.5.1.)
LL
Right ➔ Left Gain
R/W
bit [19:0]
D1:7fb
OutputConfig
0
generate 32-bit audio samples
16
generate 16-bit audio samples
Left ➔ Right Gain
R/W
bit [19:0]
D1:7fa
OutputConfig
Left ➔ Left Gain
R/W
Name
none
50/15 µs
reserved
CCITT J.17
Configures the Serial Audio Output Interface
bit [19:0]
D1:7f8
Default
right → right gain
RR
* Modes marked with an asterisk are not used in the WorldSpace system.
3.5.1. Volume Matrix
left audio
The digital baseband volume matrix is used for controlling the digital gain as shown in Fig. 3–2. Table 3–12
shows the proposed settings for the four volume matrix
coefficients for stereo, left, and right mono. The gain
factors are given in fixed point notation as desribed in
Section 3.3.1.
−1
LL
−1
LR
−1
RL
−1
RR
+
Table 3–12: Settings for the digital volume matrix
Memory location (hex)
D1:
7f8
D1:
7f9
D1:
7fa
D1:
7fb
Name
LL
LR
RL
RR
Stereo
(default)
−1.0
0
0
−1.0
Mono
left
−1.0
−1.0
0
0
Mono
right
0
0
−1.0
−1.0
28
right audio
+
Fig. 3–2: Digital volume matrix
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
Table 3–13: Volume matrix conversion (dB into hexadecimal)
Volume
(in dB)
Hexa
decimal
Volume
(in dB)
Hexa
decimal
Volume
(in dB)
Hexa
decimal
Volume
(in dB)
Hexa
decimal
Volume
(in dB)
Hexa
decimal
0
80000
−20
F3333
−40
FEB85
−60
FFDF4
−80
FFFCC
−1
8DEB8
−21
F4979
−41
FEDBF
−61
FFE2D
−81
FFFD1
−2
9A537
−22
F5D52
−42
FEFBB
−62
FFE60
−82
FFFD6
−3
A5621
−23
F6F03
−43
FF180
−63
FFE8D
−83
FFFDB
−4
AF3CD
−24
F7EC8
−44
FF314
−64
FFEB5
−84
FFFDF
−5
B8053
−25
F8CD5
−45
FF47C
−65
FFED9
−85
FFFE3
−6
BFD92
−26
F995B
−46
FF5BC
−66
FFEF9
−86
FFFE6
−7
C6D31
−27
FA485
−47
FF6DA
−67
FFF16
−87
FFFE9
−8
CD0AD
−28
FAE78
−48
FF7D9
−68
FFF2F
−88
FFFEB
−9
D2958
−29
FB756
−49
FF8BC
−69
FFF46
−89
FFFED
−10
D785E
−30
FBF3D
−50
FF986
−70
FFF5A
−90
FFFEF
−11
DBECC
−31
FC648
−51
FFA3A
−71
FFF6C
−91
FFFF1
−12
DFD91
−32
FCC8E
−52
FFADB
−72
FFF7C
−92
FFFF3
−13
E3583
−33
FD227
−53
FFB6A
−73
FFF8B
−93
FFFF4
−14
E675F
−34
FD723
−54
FFBEA
−74
FFF97
−94
FFFF6
−15
E93CF
−35
FDB95
−55
FFC5C
−75
FFFA3
−95
FFFF7
−16
EBB6A
−36
FDF8B
−56
FFCC1
−76
FFFAD
−96
FFFF8
−17
EDEB6
−37
FE312
−57
FFD1B
−77
FFFB6
−97
FFFF9
−18
EFE2C
−38
FE638
−58
FFD6C
−78
FFFBE
−98
FFFF9
−19
F1A36
−39
FE905
−59
FFDB4
−79
FFFC5
−99
FFFFA
Micronas
29
MAS 3506D
PRELIMINARY DATA SHEET
4. Specifications
4.1. Outline Dimensions
10 x 0.8 = 8 ± 0.1
0.17 ± 0.06
0.8
23
10 ± 0.1
0.34 ± 0.05
13.2 ± 0.2
12
44
0.8
22
34
10 x 0.8 = 8 ± 0.1
33
1
11
2.0 ± 0.1
13.2 ± 0.2
2.15 ± 0.2
10 ± 0.1
0.1
SPGS706000-5(P44)/1E
0.9 ± 0.2
Fig. 4–1:
44-Pin Plastic Metric Quad Flat Package
(PMQFP44)
Weight approximately 0.4g
Dimensions in mm
1.1 x 45 °
6
17
29
18
28
1.9 ±0.05
1.27
6
0.71 ± 0.05
17.52 ± 0.12
2
2
8.6
10 x 1.27 = 12.7 ± 0.1
39
1.6
16.5 ± 0.1
7
0.48 ± 0.06
40
15.7 ± 0.3
1
0.27 ± 0.03
6
10 x 1.27 = 12.7 ± 0.1
1.27
1.2 x 45°
4.05 ±0.1
17.52 ± 0.12
4.75 ±0.15
0.1
16.5 ± 0.1
SPGS704000-1(P44/K)/1E
Fig. 4–2:
44-Pin Plastic Leaded Chip Carrier Package
(PLCC44)
Weight approximately 2.5 g
Dimensions in mm
Note: The PLCC44-package has limited availability
Caution: Start pin and orientation of pin numbering is different for PLCC and PMQFP-housings.
30
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
4.2. Pin Connections and Short Descriptions
NC
X
not connected, leave vacant
obligatory, pin must be connected as
described in application informations
Pin No.
Pin Name
Type
LV
VDD
VSS
if not used, leave vacant
connect to positive supply
connect to ground
Connection
Short Description
PMQFP
44-pin
PLCC
44-pin
1
6
TE
I
VSS
Test enable
2
5
POR
I
VDD
Reset , active low
3
4
I2CC
IO
X
I2C clock line
4
3
I2CD
IO
X
I2C data line
5
2
VDD
Supply
X
Positive supply for digital parts
6
1
VSS
Supply
X
Gound supply for digital parts
7
44
DCEN
I
VSS
Start and enable DC/DC converter
8
43
EOD
O
LV
PIO end of DMA, active low
9
42
RTR
O
LV
PIO ready to read, active low
10
41
RTW
O
LV
PIO ready to write, active low
11
40
DCSG
Supply
VSS
DC converter transistor ground
12
39
DCSO
O
VSS
DC converter transistor open drain
13
38
VSENS
I
VDD
DC converter voltage sense
14
37
PR
I
VDD
PIO DMA request or Read/Write
15
36
PCS
I
VDD
PIO chip select , active low
16
35
PI19
O
LV
BC-Frame-Toggle
17
34
PI18
I
VSS
BCINENABLE
18
33
PI17
I
VSS
PIO data [17], reserved
19
32
SIC*/PI16
I
X
PIO data[16] (SIC*)
20
31
SII*/PI15
I
VSS
PIO data[15] (SII*)
21
30
SID*/PI14
I
X
PIO data [14] (SID*)
22
29
PI13
O
LV
BC-FRAME-SYNC
23
28
PI12
O
LV
BC-SYNC
24
27
SOD/PI11
O
LV
Serial output data
25
26
SOI/PI10
O
LV
Serial ouput frame identification
26
25
SOC/PI9
O
LV
Serial output clock
27
24
PI8
O
LV
Decoding-error
28
23
XVDD
Supply
X
Positive supply of output buffers
Micronas
(If not used)
31
MAS 3506D
Pin No.
PRELIMINARY DATA SHEET
Pin Name
Type
Connection
Short Description
PMQFP
44-pin
PLCC
44-pin
29
22
XVSS
Supply
X
Ground of output buffers
30
21
SID/PI7
I
X
Serial input data
31
20
SII/PI6
I
VSS
Serial input frame identification
32
19
SIC/PI5
I
X
Serial input clock
33
18
PI4
O
LV
MPEG-frame sync
34
17
PI3
I
VSS
AUD-SW, information from headphone jack
35
16
PI2
I
VSS
Reserved
36
15
PI1
I
VSS
Reserved
37
14
PI0
I
VSS
Reserved
38
13
CLKO
O
LV
Clock output (nominal 24.576 MHz)
39
12
PUP
O
LV
Power Up, i.e. status of voltage supervision
40
11
WSEN
I
X
Enable DSP and DC/DC converter
41
10
WRDY
O
LV
If WSEN=0: Valid clock input at CLKI
If WSEN=1: Clock synthesizer PLL
locked
42
9
AVDD
Supply
VDD
Supply for analog circuits
43
8
CLKI
I
X
Clock input
44
7
AVSS
Supply
VSS
Ground supply for analog circuits
32
(If not used)
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
4.3. Pin Descriptions
4.3.3. Control Lines
4.3.1. Power Supply Pins
Connection of all power supply pins is mandatory for
the function of the MAS 3506D.
VDD
VSS
I2CC
I2CD
SCL
SDA
IN/OUT
IN/OUT
Standard I2C control lines. Normally there are pull-up
resistors from each line to VDD.
SUPPLY
SUPPLY
4.3.4. Parallel Interface Control Lines
The VDD/VSS pair is internally connected with all digital modules of the MAS 3506D.
XVDD
XVSS
SUPPLY
SUPPLY
The XVDD/XVSS pins are the supply lines for the pin
output buffers.
AVDD
AVSS
PR
PCS
RTR
RTW
EOD
IN
IN
OUT
OUT
OUT
PIO handshake lines. Their use depends on the actual
firmware on the MAS 3506D. Usage of these lines in
the standard WorldSpace configuration is not planned.
SUPPLY
SUPPLY
4.3.5. Parallel Interface Data Lines
The AVDD/AVSS pair is internally connected with the
analog blocks of the MAS 3506D, i.e. clock synthesizer and supply voltage supervision circuits.
General purpose Parallel IO pins. The information of
the input and output signals may also be read from
Register c8hex (please refer to Table 3–10 in Section
Section 3.4. on page 20).
4.3.2. DC/DC Converter Pins
DCEN
DC/DC ENABLE
IN
The DCEN input signal starts and enables the DC/DC
converter operation.
DCSG
OUT
DCSO is an open drain output and should be connected with external circuitry (inductor/diode) to start
the DC/DC converter. When the DC/DC converter is
not used, it has to be connected to VSS.
VSENS
IN
The VSENS pin is the input for the DC/DC converter
feedback loop. It must be connected directly with the
Schottky diode and the capacitor as shown in Fig. 2–5
on page 10.
When the DC/DC converter is not used, it has to be
connected to VDD.
Micronas
BC-FRAME-TOGGLE
OUT
The BC-FRAME-TOGGLE output toggles its state after
each correctly decoded Broadcast Channel Frame
(432 ms). This pin can be used for monitor the proper
function of the system.
SUPPLY
The DC converter Signal Ground pin is used as a
basepoint for the internal switching transistor of the
DC/DC converter. It must always be connected to
ground.
DCSO
PI19
PI18
BCINENABLE
IN
PI18 is used as input pin to sense the status of the
BCINENABLE line at the WorldSpace connector. On
low input level the alternative BC-input lines SIC*, SII*
and SID* are activated and SIC, SII, SID are deactivated.
PI17
PI16
PI15
PI14
RESERVED
SIC*
SII*
SID*
IN/OUT
IN
IN
IN
The SIC*, SID*, and SII* may be configured as alternative serial input lines in order to support alternative
serial digital sources. SID* (PI14) is used as Broadcast
Channel data input from the Broadcast Channel I/O
interface.
33
MAS 3506D
PI13
BC-FRAME-SYNC
PRELIMINARY DATA SHEET
OUT
The BC-FRAME-SYNC is reset after POR and set to
‘1’ after each correctly decoded SCH. It will only be
cleared if the controller reads out SCH information
from the MAS 3506D.
PI12
BC-SYNC
OUT
4.3.6. Voltage Supervision And Other Functions
CLKI
CLKO
IN
OUT
CLKI and CLKO are the input and output clock lines to
be connected to the DRD 3515A. CLKI expects
14.725 MHz, CLKO delivers 24.576 MHz synchronous
to the audio data stream.
The BC-SYNC is set, if the MAS 3506D is in the state
of proper decoding of the Broadcast Channel bitstream.
PUP
PI8
The PUP output indicates that the power supply voltage exceeds its minimal level (software adjustable).
DECODING-ERROR
OUT
The Decoding-Error pin is activated, if during decoding
of the Broadcast Channel, the MPEG frame an error
occurs or if no input bitstream is applied.
PI4
MPEG-FRAME-SYNC
IN
The MPEG-FRAME-SYNC signal indicates that an
MPEG header has been decoded properly and the
internal MPEG decoder is in a synchronized state. The
MPEG-FRAME-SYNC signal is inactive after PowerOn Reset and will be activated when a valid MPEG
Layer 3 header has been recognized. The signal will
be cleared if the ancillary data information is read out
by the controller via I2C interface.
PI3
AUD-SW
IN
The AUD-SW input may sense the headphone jack
and deposit its information in Bit 3 of register c8hex
(please refer to Table 3–10 on page 20.) This way the
controller can get the information weather a loudspeaker or a headphone should be supplied and can
set the BAS_INVR bit in DRD 3515A’s register
GLB_CONFIG accordingly.
PI2
PI1
PI0
34
RESERVED
RESERVED
RESERVED
IN
IN
IN
WSEN
POWER UP
DSP ENABLE
OUT
IN
WSEN enables DSP and DC/DC-converter operation.
It must also be set to activate the control interface e.g.
to reprogram the DC/DC-converter.
WRDY
OUT
WRDY has two functionalities depending on the state
of the WSEN signal.
If WSEN = 0, it indicates that a valid clock has been
recognized at the CLKI clock input.
If WSEN = 1, the WRDY output will be set to ‘0’ until
the internal clock synthesizer has locked to the incoming audio data stream, and thus, the CLKO clock output signal is valid.
4.3.7. Serial Input Interface
SID
SII
SIC
IN
IN
IN
Data, Frame Indication and Clock line of the serial
input interface. The SII line should be connected with
VSS in the standard WorldSpace mode. The SID and
SIC lines are used for the Broadcast Channel input.
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
4.3.8. Serial Output Interface
4.3.9. Miscellaneous
SOD
SOI
SOC
OUT
OUT
OUT
Data, Frame Indication and Clock line of the serial
audio output interface (I2S). The SOC line can be
deactivated, if only the DRD 3515A D/A converter is
connected. The SOI indicates, whether the left or the
right audio sample is transmitted. In the default setting
a left audio sample always corresponds to SOI = low.
POR
IN
The Power-On Reset pin is used to reset the digital
parts of the MAS 3506D.
TE
IN
The TE pin is for production test only and must be connected with VSS in all applications.
4.4. Pin Configuration
XVDD
VSS
XVSS
PI8
SID
VDD
SOC
SII
SOI
SIC
DCEN
I2CD
EOD
I2CC
SOD
PI4
RTR
POR
PI12
RTW
TE
DCSG
33 32 31 30 29 28 27 26 25 24 23
6
5
4
3
2
1
44 43 42 41 40
PI3
34
22
PI13
AVSS
7
39
DCSO
PI2
35
21
SID
CLKI
8
38
VSENS
PI1
36
20
SII
AVDD
9
37
PR
PI0
37
19
SIC
WRDY
10
36
PCS
CLKO
38
18
PI17
WSEN
11
35
PI19
MAS 3506D
MAS 3506D
PUP
39
17
PI18
PUP
12
34
PI18
WSEN
40
16
PI19
CLKO
13
33
PI17
WRDY
41
15
PCS
PI0
14
32
SIC
AVDD
42
14
PR
PI1
15
31
SII
CLKI
43
13
VSENS
PI2
16
30
SID
AVSS
44
12
DCSO
PI3
17
29
PI13
1
2
3
4
5
6
7
8
9
10 11
TE
DCSG
RTW
POR
I2CC
RTR
I2CD
EOD
VDD
DCEN
VSS
Fig. 4–3: PMQFP44 package
Micronas
18 19 20 21 22 23 24 25 26 27 28
PI4
PI12
SIC
SOD
SII
SOI
SID
SOC
XVSS
PI8
XVDD
Fig. 4–4: PLCC44 package
35
MAS 3506D
PRELIMINARY DATA SHEET
4.5. Internal Pin Circuits
DCSO
TTLIN
DCSG
VSS
Fig. 4–5: Input pins PCS, PR
Fig. 4–11: Input/Output pins DCSO, DCSG
XVDD
P
Fig. 4–6: Input pin TE, DCEN
N
XVSS
Fig. 4–12: Output pins WRDY, RTW, EOD, RTR,
CLKO, PUP
Fig. 4–7: Input pins WSEN, POR
VSENS
Fig. 4–8: Input pin CLKI
VSS
XVDD
Fig. 4–13: Input pin VSENS
P
N
XVDD
P
XVSS
Fig. 4–9: Input/Output pins PI0...PI4, PI8, SOC, SOI,
SOD, PI12...PI19
N
XVSS
Fig. 4–14: Input/Output pins SIC, SII, SID
VDD
N
VSS
Fig. 4–10: Input/Output pins I2CC, I2CD
36
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
4.6. Electrical Characteristics
4.6.1. Absolute Maximum Ratings
Symbol
Parameter
TA
Pin Name
Min.
Max.
Unit
Ambient operating temperature
−40
85
°C
TS
Storage temperature
−40
125
°C
PMAX
Power dissipation
VDD, XVDD,
AVDD
600
mW
VSUP
Supply voltage
VDD, XVDD,
AVDD
5.5
V
VIdig
Input voltage, all digital inputs
−0.3
VSUP +0.3
V
IIdig
Input current, all digital inputs
−20
+20
mA
IOut
Current, all digital output
0.5
A
IOutDC
Current
DCSO
1.5
A
VII2C
Input voltage, I2C-Pins
I2CC,
I2CC
5.5
V
−0.3
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
4.6.2. Recommended Operating Conditions
Symbol
Parameter
TA
Ambient temperature range
VSUP
Supply voltage
Pin Name
Min.
Typ.
−40
VDD, XVDD,
AVDD
2.7
3.0
Max.
Unit
85
°C
3.6
V
Reference Frequency Generation
CLKF
Clock frequency
CLKI_V
Clock input voltage
0
CLKAmp
Clock amplitude
0.5
Micronas
CLKI
14.725
MHz
VSUP
V
Vpp
37
MAS 3506D
Symbol
PRELIMINARY DATA SHEET
Parameter
Pin Name
IIL27
Input low voltage
at VSUP = 2.7 V ... 3.6 V
IIH36
Input high voltage
at VSUP = 2.7 V ... 3.6 V
POR
I2CC,
I2CD,
DCEN,
WSEN
IIH33
Min.
Typ.
Max.
Unit
0.4
V
Levels
1.8
V
Input high voltage
at VSUP = 2.7 V ... 3.3 V
1.7
V
IIH30
Input high voltage
at VSUP = 2.7 V ... 3.0 V
1.6
V
IILD
Input low voltage
IIHD
Input high voltage
Trf
Rise/fall time of digital inputs
PI<i>,
SII,
SIC,
SID,
PR,
PCS, CLKI
Dcycle
Duty cycle of digital clock inputs
SIC, CLKI
PI<i>1),
SII,
SIC,
SID,
PR,
PCS,
TE,
0.4
VSUP−
0.5
40
V
V
50
10
ns
60
%
DC-DC converter external circuitry
C1
Blocking capacitor
(< 100 mΩ ESR)2)
VSENS, DCSG
330
µF
VF
Schottky diode forward voltage3)
DCSO,
VSENS
0.35
V
L
Inductance of ferrite ring core
coil4)
DCSO
22
µH
1)
2)
3)
4)
38
i = 0 to 4, 8 , 12 to 19
Sanyo Oscon 6SA330M
(distributed by Endrich Bauelemente, D-72202 Nagold-lselshausen)
ZETEX ZMCS1000
(distributed by ZETEX, D-81673 München), standard Schottky 1N5817
C8 R/4L, SDS0604 (distributed by Endrich Bauelemente, see above)
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
4.6.3. Characteristics
at T = TA, VSUP = 2.7 to 3.6 V, typ. values at TA = 27°C, VSUP = 3.5 V, CLKF = 14.725 MHz, duty cycle = 50%
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
32
mA
2.7 V, sampling
frequency ≥ 32kHz
17
mA
2.7 V, sampling
frequency ≤ 24 kHz
11
mA
2.7 V, sampling
frequency ≤ 12 kHz
V
Iload = 6mA
V
Iload = 6mA
Supply Voltage
ISUP
Current consumption
VDD, XVDD,
AVDD
Digital Outputs and Inputs
VDOL
Output low voltage
VDIH
Output high voltage
ZDigI
Input impedance
IDLeak
Digital input leakage current
1)
SOI1),
SOC1),
SOD1),
EOD,
RTR,
RTW,
WRDY,
PUP,
CLKO
PI<i>
PI<i>,
SII,
SIC,
SID,
PR,
PCS, CLKI
0.3
VSUP−
0.3
−1
7
pF
1
µA
0 V < Vpin < VSUP
in low impedance mode
Micronas
39
MAS 3506D
PRELIMINARY DATA SHEET
4.6.3.1. I2C Characteristics
at T = TA, VSUP =2.7 to 3.6 V, typ. values at TA = 27°C, VSUP = 3.0 V, CLKF = 14.725 MHz, duty cycle = 50 %
Symbol
Parameter
Pin Name
RON
Output resistance
fI2C
Min.
Typ.
Max.
Unit
Test Conditions
I2CC,
I2CD
60
Ω
Iload = 5 mA,
VSUP = 2.7 V
I2C bus frequency
I2CC
400
kHz
tI2C1
I2C Start condition setup time
I2CC,
I2CD
300
ns
tI2C2
I2C Stop condition setup time
I2CC,
I2CD
300
ns
tI2C3
I2C clock low pulse time
I2CC
1250
ns
tI2C4
I2C clock high pulse time
I2CC
1250
ns
tI2C5
I2C data hold time before
rising edge of clock
I2CC
80
ns
tI2C6
I2C data hold time after falling
edge of clock
I2CC
80
ns
VI2COL
I2C output low voltage
I2CC,
I2CD
0.3
V
ILOAD = 5 mA
II2COH
I2C output high leakage
current
I2CC,
I2CD
1
uA
VI2CH = 3.6 V
tI2COL1
I2C data output hold time after
falling edge of clock
I2CC,
I2CD
20
ns
tI2COL2
I2C data output setup time
before rising edge of clock
I2CC,
I2CD
250
ns
tW
Wait time
I2CC,
I2CD
0
0.5
4
fI2C = 400kHz
ms
1/fI2C
tI2C4
tI2C3
H
L
I2CC
tI2C1
tI2C5
tI2C6
tI2C2
H
L
I2CD as input
tI2COL2
tIC2OL1
H
L
I2CD as output
Fig. 4–15: I2C timing diagram
40
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
4.6.3.2. Timing of PIO-Signals
Table 4–1: PIO Characteristics
Symbol
Parameter
Pin Name
tBCTP
BC-frame toggle time
PI19
Behavior of the FRAME signals
The BC-FRAME-TOGGLE toggles its level from ’1’ to
’0’ and vice-versa every 432 ms. The BC-FRAMESYNC signal is set to ’1’ after the internal decoding
process for the Service Control Header has been finished for one frame. The signal could be used as an
interrupt input for the controller that triggers the read
out of the Service Control Header. As soon as the
MAS 3506D has recognized the corresponding read
command for the SCH, the BC-FRAME-SYNC is reset
Min.
Typ.
432
Max.
Unit
Test Conditions
ms
before sending the first data word. The time tread
depends on the response time of the controller. This
behavior reduces the possibility of not recognizing the
BC-FRAME-SYNC active state, if no controller interrupt line is available for this purpose.
A similar behavior is implemented for MPEG-FRAMESYNC signal. However the frame period is restricted to
the MPEG frame length, the reset is initiated by issuing
a ’Read Ancillary MPEG Data’ command.
Vh
VL
432 ms
BC-FRAME-TOGGLE (PI 19)
432 ms
tread
Vh
VL
BC-FRAME-SYNC (PI13)
Fig. 4–16: Schematic timing of BC-FRAME signals
Micronas
41
MAS 3506D
PRELIMINARY DATA SHEET
4.6.3.3. I2S Bus Characteristics – SDI
at T = TA, VSUP = 2.7 to 3.6 V, typ. values at TA = 27°C, VSUP = 3.0 V, CLKF = 14.725 MHz, duty cycle = 50 %
Symbol
Parameter
Pin Name
Min.
tSICLK
I2S clock input clock period
SIC
480
tSIIDS
I2S data setuptime before
falling edge of clock
SIC,
SID
50
tSIIDH
I2S data hold time
SID
50
tbw
Burst wait time
SIC,
SID
480
Typ.
Max.
tSICLK100
Unit
Test Conditions
ns
multimedia mode, mean
data rate < 150 kbit/s
ns
ns
TSICLK
H
SIC
L
H
(SII)
L
H
SID
L
TSIIDS
TSIIDH
Fig. 4–17: Serial input
42
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
4.6.3.4. I2S Characteristics – SDO
at T = TA, VSUP = 2.7 to 3.6 V, typ. values at TA = 27°C, VSUP = 3.0 V, CLKF = 14.725 MHz, duty cycle = 50 %
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
tSOCLK
I2S clock output period
SOC
tSOISS
I2S wordstrobe delay time
after falling edge of clock
SOC,
SOI
0
ns
tSOODC
I2S data delay time after
falling edge of clock
SOC,
SOD
0
ns
325
Unit
Test Conditions
ns
48 kHz Stereo
32 bit/sample
TSOCLK
H
SOC
L
H
SOI
L
TSOISS
TSOISS
H
SOD
L
TSOODC
Fig. 4–18: Serial output
4.6.3.5. Firmware Characteristics
at T = TA, VSUP = 2.7 to 3.6 V, typ. values at TA = 27°C, VSUP = 3.0 V, CLKF = 14.725 MHz, duty cycle = 50 %
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
Synchronization Times
tbcsync
Synchronization on Broadcast Channel
216
432
ms
tmpgsync
Synchronization on MPEG bit streams
12..36
72
ms
fs = 32 kHz, MPEG 2.5
8
10
s
step response
Time constants
tbcloop
Buffer controlled loop time constant (see Fig. 2– 5
2 on page 8)
tanc
Validity of ancillary data after rising edge of
MPEG-FRAME-SYNC signal
6
ms
tSCH
Validity of SCH-data after rising edge of
BC-FRAME-SYNC signal
400
ms
Tracking range of sampling clock recovery PLL
−200
Ranges
PLLRange
Micronas
200
ppm
43
MAS 3506D
PRELIMINARY DATA SHEET
4.6.4. DC/DC Converter Characteristics
at T = TA, VSUP = 3.0 V, CLKF = 14.725 MHz, fsw = 230 kHz, typ. values at TA = +27 °C.
Unless otherwise noted: VOUT = 3.0 V, VIN = 1.2 V
Symbol
Parameter
Pin Name
VIN1
Minimum start-up input voltage
VIN2
Minimum operating input
voltage
VOUT
Output voltage range
Min.
Typ.
Max.
Unit
Test Conditions
1)
0.9
1.1
V
ILOAD = 0 mA
DCCF = $08000
(Reset)
1)
0.6
0.9
V
ILOAD = 55 mA,
DCCF = $08000
(Reset)
1.3
1.8
V
ILOAD = 250 mA,
DCCF = $08000
(Reset)
V
VIN = 1.2 V
ILOAD = 50 mA
3.6
%
ILOAD = 50 mA
Tj = 27 °C
VIN = 1.2 V
150
mA
VIN = 0.9...1,5 V
250
mA
VIN = 1.8...3.0 V
VSENS
Bits 16..14, Bit 9 of DCCF
Register (hex):
1C000
18000
14000
10000
0C000
08000
04000
00000
1C200
18200
14200
10200
0C200
08200
04200
00200
3.567
3.460
3.354
3.248
3.144
3.039
2.935
2.831
2.729
2.625
2.524
2.422
2.321
2.219
2.118
2.017
VOTOL
Output voltage tolerance
VSENS
ILOAD1
Output current
VSENS
−3.6
ILOAD2
dVOUT/dVIN/
VOUT
Line regulation
VSENS
0.35
%/V
ILOAD = 50 mA
dVOUT/dVIN/
VOUT
Line regulation
VSENS
0.7
%/V
ILOAD = 250 mA,
VOUT = 3.5 V,
VIN = 2.4 V
dVOUT/VOUT
Load regulation
VSENS
−0.5
%
ILOAD = 50...150 mA
dVOUT/VOUT
Load regulation
VSENS
−0.5
%
ILOAD = 50...250 mA,
VOUT = 3.5 V,
VIN = 2.4 V
44
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
1)
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
hmax
Maximum efficiency
%
VIN = 3.0 V,
VOUT = 3.5 V
ISUPPLY
Supply current
VSENS
1.1
5
mA
VIN = 3.0 V, ILOAD = 0,
includ. switch current
IL,MAX
Inductor current limit
DCSO,
DCSG
1.0
1.4
A
RON
Switch on-resistance
DCSO,
DCSG
0.4
ILEAK
Switch leakage current
DCSO,
DCSG
0.1
1
µA
Tj = 27 °C,
converter = off;
ILOAD = 0 µA
fSW
Switch frequency
DCSO,
DCSG
230
460
kHz
Depending on DCCF
tSTART
Start-up zime asserting to
PUP
DCEN,
PUP
8
ms
VIN = 1.0 V,
ILOAD = 1 mA,
PUPLIM = 010 (Reset)
fSTARTUP
VSENSE
DCSO
250
kHz
VSENS < 1.9 V
90
156
Ω
All measurements are made with a C8 R/4L 20 µH, 25 mΩ ferrite ring-core coil, Zetex ZLMCS1000 Schottky
diode, and Sanyo/Oscon 6SA330M 330 µF, 25 mΩ ESR capacitors at input and output.
Micronas
45
MAS 3506D
PRELIMINARY DATA SHEET
4.6.5. Typical Performance Characteristics
Efficiency vs. Load Current
(Vout=3.5V)
Efficiency vs. Load Current
(Vout=3.0V)
100
100
Vin
80
1.8 V
Efficiency (%)
Efficiency (%)
80
2.4 V
3.0 V
60
40
Vin:
3.0V
2.4V
1.8V
20
0
10 -4
10-3
10-2
10-1
Vin
0.7 V
60
Vin:
2.4V
1.8V
1.5V
1.2V
0.9V
0.7V
40
20
0
10 -4
1
Load Current (A)
10-3
10-2
10-1
1
Load Current (A)
Efficiency vs. Load Current
(Vout=2.7V)
Efficiency vs. Load Current
(Vout=2.2V)
100
100
Vin
2.4 V
Vin
80
1.5 V
80
Efficiency (%)
Efficiency (%)
1.2 V
60
40
Vin:
2.4V
1.8V
1.2V
20
0.7 V
60
40
Vin:
1.5V
1.2V
0.9V
0.7V
20
0
0
10 -4
10-3
10-2
Load Current (A)
10-1
1
10 -4
10-3
10-2
10-1
1
Load Current (A)
Fig. 4–19: Efficiency vs. Load Current
46
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
Output Voltage vs. Input Voltage
Iload=250mA
Output Voltage vs. Input Voltage
Iload=50mA
3.6
3.2
3.1 V
3.5 V
3
3.4
Output Voltage (V)
Output Voltage (V)
2.8
3.2
3.1 V
3
2.8
2.7 V
2.6
2.4
2.2 V
2.2
2.7 V
2.6
2
1.5
2
2.5
3
3.5
0.9
Input Voltage (V)
1.4
1.9
2.4
2.9
Input Voltage (V)
Fig. 4–20: Output Voltage vs. Input Voltage
Output Voltage
vs. Load Current
3.6
Output Voltage
vs. Load Current
Vin
3.4
Vin=3V, 2.4V, 1.8V
3.4
Vin
3.2
Output Voltage
Output Voltage (V)
3
3.2
3
Vin=1.5V, 0.9V
2.8
2.6
2.4
Vin
2.8
2.2
Vin=1.5V, 0.9V
Vin=2.4V
2.6
0
0.1
2
0.2
Load Current (A)
0.3
0
0.02
0.04
0.06
0.08
Load Current (A)
Fig. 4–21: Output Voltage vs. Load Current
Micronas
47
MAS 3506D
Maximum Load Current
vs. Input Voltage
0.8
Maximum Load Current (A)
PRELIMINARY DATA SHEET
No Load Supply Current
vs. Input Voltage
6.0
0.6
3.5V
Vout = 3 V
2.2V
4.0
Vout
0.4
Vout=
3.5V
3.1V
2.7V
2.2V
0.2
2.0
0
0
1
2
Input Voltage (V)
3
0
0
1
2
3
Input Voltage (V)
Fig. 4–22: Maximum Load Current vs. Input Voltage
48
Fig. 4–23: No Load Supply Current vs. Input Voltage
Micronas
MAS 3506D
PRELIMINARY DATA SHEET
3V
3V
3V
3V
0A
0A
0A
500 µs/Div
500.00 µs/Div
Vin = 1 V; Iload = 0 mA
Vin = 1.2 V; Vout = 3 V
1 Load Current
2 Output Voltage
3 Inductor Current
200.0 mA/Div
100.0 mV/Div / AC-coupled
500.0 mA/Div
Fig. 4–24: Load Transient-Response
1
2
3
4
V (DCEN)
V (PUP)
Inductor Current
Output Voltage
2.000 V/Div
2.000 V/Div
500.0 mA/Div
2.000 V/Div
Fig. 4–26: Startup Waveform
3V
200 mA
2V
5.00 ms/Div
Iload = 100 mA; Vout = 3 V
2.000 V/Div
1 Vin
2 Output Voltage 50.00 mV/Div / AC-coupled
3 Inductor Current 200.0 mA/Div
Fig. 4–25: Line Transient-Response
Micronas
49
MAS 3506D
50
PRELIMINARY DATA SHEET
Micronas
PRELIMINARY DATA SHEET
Micronas
MAS 3506D
51
MAS 3506D
PRELIMINARY DATA SHEET
5. Data Sheet History
1. Preliminary data sheet: “MAS 3506D WorldSpace
Broadcast Channel Audio Decoder, July 25, 2001,
6251-433-1PD. First release of the preliminary data
sheet.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: www.micronas.com
Printed in Germany
Order No. 6251-433-1PD
52
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Micronas