MICRON MT28F002B5

2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
FLASH MEMORY
MT28F002B5
MT28F200B5
5V Only, Dual Supply (Smart 5)
FEATURES
40-Pin TSOP Type I 48-Pin TSOP Type I
• Five erase blocks:
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
Two main memory blocks
• Smart 5 technology (B5):
5V ±10% VCC
5V ±10% VPP application/production
programming
12V ±5% VPP compatibility production
programming
• Address access times: 60ns, 80ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• Byte- or word-wide READ and WRITE
(MT28F200B5, 128K x 16/256K x 8)
• Byte-wide READ and WRITE only
(MT28F002B5, 256K x 8)
• TSOP and SOP packaging options
OPTIONS
44-Pin SOP
GENERAL DESCRIPTION
The MT28F002B5 (x8) and MT28F200B5 (x16/x8)
are nonvolatile, electrically block-erasable (flash), programmable, read-only memories containing 2,097,152
bits organized as 262,144 bytes (8 bits) or 131,072
words (16 bits). Writing or erasing the device is done
with a 5V VPP voltage, while all operations are performed with a 5V VCC. Due to process technology
advances, 5V VPP is optimal for application and production programming. For backward compatibility with
SmartVoltage technology, 12V VPP is supported for a
maximum of 100 cycles and may be connected for up
to 100 cumulative hours. These devices are fabricated
with Micron’s advanced CMOS floating-gate process.
The MT28F002B5 and MT28F200B5 are organized
into five separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure or
overwrite, the devices feature a hardware-protected
boot block. Writing or erasing the boot block requires
either applying a super-voltage to the RP# pin or driving WP# HIGH in addition to executing the normal
write or erase sequences. This block may be used to store
code implemented in low-level system recovery. The
remaining blocks vary in density and are written and
erased with no additional security measures.
Please refer to Micron’s Web site (www.micron.com/
flash/htmls/datasheets.html) for the latest data sheet.
MARKING
• Timing
60ns access
80ns access
80ns access
-6
-8
-8 ET
• Configurations
256K x 8
128K x 16/256K x 8
• Boot Block Starting Word Address
Top (1FFFFH)
Bottom (00000H)
• Operating Temperature Range
Commercial (0°C to +70°C)
Extended (-40°C to +85°C)
• Packages
Plastic 44-pin SOP (600 mil)
Plastic 48-pin TSOP Type 1
(12mm x 20mm)
Plastic 40-pin TSOP
(10mm x 20mm)
MT28F002B5
MT28F200B5
T
B
None
ET
SG
WG
VG
Part Number Example:
MT28F200B5SG-8 T
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
PIN ASSIGNMENT (Top View)
48-Pin TSOP Type I
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
VPP
WP#
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
44-Pin SOP
A16
BYTE#
VSS
DQ15/(A - 1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
ORDER NUMBER AND PART MARKING
MT28F200B5WG-6 B
MT28F200B5WG-6 T
MT28F200B5WG-8 B
MT28F200B5WG-8 T
MT28F200B5WG-8 BET
MT28F200B5WG-8 TET
VPP
1
44
RP#
WP#
2
43
WE#
NC
3
42
A8
A7
4
41
A9
A6
5
40
A10
A5
6
39
A11
A4
7
38
A12
A3
8
37
A13
A2
9
36
A14
A1
10
35
A15
A0
11
34
A16
CE#
12
33
BYTE#
VSS
13
32
VSS
OE#
14
31
DQ15/(A - 1)
DQ0
15
30
DQ7
DQ8
16
29
DQ14
DQ1
17
28
DQ6
DQ9
18
27
DQ13
DQ2
19
26
DQ5
DQ10
20
25
DQ12
DQ3
21
24
DQ4
DQ11
22
23
VCC
ORDER NUMBER AND PART MARKING
MT28F200B5SG-6 B
MT28F200B5SG-6 T
MT28F200B5SG-8 B
MT28F200B5SG-8 T
MT28F200B5SG-8 BET
MT28F200B5SG-8 TET
40-Pin TSOP Type I
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
VPP
WP#
NC
A7
A6
A5
A4
A3
A2
A1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A17
VSS
NC
NC
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
ORDER NUMBER AND PART MARKING
MT28F002B5VG-6 B
MT28F002B5VG-6 T
MT28F002B5VG-8 B
MT28F002B5VG-8 T
MT28F002B5VG-8 BET
MT28F002B5VG-8 TET
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
BYTE#1
8
Input
Buffer
7
Input
Buffer
I/O
Control
Logic
16KB Boot Block
Addr.
Buffer/
18 (19)
9
X - Decoder/Block Erase Control
A0-A16/(A17)
Latch
A9
9
(10)
Addr.
Power
(Current)
Control
Counter
8KB Parameter Block
8KB Parameter Block
Input
Buffer
96KB Main Block
(A - 1)
Input Data
Latch/Mux
16
WP#
CE#
OE#
WE#
Command
State
Execution
Machine
Logic
YDecoder
RP#
VCC
VPP
DQ15/(A - 1)1
128KB Main Block
DQ8-DQ141
DQ0-DQ7
7
Y - Select Gates
8
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
VPP
Switch/
Pump
Output
Buffer
DQ15
Status
Register
Identification
Register
Output
Buffer
7
8
MUX
Output
Buffer
8
NOTE
1. Does not apply to MT28F002B5.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
44-PIN SOP 40-PIN TSOP 48-PIN TSOP
NUMBERS NUMBERS NUMBERS SYMBOL
43
9
11
WE#
TYPE
Input
2
12
14
WP#
Input
12
22
26
CE#
Input
44
10
12
RP#
Input
14
24
28
OE#
Input
33
–
47
BYTE#
Input
A0-A16/
(A17)
Input
11, 10, 9, 8, 21, 20, 19,
25, 24, 23,
7, 6, 5, 4,
18, 17, 16,
22, 21, 20,
42, 41, 40, 15, 14, 8, 7, 19, 18, 8, 7,
39, 38, 37, 36, 6, 5, 4, 3, 6, 5, 4, 3, 2,
36, 35, 34
2, 1, 40
1, 48
31
–
45
15, 17, 19,
21, 24, 26,
28, 30
16, 18, 20,
22, 25, 27,
29
1
23
13, 32
3
DESCRIPTION
Write Enable: Determines if a given cycle is a WRITE cycle. If
WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
Write Protect: Unlocks the boot block when HIGH if VPP =
VPPH1 (5V) or VPPH2 (12V)1 and RP# = VIH during a WRITE or
ERASE. Does not affect WRITE or ERASE operation on other
blocks.
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
Reset/Power-Down: When LOW, RP# clears the status register,
sets the internal state machine (ISM) to the array read mode
and places the device in deep power-down mode. All inputs,
including CE#, are “Don’t Care,” and all outputs are High-Z.
RP# unlocks the boot block and overrides the condition of
WP# when at VHH (12V), and must be held at VIH during all
other modes of operation.
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active through
DQ8-DQ15. If BYTE# = LOW, DQ8-DQ14 are High-Z, and all
data is accessed through DQ0-DQ7. DQ15/(A - 1) becomes the
least significant address input.
Address Inputs: Select a unique, 16-bit word or 8-bit byte. The
DQ15/(A - 1) input becomes the lowest order address when
BYTE# = LOW (MT28F200B5) to allow for a selection of an
8-bit byte from the 262,144 available.
DQ15
(A - 1)
Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB
Output of address input when BYTE# = LOW during READ or WRITE
operation.
25-28, 32-35 29, 31, 33, DQ0-DQ7 Input/ Data I/Os: Data output pins during any READ operation or
35, 38, 40,
Output data input pins during a WRITE. These pins are used to input
42, 44
commands to the CEL.
–
30, 32, 34, DQ8-DQ14 Input/ Data I/Os: Data output pins during any READ operation or
36, 39, 41,
Output data input pins during a WRITE when BYTE# = HIGH. These
43
pins are High-Z when BYTE# is LOW.
11
13
VPP
Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM
until completion of the WRITE or ERASE, VPP must be at VPPH1
(5V) or VPPH2 (12V)1. VPP = “Don’t Care” during all other
operations.
30, 31
37
VCC
Supply Power Supply: +5V ±10%.
23, 39
27, 46
VSS
Supply Ground.
13, 29, 37, 38 9, 10, 15-17
NC
–
No Connect: These pins may be driven or left unconnected.
NOTE: 1. For SmartVoltage-compatible production programming, 12V VPP is supported for a maximum of 100 cycles and may
be connected for up to 100 cumulative hours.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
TRUTH TABLE (MT28F200B5)1
RP#
CE#
OE#
A9
VPP
Standby
FUNCTION
H
H
X
WE# WP# BYTE# A0
X
X
X
X
X
X
DQ0-DQ7 DQ8-DQ14 DQ15/A - 1
High-Z
High-Z
High-Z
RESET
L
X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
H
L
L
H
X
H
X
X
X
Data-Out
Data-Out
Data-Out
READ
READ (word mode)
READ (byte mode)
H
L
L
H
X
L
X
X
X
Data-Out
High-Z
A-1
Output Disable
H
L
H
H
X
X
X
X
X
High-Z
High-Z
High-Z
ERASE SETUP
H
L
H
L
X
X
X
X
X
20H
X
X
ERASE CONFIRM3
H
L
H
L
X
X
X
X
VPPH
D0H
X
X
WRITE SETUP
H
L
H
L
X
X
X
X
X
10H/40H
X
X
WRITE (word mode)4
H
L
H
L
X
H
X
X
VPPH
Data-In
Data-In
Data-In
WRITE (byte mode)4
H
L
H
L
X
L
X
X
VPPH
Data-In
X
A-1
H
L
H
L
X
X
X
X
X
FFH
X
X
H
L
H
L
X
X
X
X
X
20H
X
X
VHH
L
H
L
X
X
X
X
VPPH
D0H
X
X
H
L
H
L
H
X
X
X
VPPH
D0H
X
X
WRITE/ERASE (EXCEPT BOOT BLOCK)2
READ ARRAY5
WRITE/ERASE (BOOT
BLOCK)2, 7
ERASE SETUP
ERASE CONFIRM3
ERASE CONFIRM3, 6
WRITE SETUP
WRITE (word mode)4
WRITE (word mode)4, 6
WRITE (byte mode)4
H
L
H
L
X
X
X
X
X
10H/40H
X
X
VHH
L
H
L
X
H
X
X
VPPH
Data-In
Data-In
Data-In
H
L
H
L
H
H
X
X
VPPH
Data-In
Data-In
Data-In
VHH
L
H
L
X
L
X
X
VPPH
Data-In
X
A-1
WRITE (byte mode)4, 6
H
L
H
L
H
L
X
X
VPPH
Data-In
X
A-1
READ ARRAY5
H
L
H
L
X
X
X
X
X
FFH
X
X
Manufacturer Compatibility
(word mode)10
H
L
L
H
X
H
L
VID
X
89H
00H
–
Manufacturer Compatibility
(byte mode)
H
L
L
H
X
L
L
VID
X
89H
High-Z
X
Device (word mode, top boot)10
H
L
L
H
X
H
H
VID
X
74H
22H
–
Device (byte mode, top boot)
H
L
L
H
X
L
H
VID
X
74H
High-Z
X
Device (word mode, bottom boot) 10
H
L
L
H
X
H
H
VID
X
75H
22H
–
Device (byte mode, bottom boot)
H
L
L
H
X
L
H
VID
X
75H
High-Z
X
DEVICE IDENTIFICATION8, 9
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).
VPPH = VPPH1 = 5V.
Operation must be preceded by ERASE SETUP command.
Operation must be preceded by WRITE SETUP command.
The READ ARRAY command must be issued before reading the array after writing or erasing.
When WP# = VIH, RP# may be at VIH or VHH.
VHH = 12V.
VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.
A1-A8, A10-A16 = VIL.
Value reflects DQ8-DQ15.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
TRUTH TABLE (MT28F002B5)1
RP#
CE#
OE#
WE#
WP#
A0
A9
VPP
DQ0-DQ7
Standby
FUNCTION
H
H
X
X
X
X
X
X
High-Z
RESET
L
X
X
X
X
X
X
X
High-Z
READ
H
L
L
H
X
X
X
X
Data-Out
Output Disable
H
L
H
H
X
X
X
X
High-Z
H
L
H
L
X
X
X
X
20H
H
L
H
L
X
X
X
VPPH
D0H
READ
WRITE/ERASE (EXCEPT BOOT BLOCK)2
ERASE SETUP
ERASE
CONFIRM3
WRITE SETUP
H
L
H
L
X
X
X
X
10H/40H
WRITE4
H
L
H
L
X
X
X
VPPH
Data-In
H
L
H
L
X
X
X
X
FFH
H
L
H
L
X
X
X
X
20H
READ
ARRAY5
WRITE/ERASE (BOOT
BLOCK)2, 7
ERASE SETUP
ERASE
CONFIRM3
VHH
L
H
L
X
X
X
VPPH
D0H
ERASE CONFIRM3, 6
H
L
H
L
H
X
X
VPPH
D0H
WRITE SETUP
H
L
H
L
X
X
X
X
10H/40H
WRITE4
VHH
L
H
L
X
X
X
VPPH
Data-In
WRITE4, 6
H
L
H
L
H
X
X
VPPH
Data-In
READ ARRAY5
H
L
H
L
X
X
X
X
FFH
Manufacturer Compatibility
H
L
L
H
X
L
VID
X
89H
Device (top boot)
H
L
L
H
X
H
VID
X
7CH
Device (bottom boot)
H
L
L
H
X
H
VID
X
7DH
DEVICE
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
9.
IDENTIFICATION8, 9
L = VIL, H = VIH, X = VIL or VIH.
VPPH = VPPH1 = 5V.
Operation must be preceded by ERASE SETUP command.
Operation must be preceded by WRITE SETUP command.
The READ ARRAY command must be issued before reading the array after writing or erasing.
When WP# = VIH, RP# may be at VIH or VHH.
VHH = 12V.
VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.
A1-A8, A10-A17 = VIL.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
FUNCTIONAL DESCRIPTION
the RP# pin or driving the WP# pin HIGH. One of these
two conditions must exist along with the VPP voltage
(5V or 12V) on the VPP pin before a WRITE or ERASE will
be performed on the boot block. The remaining blocks
require that only the VPP voltage be present on the VPP
pin before writing or erasing.
The MT28F002B5 and MT28F200B5 flash memory
incorporate a number of features ideally suited for
system firmware. The memory array is segmented into
individual erase blocks. Each block may be erased
without affecting data stored in other blocks. These
memory blocks are read, written and erased with commands to the command execution logic (CEL). The CEL
controls the operation of the internal state machine
(ISM), which completely controls all WRITE, BLOCK
ERASE and VERIFY operations. The ISM protects each
memory location from over-erasure and optimizes each
memory location for maximum data retention. In addition, the ISM greatly simplifies the control necessary
for writing the device in-system or in an external
programmer.
The Functional Description provides detailed information on the operation of the MT28F002B5 and
MT28F200B5 and is organized into these sections:
•
•
•
•
•
•
•
•
•
•
•
HARDWARE-PROTECTED BOOT BLOCK
This block of the memory array can be erased or
written only when the RP# pin is taken to VHH or when
the WP# pin is brought HIGH. This provides additional
security for the core firmware during in-system firmware updates should an unintentional power fluctuation or system reset occur. The MT28F002B5 and
MT28F200B5 are available with the boot block starting
at the bottom of the address space (“B” suffix) or the top
of the address space (“T” suffix).
SELECTABLE BUS SIZE (MT28F200B5 ONLY)
The MT28F200B5 allows selection of an 8-bit (256K
x 8) or 16-bit (128K x 16) data bus for reading and
writing the memory. The BYTE# pin is used to select the
bus width. In the x16 configuration, control data is read
or written only on the lower eight bits (DQ0-DQ7).
Data written to the memory array utilizes all active
data pins for the selected configuration. When the x8
configuration is selected, data is written in byte form;
when the x16 configuration is selected, data is written
in word form.
Overview
Memory Architecture
Output (READ) Operations
Input Operations
Command Set
ISM Status Register
Command Execution
Error Handling
WRITE/ERASE Cycle Endurance
Power Usage
Power-Up
INTERNAL STATE MACHINE (ISM)
BLOCK ERASE and BYTE/WORD WRITE timing are
simplified with an ISM that controls all erase and write
algorithms in the memory array. The ISM ensures
protection against overerasure and optimizes write
margin to each cell.
During WRITE operations, the ISM automatically
increments and monitors WRITE attempts, verifies write
margin on each memory cell and updates the ISM status
register. When BLOCK ERASE is performed, the ISM
automatically overwrites the entire addressed block
(eliminates overerasure), increments and monitors
ERASE attempts, and sets bits in the ISM status register.
OVERVIEW
SMART 5 TECHNOLOGY (B5)
Smart 5 technology allows maximum flexibility for
in-system READ, WRITE and ERASE operations. For 5Vonly systems, WRITE and ERASE operations may be
executed with a VPP voltage of 5V. Due to process
technology advances, 5V VPP is optimal for application
and production programming. For backward compatibility with SmartVoltage technology, 12V VPP is supported for a maximum of 100 cycles and may be
connected for up to 100 cumulative hours. However,
no performance increase will be realized. For any operation, VCC may be at 5V.
ISM STATUS REGISTER
The ISM status register allows an external processor
to monitor the status of the ISM during WRITE and
ERASE operations. Two bits of the 8-bit status register
are set and cleared entirely by the ISM. These bits
indicate whether the ISM is busy with a WRITE or
ERASE task and when an ERASE has been suspended.
Additional error information is set in three other bits:
VPP status, write status and erase status.
FIVE INDEPENDENTLY ERASABLE MEMORY
BLOCKS
The MT28F002B5 and MT28F200B5 are organized
into five independently erasable memory blocks that
allow portions of the memory to be erased without
affecting the rest of the memory data. A special boot
block is hardware-protected against inadvertent erasure or writing by requiring either a super-voltage on
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
COMMAND EXECUTION LOGIC (CEL)
The CEL receives and interprets commands to the
device. These commands control the operation of the
ISM and the read path (i.e., memory array, ID register or
status register). Commands may be issued to the CEL
while the ISM is active. However, there are restrictions
on what commands are allowed in this condition. See
the Command Execution section for more detail.
and are independently erasable. When blocks rather
than the entire array are erased, total device endurance
is enhanced, as is system flexibility. Only the ERASE
function is block-oriented. All READ and WRITE operations are done on a random-access basis.
The boot block is protected from unintentional
ERASE or WRITE with a hardware protection circuit
which requires that a super-voltage be applied to RP# or
that the WP# pin be driven HIGH before erasure is
commenced. The boot block is intended for the core
firmware required for basic system functionality. The
remaining four blocks do not require that either of
these two conditions be met before WRITE or ERASE
operations.
DEEP POWER-DOWN MODE
To allow for maximum power conservation, the
MT28F002B5 and MT28F200B5 feature a very low current, deep power-down mode. To enter this mode, the
RP# pin is taken to VSS ±0.2V. In this mode, the current
draw is a maximum of 20µA at 5V VCC. Entering deep
power-down also clears the status register and sets the
ISM to the read array mode.
BOOT BLOCK
The hardware-protected boot block provides extra
security for the most sensitive portions of the firmware.
This 16KB block may only be erased or written when the
RP# pin is at the specified boot block unlock voltage
(VHH) of 12V or when the WP# pin is VIH. During a
WRITE or ERASE of the boot block, the RP# pin must be
MEMORY ARCHITECTURE
The MT28F002B5 and MT28F200B5 memory array
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into five addressable blocks that vary in size
WORD ADDRESS BYTE ADDRESS
WORD ADDRESS BYTE ADDRESS
1FFFFH
3FFFFH
1FFFFH
3FFFFH
1E000H
1DFFFH
3C000H
3BFFFH
1D000H
1CFFFH
3A000H
39FFFH
1C000H
1BFFFH
38000H
37FFFH
16KB Boot Block
128KB Main Block
8KB Parameter Block
8KB Parameter Block
10000H
0FFFFH
20000H
1FFFFH
96KB Main Block
96KB Main Block
04000H
03FFFH
08000H
07FFFH
03000H
02FFFH
06000H
05FFFH
02000H
01FFFH
04000H
03FFFH
10000H
0FFFFH
20000H
1FFFFH
8KB Parameter Block
128KB Main Block
8KB Parameter Block
16KB Boot Block
00000H
00000H
00000H
Bottom Boot
MT28F002B5/200B5xx-xxB
00000H
Top Boot
MT28F002B5/200B5xx-xxT
Figure 1
Memory Address Maps
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2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
held at VHH or the WP# pin held HIGH until the ERASE
or WRITE is completed. The VPP pin must be at VPPH (5V
or 12V) when the boot block is written to or erased.
The MT28F002B5 and MT28F200B5 are available in
two configurations and top or bottom boot block. The
top boot block version supports processors of the x86
variety. The bottom boot block version is intended for
680X0 and RISC applications. Figure 1 illustrates the
memory address maps associated with these two
versions.
After power-up or RESET, the device will automatically be in the array read mode. All commands and their
operations are covered in the Command Set and Command Execution sections.
STATUS REGISTER
Performing a READ of the status register requires the
same input sequencing as a READ of the array except
that the address inputs are “Don’t Care.” The status
register contents are always output on DQ0-DQ7, regardless of the condition of BYTE# on the MT28F200B5.
DQ8-DQ15 are LOW when BYTE# is HIGH, and DQ8DQ14 are High-Z when BYTE# is LOW. Data from the
status register is latched on the falling edge of OE# or
CE#, whichever occurs last. If the contents of the status
register change during a READ of the status register,
either OE# or CE# may be toggled while the other is
held LOW to update the output.
Following a WRITE or ERASE, the device automatically enters the status register read mode. In addition,
a READ during a WRITE or ERASE will produce the
status register contents on DQ0-DQ7. When the device
is in the erase suspend mode, a READ operation will
produce the status register contents until another command is issued. In certain other modes, READ STATUS
REGISTER may be given to return to the status register
read mode. All commands and their operations are
covered in the Command Set and Command Execution
sections.
PARAMETER BLOCKS
The two 8KB parameter blocks store less sensitive
and more frequently changing system parameters and
also may store configuration or diagnostic coding.
These blocks are enabled for erasure when the VPP pin
is at VPPH. No super-voltage unlock or WP# control is
required.
MAIN MEMORY BLOCKS
The two remaining blocks are general-purpose
memory blocks and do not require a super-voltage on
RP# or WP# control to be erased or written. These
blocks are intended for code storage, ROM-resident
applications or operating systems that require insystem update capability.
OUTPUT (READ) OPERATIONS
The MT28F002B5 and MT28F200B5 feature three
different types of READs. Depending on the current
mode of the device, a READ operation will produce data
from the memory array, status register or device identification register. In each of these three cases, the WE#,
CE# and OE# inputs are controlled in a similar manner.
Moving between modes to perform a specific READ is
covered in the Command Execution section.
IDENTIFICATION REGISTER
A READ of the two 8-bit device identification registers requires the same input sequencing as a READ of
the array. WE# must be HIGH, and OE# and CE# must
be LOW. However, ID register data is output only on
DQ0-DQ7, regardless of the condition of BYTE# on the
MT28F200B5. A0 is used to decode between the two
bytes of the device ID register; all other address inputs
are “Don’t Care.” When A0 is LOW, the manufacturer
compatibility ID is output, and when A0 is HIGH, the
device ID is output. DQ8-DQ15 are High-Z when BYTE#
is LOW. When BYTE# is HIGH, DQ8-DQ15 are 00H
when the manufacturer compatibility ID is read and
22H when the device ID is read.
To get to the identification register read mode,
READ IDENTIFICATION may be issued while the device
is in certain other modes. In addition, the identification register read mode can be reached by applying a
super-voltage (VID) to the A9 pin. Using this method,
the ID register can be read while the device is in any
mode. Once A9 is returned to VIL or VIH, the device will
return to the previous mode.
MEMORY ARRAY
To read the memory array, WE# must be HIGH, and
OE# and CE# must be LOW. Valid data will be output
on the DQ pins once these conditions have been met
and a valid address is given. Valid data will remain on
the DQ pins until the address changes, or until OE# or
CE# goes HIGH, whichever occurs first. The DQ pins
will continue to output new data after each address
transition as long as OE# and CE# remain LOW.
The MT28F200B5 features selectable bus widths.
When the memory array is accessed as a 128K x 16,
BYTE# is HIGH, and data will be output on DQ0-DQ15.
To access the memory array as a 256K x 8, BYTE# must
be LOW, DQ8-DQ14 are High-Z, and all data is output
on DQ0-DQ7. The DQ15/(A - 1) pin becomes the lowest
order address input so that 262,144 locations can be
read.
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SMART 5 BOOT BLOCK FLASH MEMORY
INPUT OPERATIONS
MEMORY ARRAY
A WRITE to the memory array sets the desired bits to
logic 0s but cannot change a given bit to a logic 1 from
a logic 0. Setting any bits to a logic 1 requires that the
entire block be erased. To perform a WRITE, OE# must
be HIGH, CE# and WE# must be LOW, and VPP must be
set to VPPH1 or VPPH2. Writing to the boot block also
requires that the RP# pin be at VHH or WP# be HIGH. A0A16/(A17) provide the address to be written, while the
data to be written to the array is input on the DQ pins.
The data and addresses are latched on the rising edge of
CE# (CE#-controlled) or WE# (WE#-controlled), whichever occurs first. A WRITE must be preceded by a WRITE
SETUP command. Details on how to input data to the
array will be covered in the Write Sequence section.
Selectable bus sizing applies to WRITEs as it does to
READs on the MT28F200B5. When BYTE# is LOW (byte
mode), data is input on DQ0-DQ7, DQ8-DQ14 are
High-Z and DQ15 becomes the lowest order address
input. When BYTE# is HIGH (word mode), data is input
on DQ0-DQ15.
The DQ pins are used either to input data to the
array or to input a command to the CEL. A command
input issues an 8-bit command to the CEL to control the
mode of operation of the device. A WRITE is used to
input data to the memory array. The following section
describes both types of inputs. More information describing how to use the two types of inputs to write or
erase the device is provided in the Command Execution
section.
COMMANDS
To perform a command input, OE# must be HIGH,
and CE# and WE# must be LOW. Addresses are “Don’t
Care” but must be held stable, except during an ERASE
CONFIRM (described in a later section). The 8-bit command is input on DQ0-DQ7, while DQ8-DQ15 are
“Don’t Care” on the MT28F200B5. The command is
latched on the rising edge of CE# (CE#-controlled) or
WE# (WE#-controlled), whichever occurs first. The
condition of BYTE# on the MT28F200B5 has no effect
on a command input.
Table 1
Command Set
COMMAND
HEX CODE
DESCRIPTION
RESERVED
00H
This command and all unlisted commands are invalid and should not
be called. These commands are reserved to allow for future feature
enhancements.
READ ARRAY
FFH
Must be issued after any other command cycle before the array can be
read. It is not necessary to issue this command after power-up or RESET.
IDENTIFY DEVICE
90H
Allows the device ID and manufacturer compatibility ID to be read. A0 is
used to decode between the manufacturer compatibility ID (A0 = LOW)
and device ID (A0 = HIGH).
READ STATUS REGISTER
70H
Allows the status register to be read. Please refer to Table 2 for more
information on the status register bits.
CLEAR STATUS REGISTER
50H
Clears status register bits 3-5, which cannot be cleared by the ISM.
ERASE SETUP
20H
The first command given in the two-cycle ERASE sequence. The ERASE will
not be completed unless followed by ERASE CONFIRM.
ERASE CONFIRM/RESUME
D0H
The second command given in the two-cycle ERASE sequence. Must follow
an ERASE SETUP command to be valid. Also used during an ERASE
SUSPEND to resume the ERASE.
40H or
10H
The first command given in the two-cycle WRITE sequence. The write
data and address are given in the following cycle to complete the WRITE.
B0H
Requests a halt of the ERASE and puts the device into the erase suspend
mode. When the device is in this mode, only READ STATUS REGISTER,
READ ARRAY and ERASE RESUME commands may be executed.
WRITE SETUP
ERASE SUSPEND
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COMMAND SET
To simplify writing of the memory blocks, the
MT28F002B5 and MT28F200B5 incorporate an ISM
that controls all internal algorithms for the WRITE and
ERASE cycles. An 8-bit command set is used to control
the device. Details on how to sequence commands are
provided in the Command Execution section. Table 1
lists the valid commands.
ISM status unless OE# or CE# is toggled. If the device is
not in the write, erase, erase suspend or status register
read mode, READ STATUS REGISTER (70H) can be
issued to view the status register contents.
All of the defined bits are set by the ISM, but only the
ISM and erase suspend status bits are reset by the ISM.
The erase, write and VPP status bits must be cleared
using CLEAR STATUS REGISTER. If the VPP status bit
(SR3) is set, the CEL will not allow further WRITE or
ERASE operations until the status register is cleared.
This allows the user to choose when to poll and clear
the status register. For example, the host system may
perform multiple BYTE WRITE operations before checking the status register instead of checking after each
individual WRITE. Asserting the RP# signal or powering
down the device will also clear the status register.
ISM STATUS REGISTER
The 8-bit ISM status register (see Table 2) is polled to
check for WRITE or ERASE completion or any related
errors. During or following a WRITE, ERASE or ERASE
SUSPEND, a READ operation will output the status
register contents on DQ0-DQ7 without prior command. While the status register contents are read, the
outputs will not be updated if there is a change in the
Table 2
Status Register
STATUS
BIT #
STATUS REGISTER BIT
DESCRIPTION
SR7
ISM STATUS
1 = Ready
0 = Busy
The ISMS bit displays the active status of the state machine during
WRITE or BLOCK ERASE operations. The controlling logic polls this
bit to determine when the erase and write status bits are valid.
SR6
ERASE SUSPEND STATUS
1 = ERASE suspended
0 = ERASE in progress/completed
Issuing an ERASE SUSPEND places the ISM in the suspend mode
and sets this and the ISMS bit to “1.” The ESS bit will remain “1” until
an ERASE RESUME is issued.
SR5
ERASE STATUS
1 = BLOCK ERASE error
0 = Successful BLOCK ERASE
ES is set to “1” after the maximum number of ERASE cycles is
executed by the ISM without a successful verify. ES is only cleared
by a CLEAR STATUS REGISTER command or after a RESET.
SR4
WRITE STATUS
1 = WORD/BYTE WRITE error
0 = Successful WORD/
BYTE WRITE
WS is set to “1” after the maximum number of WRITE cycles is
executed by the ISM without a successful verify. WS is only cleared
by a CLEAR STATUS REGISTER command or after a RESET.
SR3
VPP STATUS
1 = No VPP voltage detected
0 = VPP present
VPPS detects the presence of a VPP voltage. It does not monitor VPP
continuously, nor does it indicate a valid VPP voltage. The VPP pin is
sampled for 5V after WRITE or ERASE CONFIRM is given. VPPS must be
cleared by CLEAR STATUS REGISTER or by a RESET.
RESERVED
Reserved for future use.
SR0-2
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COMMAND EXECUTION
WRITE SEQUENCE
Two consecutive cycles are needed to write data to
the array. WRITE SETUP (40H or 10H) is given in the
first cycle. The next cycle is the WRITE, during which
the write address and data are issued and VPP is brought
to VPPH. Writing to the boot block also requires that the
RP# pin be brought to VHH or that the WP# pin be
brought HIGH at the same time VPP is brought to VPPH.
The ISM will now begin to write the word or byte. VPP
must be held at VPPH until the WRITE is completed
(SR7 = 1).
While the ISM executes the WRITE, the ISM status
bit (SR7) will be at “0,” and the device will not respond
to any commands. Any READ operation will produce
the status register contents on DQ0-DQ7. When the
ISM status bit (SR7) is set to a logic 1, the WRITE has
been completed, and the device will go into the status
register read mode until another command is given.
After the ISM has initiated the WRITE, it cannot be
aborted except by a RESET or by powering down the
part. Doing either during a WRITE will corrupt the data
being written. If only the WRITE SETUP command has
been given, the WRITE may be nullified by performing
Commands are issued to bring the device into different operational modes. Each mode allows specific operations to be performed. Several modes require a
sequence of commands to be written before they are
reached. The following section describes the properties
of each mode, and Table 3 lists all command sequences
required to perform the desired operation.
READ ARRAY
The array read mode is the initial state of the device
upon power-up and after a RESET. If the device is in any
other mode, READ ARRAY (FFH) must be given to
return to the array read mode. Unlike the WRITE SETUP
command (40H), READ ARRAY does not need to be
given before each individual read access.
IDENTIFY DEVICE
IDENTIFY DEVICE (90H) may be written to the CEL
to enter the identify device mode. While the device is
in this mode, any READ will produce the device ID
when A0 is HIGH and manufacturer compatibility ID
when A0 is LOW. The device will remain in this mode
until another command is given.
Table 3
Command Sequences
COMMANDS
BUS
1ST
2ND
CYCLES
CYCLE
CYCLE
REQ’D OPERATION ADDRESS DATA OPERATION ADDRESS DATA
NOTES
READ ARRAY
1
WRITE
X
FFH
IDENTIFY DEVICE
3
WRITE
X
90H
READ
IA
ID
2, 3
READ STATUS REGISTER
2
WRITE
X
70H
READ
X
SRD
4
CLEAR STATUS REGISTER
1
WRITE
X
50H
ERASE SETUP/CONFIRM
2
WRITE
X
20H
WRITE
BA
D0H
5, 6
ERASE SUSPEND/RESUME
2
WRITE
X
B0H
WRITE
X
D0H
WRITE SETUP/WRITE
2
WRITE
X
40H
WRITE
WA
WD
6, 7
ALTERNATE WORD/BYTE
WRITE
2
WRITE
X
10H
WRITE
WA
WD
6, 7
NOTE: 1.
2.
3.
4.
5.
6.
7.
1
Must follow WRITE or ERASE CONFIRM commands to the CEL in order to enable flash array READ cycles.
IA = Identify Address: 00H for manufacturer compatibility ID; 01H for device ID.
ID = Identify Data.
SRD = Status Register Data.
On x16 (X00) devices BA = Block Address (A12-A16), on x8 (00X) devices BA = Block Address (A13-A17).
Addresses are “Don’t Care” in first cycle but must be held stable.
WA = Address to be written; WD = Data to be written to WA.
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a null WRITE. To execute a null WRITE, FFH must be
written when BYTE# is LOW, or FFFFH must be written
when BYTE# is HIGH. Once the ISM status bit (SR7) has
been set, the device will be in the status register read
mode until another command is issued.
requires that either the RP# pin be set to VHH or the WP#
pin be held HIGH at the same time VPP is set to VPPH.
ERASE SUSPENSION
The only command that may be issued while an
ERASE is in progress is ERASE SUSPEND. This command
allows other commands to be executed while pausing
the ERASE in progress. Once the device has reached the
erase suspend mode, the erase suspend status bit (SR6)
and ISM status bit (SR7) will be set. The device may now
be given a READ ARRAY, ERASE RESUME or READ
STATUS REGISTER command. After READ ARRAY has
been issued, any location not within the block being
erased may be read. If ERASE RESUME is issued before
SR6 has been set, the device will immediately proceed
with the ERASE in progress.
ERASE SEQUENCE
Executing an ERASE sequence will set all bits within
a block to logic 1. The command sequence necessary to
execute an ERASE is similar to that of a WRITE. To
provide added security against accidental block erasure, two consecutive command cycles are required to
initiate an ERASE of a block. In the first cycle, addresses
are “Don’t Care,” and ERASE SETUP (20H) is given. In
the second cycle, VPP must be brought to VPPH, an
address within the block to be erased must be issued,
and ERASE CONFIRM (D0H) must be given. If a command other than ERASE CONFIRM is given, the write
and erase status bits (SR4 and SR5) will be set, and the
device will be in the status register read mode.
After the ERASE CONFIRM (D0H) is issued, the ISM
will start the ERASE of the addressed block. Any READ
operation will output the status register contents on
DQ0-DQ7. VPP must be held at VPPH until the ERASE is
completed (SR7 = 1). Once the ERASE is completed, the
device will be in the status register read mode until
another command is issued. Erasing the boot block also
ERROR HANDLING
After the ISM status bit (SR7) has been set, the VPP
(SR3), write (SR4) and erase (SR5) status bits may be
checked. If one or a combination of these three bits has
been set, an error has occurred. The ISM cannot reset
these three bits. To clear these bits, CLEAR STATUS
REGISTER (50H) must be given. If the VPP status bit
(SR3) is set, further WRITE or ERASE operations cannot
resume until the status register is cleared. Table 4 lists
the combination of errors.
Table 4
Status Register Error Decode1
SR5
0
STATUS BITS
SR4
SR3
0
0
ERROR DESCRIPTION
No errors
0
0
1
VPP voltage error
0
1
0
WRITE error
0
1
1
WRITE error, VPP voltage not valid at time of WRITE
1
0
0
ERASE error
1
0
1
ERASE error, VPP voltage not valid at time of ERASE CONFIRM
1
1
0
Command sequencing error or WRITE/ERASE error
1
1
1
Command sequencing error, VPP voltage error, with WRITE and ERASE errors
NOTE: 1. SR3-SR5 must be cleared using CLEAR STATUS REGISTER.
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WRITE/ERASE CYCLE ENDURANCE
POWER-UP
The MT28F002B5 and MT28F200B5 are designed
and fabricated to meet advanced firmware storage requirements. To ensure this level of reliability, VPP must
be at 5V ±10% during WRITE or ERASE cycles. Due to
process technology advances, 5V VPP is optimal for
application and production programming. For backward compatibility with SmartVoltage technology, 12V
VPP is supported for a maximum of 100 cycles and may
be connected for up to 100 cumulative hours. Operation outside these limits may reduce the number of
WRITE and ERASE cycles that can be performed on the
device.
The likelihood of unwanted WRITE or ERASE operations is minimized since two consecutive cycles are
required to execute either operation. However, to reset
the ISM and to provide additional protection while VCC
is ramping, one of the following conditions must be
met:
• RP# must be held LOW until VCC is at valid
functional level; or
• CE# or WE# may be held HIGH and
RP# must be toggled from VCC-GND-VCC.
After a power-up or RESET, the status register is reset,
and the device will enter the array read mode.
POWER USAGE
RP#
,,,
,,,
The MT28F002B5 and MT28F200B5 offer several
power-saving features that may be utilized in the array
read mode to conserve power. Deep power-down mode
is enabled by bringing RP# LOW. Current draw (ICC) in
this mode is a maximum of 20µA at 5V VCC. When CE#
is HIGH, the device will enter standby mode. In this
mode, maximum ICC current is 130µA at 5V. If CE# is
brought HIGH during a WRITE or ERASE, the ISM will
continue to operate, and the device will consume the
respective active power until the WRITE or ERASE is
completed.
Note 1
VCC
(5V)
t
AA
Address
,,
,,
VALID
VALID
Data
t
RWH
UNDEFINED
NOTE:
1. VCC must be within the valid operating range before RP#
goes HIGH.
Figure 2
Power-Up/Reset Timing Diagram
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SELF-TIMED WRITE SEQUENCE
(WORD or BYTE WRITE)1
COMPLETE WRITE STATUS-CHECK
SEQUENCE
Start
Start (WRITE completed)
WRITE 40H or 10H
SR3 = 0?
NO
VPP Error 4, 5
NO
BYTE/WORD WRITE Error5
YES
SR4 = 0?
VPP = 5V
YES
WRITE Word or Byte
Address/Data
WRITE Successful
STATUS REGISTER
READ
SR7 = 1?
NO
YES
Complete Status2
Check (optional)
WRITE Complete 3
NOTE: 1. Sequence may be repeated for additional BYTE or WORD WRITEs.
2. Complete status check is not required. However, if SR3 = 1, further WRITEs are inhibited until the status register is
cleared.
3. Device will be in status register read mode. To return to the array read mode, the FFH command must be issued.
4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE
or ERASE operations are allowed by the CEL.
5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
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SELF-TIMED BLOCK ERASE SEQUENCE1
COMPLETE BLOCK ERASE
STATUS-CHECK SEQUENCE
Start
Start (ERASE completed)
WRITE 20H
SR3 = 0?
NO
VPP Error 5, 6
YES
Command Sequence Error6
NO
BLOCK ERASE Error6
YES
VPP = 5V
SR4, 5 = 1?
NO
WRITE D0H,
Block Address
SR5 = 0?
YES
ERASE
Busy
STATUS REGISTER
READ
ERASE Successful
NO
NO
SR7 = 1?
YES
Complete Status 2
Check (optional)
Suspend ERASE?
YES
Suspend 4
Sequence
ERASE Resumed
ERASE Complete 3
NOTE: 1. Sequence may be repeated to erase additional blocks.
2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register is
cleared.
3. To return to the array read mode, the FFH command must be issued.
4. Refer to the ERASE SUSPEND flowchart for more information.
5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE
or ERASE operations are allowed by the CEL.
6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
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ERASE SUSPEND/RESUME SEQUENCE
Start (ERASE in progress)
WRITE B0H
(ERASE SUSPEND)
VPP = 5V
STATUS REGISTER
READ
SR7 = 1?
NO
YES
SR6 = 1?
NO
YES
ERASE Completed
WRITE FFH
(READ ARRAY)
Done
Reading?
NO
YES
WRITE D0H
(ERASE RESUME)
Resume ERASE
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ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**VCC, input and I/O pins may transition to -2V for
<20ns and VCC + 2V for <20ns.
†Voltage may pulse to -2V for <20ns and 14V for <20ns.
Voltage on VCC Supply
Relative to VSS ................................ -0.5V to +6V**
Input Voltage Relative to VSS ................ -0.5V to +6V**
VPP Voltage Relative to VSS ............... -0.5V to +12.6V†
RP# or A9 Pin Voltage
Relative to VSS ............................ -0.5V to +12.6V†
Temperature Under Bias ...................... -40°C to +85°C
Storage Temperature (plastic) ............ -55°C to +125°C
Power Dissipation ................................................... 1W
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC READ
OPERATING CONDITIONS
Commercial Temperature (0°C ≤ TA ≤ +70°C) and Extended Temperature (-40°C ≤ TA ≤ +85°C)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
5V Supply Voltage
VCC
4.5
5.5
V
1
Input High (Logic 1) Voltage, all inputs
VIH
2
VCC + 0.5
V
1
Input Low (Logic 0) Voltage, all inputs
VIL
-0.5
0.8
V
1
Device Identification Voltage, A9
VID
11.4
12.6
V
1
VPP Supply Voltage
VPP
-0.5
12.6
V
1
DC OPERATING CHARACTERISTICS
Commercial Temperature (0°C ≤ TA ≤ +70°C) and Extended Temperature (-40°C ≤ TA ≤ +85°C)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
OUTPUT VOLTAGE LEVELS (TTL)
Output High Voltage (IOH = -2.5mA)
Output Low Voltage (IOL = 5.8mA)
VOH1
2.4
–
UNITS NOTES
V
VOL
–
0.45
V
OUTPUT VOLTAGE LEVELS (CMOS)
Output High Voltage (IOH = -100µA)
VOH2
VCC - 0.4
–
V
IL
-1
1
µA
INPUT LEAKAGE CURRENT: A9 INPUT
(11.4V ≤ A9 ≤ 12.6 = VID)
IID
–
500
µA
INPUT LEAKAGE CURRENT: RP# INPUT
(11.4V ≤ RP# ≤ 12.6 = VHH)
IHH
–
500
µA
OUTPUT LEAKAGE CURRENT
(DOUT is disabled; 0V ≤ VOUT ≤ VCC)
IOZ
-10
10
µA
1
INPUT LEAKAGE CURRENT
Any input (0V ≤ VIN ≤ VCC);
All other pins not under test = 0V
1
NOTE: 1. All voltages referenced to VSS.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
CAPACITANCE
(TA = +25°C; f = 1 MHz)
PARAMETER/CONDITION
SYMBOL
MAX
UNITS
Input Capacitance
CI
8
pF
Output Capacitance
CO
12
pF
NOTES
READ AND STANDBY CURRENT DRAIN
Commercial Temperature (0°C ≤ TA ≤ +70°C) and Extended Temperature (-40°C ≤ TA ≤ +85°C)
PARAMETER/CONDITION
SYMBOL
MAX
UNITS
NOTES
ICC1
55
mA
1, 2
ICC2
50
mA
1, 2
ICC3
55
mA
1, 2
READ CURRENT: BYTE-WIDE, CMOS INPUT LEVELS
(CE# ≤ 0.2V; OE# ≥ VCC - 0.2V; f = 10 MHz; Other inputs ≤ 0.2V
or ≥ VCC - 0.2V; RP# = VCC - 0.2V)
ICC4
50
mA
1, 2
STANDBY CURRENT: TTL INPUT LEVELS
VCC power supply standby current
(CE# = RP# = VIH; Other inputs = VIL or VIH)
ICC5
2
mA
STANDBY CURRENT: CMOS INPUT LEVELS
VCC power supply standby current
(CE# = RP# = VCC - 0.2V)
ICC6
130
µA
DEEP POWER-DOWN CURRENT: VCC SUPPLY (RP# = VSS ±0.2V)
ICC8
20
µA
STANDBY OR READ CURRENT: VPP SUPPLY (VPP ≤ 5.5V)
IPP1
±15
µA
DEEP POWER-DOWN CURRENT: VPP SUPPLY (RP# = VSS ±0.2V)
IPP2
5
µA
READ CURRENT: WORD-WIDE, TTL INPUT LEVELS
(CE# = VIL; OE# = VIH; f = 10 MHz; Other inputs = VIL or VIH; RP# = VIH)
READ CURRENT: WORD-WIDE, CMOS INPUT LEVELS
(CE# ≤ 0.2V; OE# ≥ VCC - 0.2V; f = 10 MHz; Other inputs ≤ 0.2V
or ≥ VCC - 0.2V; RP# ≥ VCC - 0.2V)
READ CURRENT: BYTE-WIDE, TTL INPUT LEVELS
(CE# = VIL; OE# = VIH; f = 10 MHz; Other inputs = VIL or VIH; RP# = VIH)
NOTE: 1. ICC is dependent on cycle rates.
2. ICC is dependent on output loading. Specified values are obtained with the outputs open.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
READ TIMING PARAMETERS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
TEST CONDITION 1
Commercial Temperature (0°C ≤ TA ≤ +70°C) and Extended Temperature (-40°C ≤ TA ≤ +85°C); VCC = +5V ±10%
AC CHARACTERISTICS
PARAMETER
READ cycle time
Access time from CE#
Access time from OE#
Access time from address
RP# HIGH to output valid delay
OE# or CE# HIGH to output in High-Z
Output hold time from OE#, CE# or address change
RP# LOW pulse width
SYMBOL
tRC
tACE
tAOE
tAA
tRWH
tOD
tOH
tRP
MIN
70
-6
MAX
MIN
80
70
35
70
500
20
0
60
-8
MAX
80
40
80
500
20
0
60
-8 ET
MIN MAX UNITS NOTES
80
ns
80
ns
1
40
ns
1
80
ns
500
ns
20
ns
0
ns
60
ns
TEST CONDITION 2
(0°C ≤ TA ≤ +70°C; VCC = +5V ±5%)
AC CHARACTERISTICS
PARAMETER
READ cycle time
Access time from CE#
Access time from OE#
Access time from address
RP# HIGH to output valid delay
OE# or CE# HIGH to output in High-Z
Output hold time from OE#, CE# or address change
RP# LOW pulse width
-6
SYMBOL
tRC
tACE
tAOE
tAA
tRWH
tOD
tOH
tRP
MIN
60
MAX
60
30
60
500
15
0
60
UNITS NOTES
ns
ns
1
ns
1
ns
ns
ns
ns
ns
NOTE: 1. OE# may be delayed by tACE minus tAOE after CE# falls before tACE is affected.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
AC TEST CONDITION 1
AC TEST CONDITION 2
Input pulse levels ............................................... 0.4V to 2.4V
Input rise and fall times ................................................ <10ns
Input timing reference level ............................... 0.8V and 2V
Output timing reference level ........................... 0.8V and 2V
Output load ................................. 1 TTL gate and CL = 100pF
,,
Input pulse levels ..................................................... 0V to 3V
Input rise and fall times ................................................ <10ns
Input timing reference level ........................................... 1.5V
Output timing reference level ....................................... 1.5V
Output load ................................... 1 TTL gate and CL = 50pF
,
,,,
WORD-WIDE READ CYCLE1, 2
VIH
A0-A16/(A17)
VALID ADDRESS
VIL
tRC
tAA
VIH
CE#
VIL
tACE
VIH
OE#
VIL
VIH
WE#
,,
,,
,
VIL
tOD
tAOE
tOH
VIH
DQ0-DQ15
VALID DATA
VIL
tRWH
VIH
RP#
VIL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
Commercial Temperature (0°C ≤ TA ≤ +70°C)
Extended Temperature (-40°C ≤ TA ≤ +85°C)
-6
SYMBOL
tRC3
MIN
-8
MAX
MAX
SYMBOL
tAA4
MIN
-8
MAX
60
MIN
70
80
80
tACE4
60
35
–
40
–
40
ns
ns
tOD3
30
70
–
80
–
80
ns
ns
tOH3
0
0
tOH4
0
–
tAOE4
tAA3
NOTE: 1.
2.
3.
4.
80
–
-6
UNITS
tACE3
tAOE3
80
–
-8 ET
MIN
MAX
ns
ns
ns
tRC4
70
60
MIN
tRWH3
tRWH4
tOD4
MAX
–
-8 ET
MIN
MAX
–
UNITS
ns
500
500
500
–
500
–
ns
ns
20
15
20
–
20
–
0
ns
ns
ns
–
ns
BYTE# = HIGH (MT28F200B5 only).
Applies to MT28F200B5 only.
Measurements tested under AC Test Condition 1, VCC = 5V ±10%.
Measurements tested under AC Test Condition 2, VCC = 5V ±5%.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
,
,,,,
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
,,,
BYTE-WIDE READ CYCLE1
VIH
1
(A - 1)-A16/(A17)
VALID ADDRESS
VIL
tRC
tAA
VIH
CE#
VIL
tACE
VIH
OE#
VIL
VIH
WE#
VIL
tOD
,
tAOE
tOH
VIH
DQ0-DQ7
DQ8-DQ142
VALID DATA
VIL
VIH
HIGH-Z
VIL
,,
tRWH
VIH
RP#
VIL
,
DON’T CARE
UNDEFINED
TIMING PARAMETERS
Commercial Temperature (0°C ≤ TA ≤ +70°C)
Extended Temperature (-40°C ≤ TA ≤ +85°C)
-6
SYMBOL
tRC3
tRC4
tACE3
tACE4
tAOE3
tAOE4
tAA3
NOTE: 1.
2.
3.
4.
MIN
-8
MAX
70
60
MIN
MAX
80
–
-8 ET
MIN
MAX
80
–
-6
UNITS
SYMBOL
ns
ns
tAA4
MIN
tRWH3
70
60
35
80
–
40
80
–
40
ns
ns
ns
tRWH4
30
70
–
80
–
80
ns
ns
tOH3
tOD3
tOD4
0
0
tOH4
-8
MAX
MIN
MAX
-8 ET
MIN
MAX
UNITS
60
500
500
–
500
–
–
500
–
ns
ns
ns
20
15
20
–
20
–
ns
ns
0
–
0
–
ns
ns
BYTE# = LOW (MT28F200B5 only).
Applies to MT28F200B5 only.
Measurements tested under AC Test Condition 1, VCC = 5V ±10%.
Measurements tested under AC Test Condition 2, VCC = 5V ±5%.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
RECOMMENDED DC WRITE/ERASE CONDITIONS1
Commercial Temperature (0°C ≤ TA ≤ +70°C) and Extended Temperature (-40°C ≤ TA ≤ +85°C); VCC = +5V ±10%
PARAMETER/CONDITION
MIN
MAX
VPP WRITE/ERASE lockout voltage
SYMBOL
VPPLK
–
1.5
UNITS NOTES
V
2
VPP voltage during WRITE/ERASE operation
VPPH1
4.5
5.5
V
3
VPP voltage during WRITE/ERASE operation
VPPH2
11.4
12.6
V
4
Boot block unlock voltage
VHH
11.4
12.6
V
VCC WRITE/ERASE lockout voltage
VLKO
2
–
V
WRITE/ERASE CURRENT DRAIN
Commercial Temperature (0°C ≤ TA ≤ +70°C) and Extended Temperature (-40°C ≤ TA ≤ +85°C); VCC = +5V ±10%
PARAMETER/CONDITION
SYMBOL
MIN
ICC9
25
mA
5
WORD WRITE CURRENT: VPP SUPPLY
IPP4
20
mA
5
BYTE WRITE CURRENT: VCC SUPPLY
ICC10
25
mA
6
BYTE WRITE CURRENT: VPP SUPPLY
IPP5
15
mA
6
ERASE CURRENT: VCC SUPPLY
ICC11
30
mA
WORD WRITE CURRENT: VCC SUPPLY
UNITS NOTES
ERASE CURRENT: VPP SUPPLY
IPP6
40
mA
ERASE SUSPEND CURRENT: VCC SUPPLY
(ERASE suspended)
ICC12
10
mA
ERASE SUSPEND CURRENT: VPP SUPPLY
(ERASE suspended)
IPP7
200
µA
7
NOTE: 1. WRITE operations are tested at VCC/VPP voltages equal to or less than the previous ERASE, and READ operations are
tested at VCC voltages equal to or less than the previous WRITE.
2. Absolute WRITE/ERASE protection when VPP ≤ VPPLK.
3. When 5V VCC and VPP are used, VCC cannot exceed VPP by more than 500mV during WRITE and ERASE operations.
4. For SmartVoltage-compatible production programming, 12V VPP is supported for a maximum of 100 cycles and may
be connected for up to 100 cummulative hours.
5. Applies to MT28F200B5 only.
6. Applies to MT28F002B5 and MT28F200B5 with BYTE = LOW.
7. Parameter is specified when device is not accessed. Actual current draw will be ICC12 (5V VCC) plus read current if a
READ is executed while the device is in erase suspend mode.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
TEST CONDITION 1
Commercial Temperature (0°C ≤ TA ≤ +70°C) and Extended Temperature (-40°C ≤ TA ≤ +85°C); VCC = +5V ±10%
AC CHARACTERISTICS
PARAMETER
WRITE cycle time
WE# HIGH pulse width
CE# HIGH pulse width
CE# pulse width
WE# pulse width
-6
SYMBOL
tWC
tWPH
tCPH
tCP
tWP
MIN
70
20
20
50
50
MAX
-8/-8 ET
MIN
MAX
80
30
30
50
50
UNITS
ns
ns
ns
ns
ns
NOTES
UNITS
ns
ns
ns
ns
ns
NOTES
TEST CONDITION 2
(0°C ≤ TA ≤ +70°C; VCC = +5V ±5%)
AC CHARACTERISTICS
PARAMETER
WRITE cycle time
WE# HIGH pulse width
CE# HIGH pulse width
CE# pulse width
WE# pulse width
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
-6
SYMBOL
tWC
tWPH
tCPH
tCP
tWP
24
MIN
60
20
20
50
50
MAX
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS: WE#-CONTROLLED WRITES
Commercial Temperature (0°C ≤ TA ≤ +70°C) and Extended Temperature (-40°C ≤ TA ≤ +85°C); VCC = +5V ±10% or
+5V ±5%
AC CHARACTERISTICS
PARAMETER
Address setup time to WE# HIGH
Address hold time from WE# HIGH
Data setup time to WE# HIGH
Data hold time from WE# HIGH
CE# setup time to WE# LOW
CE# hold time from WE# HIGH
VPP setup time to WE# HIGH
RP# HIGH to WE# LOW delay
RP# at VHH or WP# HIGH setup time to WE# HIGH
WRITE duration (WORD or BYTE WRITE)
Boot BLOCK ERASE duration
Parameter BLOCK ERASE duration
Main BLOCK ERASE duration
WE# HIGH to busy status (SR7 = 0)
VPP hold time from status data valid
RP# at VHH or WP# HIGH hold time from status data valid
Boot block relock delay time
NOTE: 1.
2.
3.
4.
5.
SYMBOL
tAS
tAH
tDS
tDH
tCS
tCH
tVPS1
tRS
tRHS
tWED1
tWED2
tWED3
tWED4
tWB
tVPH
tRHH
tREL
-6/-8/-8 ET
MIN
MAX
50
0
50
0
0
0
200
500
100
6
300
300
600
200
0
0
100
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ms
ms
ns
ns
ns
ns
NOTES
1
2
3
2, 3
3
3
4
3
2
5
Measured with VPP = VPPH1 = 5V.
RP# should be held at VHH or WP# held HIGH until boot block WRITE or ERASE is complete.
WRITE/ERASE times are measured to valid status register data (SR7 = 1).
Polling status register before tWB is met may falsely indicate WRITE or ERASE completion.
tREL is required to relock boot block after WRITE or ERASE to boot block.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS: CE#-CONTROLLED WRITES
Commercial Temperature (0°C ≤ TA ≤ +70°C) and Extended Temperature (-40°C ≤ TA ≤ +85°C); VCC = +5V ±10% or
+5V ±5%
AC CHARACTERISTICS
PARAMETER
Address setup time to CE# HIGH
Address hold time from CE# HIGH
Data setup time to CE# HIGH
Data hold time from CE# HIGH
WE# setup time to CE# LOW
WE# hold time from CE# HIGH
VPP setup time to CE# HIGH
RP# HIGH to CE# LOW delay
RP# at VHH or WP# HIGH setup time to CE# HIGH
WRITE duration (WORD or BYTE WRITE)
Boot BLOCK ERASE duration
Parameter BLOCK ERASE duration
Main BLOCK ERASE duration
CE# HIGH to busy status (SR7 = 0)
VPP hold time from status data valid
RP# at VHH or WP# HIGH hold time from status data valid
Boot block relock delay time
SYMBOL
tAS
tAH
tDS
tDH
tWS
tWH
tVPS1
tRS
tRHS
tWED1
tWED2
tWED3
tWED4
tWB
tVPH
tRHH
tREL
-6/-8/-8 ET
MIN
MAX
50
0
50
0
0
0
200
500
100
6
300
300
600
200
0
0
100
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ms
ms
ns
ns
ns
ns
NOTES
1
2
3
2, 3
3
3
4
3
2
5
WORD/BYTE WRITE AND ERASE DURATION CHARACTERISTICS
PARAMETER
TYP MAX UNITS NOTES
Boot/parameter BLOCK ERASE time
0.5
7
s
6
Main BLOCK ERASE time
1.5
14
s
6
Main BLOCK WRITE time (byte mode)
1
–
s
6, 7, 8
Main BLOCK WRITE time (word mode)
1
–
s
6, 7, 8
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
Measured with VPP = VPPH1 = 5V.
RP# should be held at VHH or WP# held HIGH until boot block WRITE or ERASE is complete.
WRITE/ERASE times are measured to valid status register data (SR7 = 1).
Polling status register before tWB is met may falsely indicate WRITE or ERASE completion.
tREL is required to relock boot block after WRITE or ERASE to boot block.
Typical values measured at TA = +25°C.
Assumes no system overhead.
Typical WRITE times use checkerboard data pattern.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
,
,,
WRITE/ERASE CYCLE
WE#-CONTROLLED WRITE/ERASE
VIH
A0-A16/(A17)
VIL
Note 1
tAS
AIN
tAS
tAH
VIH
CE#
VIL
tCS
tCH
VIH
OE#
VIL
,
,
,
,
,
,
,
,
,, ,, , , ,
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
tAH
tWC
tWP
tWED1/2/3/4
tWPH
VIH
WE#
DQ0-DQ7/
DQ0-DQ15 2
tWB
VIL
VIH
VIL
tDH
tDH
tDS
tDS
CMD
in
Status
(SR7=0)
CMD/
Data-in
tRS
tRHS
Status
(SR7=1)
tRHH
CMD
in
,
,
,
,
,,,,,,,,,,,,,,,,,,
,
,,
[Unlock boot block]
VHH
VIH
RP#
3
VIL
[Unlock boot block]
VIH
WP#
3
VIL
tVPH
tVPS1
VPPH1
VPPLK
VPP
[5V VPP]
VIL
WRITE SETUP or
ERASE SETUP input
WRITE or ERASE (block)
address asserted, and
WRITE data or ERASE
CONFIRM issued
WRITE or ERASE
executed, status register
checked for completion
Command for next
operation issued
DON’T CARE
TIMING PARAMETERS
Commercial Temperature (0°C ≤ TA ≤ +70°C)
Extended Temperature (-40°C ≤ TA ≤ +85°C)
-6
SYMBOL
tWC4
MIN
MAX
-8/-8 ET
MIN MAX
-6
UNITS
MIN
0
200
0
200
ns
ns
500
100
6
500
100
6
ns
ns
µs
300
300
300
300
ms
ms
600
200
0
ms
ns
ns
0
ns
70
60
80
–
ns
ns
tCH
20
20
50
30
–
50
ns
ns
ns
tRS
50
50
–
50
ns
ns
tWED2
0
50
0
ns
ns
ns
tWED4
tDH
0
50
0
tVPH
600
200
0
tCS
0
0
ns
tRHH
0
tWC5
tWPH4
tWPH5
tWP4
tWP5
tAS
tAH
tDS
tVPS1
tRHS
tWED1
tWED3
tWB
MAX
-8/-8 ET
MIN MAX
SYMBOL
UNITS
NOTE: 1. Address inputs are “Don’t Care” but must be held stable.
2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit (MT28F200B5
only).
3. Either RP# at VHH or WP# HIGH unlocks the boot block.
4. Measurements tested under AC Test Condition 1, VCC = 5V ±10%.
5. Measurements tested under AC Test Condition 2, VCC = 5V ±5%.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
,,
WRITE/ERASE CYCLE
CE#-CONTROLLED WRITE/ERASE
VIH
A0-A16/(A17)
VIL
Note 1
tAS
AIN
tAS
tAH
tAH
VIH
WE#
VIL
tWS
tWH
VIH
OE#
VIL
,
,
,
,
,
,
,
,
,
,, ,, , ,
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
tWC
tCP
tWED1/2/3/4
tCPH
VIH
CE#
DQ0-DQ7/
DQ0-DQ15 2
VIL
VIH
VIL
tWB
tDH
tDS
tDH
tDS
CMD
in
Status
(SR7=0)
CMD/
Data-in
tRS
tRHS
Status
(SR7=1)
tRHH
CMD
in
,
,
,
,
,
,
,
,
,, ,,,,,,, ,, ,,,
,
,
[Unlock boot block]
VHH
VIH
RP#
3
VIL
[Unlock boot block]
VIH
WP#
3
VIL
t VPH
tVPS1
VPPH1
VPPLK
VPP
[5V VPP]
VIL
WRITE SETUP or
ERASE SETUP input
WRITE or ERASE (block)
address asserted, and
WRITE data or ERASE
CONFIRM issued
WRITE or ERASE
executed, status register
checked for completion
Command for next
operation issued
DON’T CARE
TIMING PARAMETERS
Commercial Temperature (0°C ≤ TA ≤ +70°C)
Extended Temperature (-40°C ≤ TA ≤ +85°C)
-6
SYMBOL
tWC4
MIN
-8/-8 ET
MAX
MIN
MAX
-6
UNITS
-8/-8 ET
SYMBOL
MIN
MAX
MIN
0
200
500
0
200
500
MAX
UNITS
ns
ns
ns
100
6
100
6
ns
µs
300
300
600
300
300
600
ms
ms
ms
70
60
20
80
–
30
ns
ns
ns
tWH
20
50
–
50
ns
ns
tRHS
50
50
0
–
50
0
ns
ns
ns
tWED2
50
0
ns
ns
tWB
tDH
50
0
tVPH
200
0
200
0
ns
ns
tWS
0
0
ns
tRHH
0
0
ns
tWC5
tCPH4
tCPH5
tCP4
tCP5
tAS
tAH
tDS
tVPS1
tRS
tWED1
tWED3
tWED4
NOTE: 1. Address inputs are “Don’t Care” but must be held stable.
2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit (MT28F200B5
only).
3. Either RP# at VHH or WP# HIGH unlocks the boot block.
4. Measurements tested under AC Test Condition 1, VCC = 5V ±10%.
5. Measurements tested under AC Test Condition 2, VCC = 5V ±5%.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
40-PIN PLASTIC TSOP I
(10mm x 20mm)
.795 (20.19)
.780 (19.81)
.727 (18.47)
.0197 (0.50)
TYP
.010 (0.25)
.721 (18.31)
1
40
PIN #1 INDEX
.397 (10.08)
.391 (9.93)
.010 (0.25)
.006 (0.15)
20
21
.010 (0.25)
.004 (0.10)
.007 (0.18)
.005 (0.13)
GAGE
PLANE
.047 (1.20)
MAX
SEE DETAIL A
.008 (0.20)
.002 (0.05)
.024 (0.60)
.016 (0.40)
DETAIL A
.0315 (0.80)
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
44-PIN PLASTIC SOP
(600 mil)
1.113 (28.27)
1.107 (28.12)
.050 (1.27)
TYP
.007 (0.18)
.020 (0.50)
.015 (0.38)
.005 (0.13)
.643 (16.34)
.620 (15.74)
.499 (12.68)
.493 (12.52)
PIN #1 INDEX
.030 (0.76)
SEE DETAIL A
.004 (0.10)
.016 (0.40)
.010 (0.25)
.106 (2.70) MAX
GAGE PLANE
.010 (0.25)
DETAIL A
.0315 (0.80)
(ROTATED 90° CW)
.066 (1.72)
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
48-PIN PLASTIC TSOP I
(12mm x 20mm)
.795 (20.19)
.780 (19.81)
.727 (18.47)
.0197 (0.50)
TYP
.010 (0.25)
.721 (18.31)
1
48
PIN #1 INDEX
.475 (12.07)
.469 (11.91)
.010 (0.25)
.006 (0.15)
25
24
.010 (0.25)
.004 (0.10)
.007 (0.18)
.005 (0.12)
SEE DETAIL A
GAGE
PLANE
.047 (1.20) MAX
.008 (0.20)
.002 (0.05)
.024 (0.60)
.016 (0.40)
DETAIL A
.0315 (0.80)
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.