ADVANCE‡ 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY FLASH MEMORY MT28F642D18 MT28F642D20 Low Voltage, Extended Temperature 0.18µm Process Technology FEATURES PIN ASSIGNMENT 59-Ball FBGA • Single device supports asynchronous, page, and burst operations • Flexible dual-bank architecture Support for true concurrent operation with zero latency Read bank a during program bank b and vice versa Read bank a during erase bank b and vice versa • Basic configuration: One hundred and thirty-five erasable blocks Bank a (16Mb for data storage) Bank b (48Mb for program storage) • VCC, VCCQ, VPP voltages 1.70V (MIN), 1.90V (MAX) VCC, VCCQ (MT28F642D18 only) 1.80V (MIN), 2.20V (MAX) VCC, and 2.25V (MAX) VCCQ (MT28F642D20 only) 1.80V (TYP) VPP (in-system PROGRAM/ERASE) 12V ±5% (HV) VPP tolerant (factory programming compatibility) • Random access time: 70ns @ 1.80V VCC1 • Burst Mode read access MAX clock rate: 54 MHz (tCLK = 18.5ns) Burst latency: 70ns @ 1.80V VCC and 54 MHz tACLK: 15ns @ 1.80V VCC and 54 MHz • Page Mode read access1 Four-/eight-word page Interpage read access: 70ns @ 1.80V Intrapage read access: 30ns @ 1.80V • Low power consumption (VCC = 2.20V) Asynchronous Read < 15mA Interpage Read < 15mA Intrapage Read < 5mA Continuous Burst Read < 10mA WRITE < 55mA (MAX) ERASE < 45mA (MAX) Standby < 50µA (MAX) Automatic power save (APS) feature Deep power-down < 25µA (MAX) • Enhanced write and erase suspend options • Accelerated programming algorithm (APA) insystem and in-factory • Dual 64-bit chip protection registers for security purposes 1 2 3 4 5 6 7 8 A A11 A8 VSS VCC VPP A18 A6 A4 B A12 A9 A20 CLK RST# A17 A5 A3 C A13 A10 A21 ADV# WE# A19 A7 A2 D A15 A14 WAIT# A16 DQ12 WP# E VCCQ DQ15 DQ6 DQ4 DQ2 DQ1 CE# A0 F VSS DQ14 DQ13 DQ11 DQ10 DQ9 DQ0 OE# G DQ7 VSSQ DQ5 VCC DQ3 VCCQ DQ8 VSSQ A1 Top View (Ball Down) NOTE: See page 7 for Ball Description Table. See page 50 for mechanical drawing. • Cross-compatible command support Extended command set Common flash interface • PROGRAM/ERASE cycle 100,000 WRITE/ERASE cycles per block OPTIONS MARKING • Timing 80ns access 70ns access • Frequency 40 MHz 54 MHz • Boot Block Configuration Top Bottom • Package 59-ball FBGA (8 x 7 ball grid) • Operating Temperature Range Extended (-40ºC to +85ºC) -80 -70 4 5 T B FN ET Part Number Example: MT28F642D20FN-804 TET NOTE: 1. Data based on MT28F642D20 device. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 1 ©2002, Micron Technology, Inc. ‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY ARCHITECTURE AND MEMORY ORGANIZATION GENERAL DESCRIPTION The MT28F642D20 and MT28F642D18 are highperformance, high-density, nonvolatile memory solutions that can significantly improve system performance. This new architecture features a twomemory-bank configuration that supports dual-bank operation with no latency. A high-performance bus interface allows a fast burst or page mode data transfer; a conventional asynchronous bus interface is provided as well. The devices allow soft protection for blocks, as readonly, by configuring soft protection registers with dedicated command sequences. For security purposes, two 64-bit chip protection registers are provided. The embedded WORD WRITE and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). Two on-chip status registers, one for each of the two memory partitions, can be used to monitor the WSM status and to determine the progress of the program/erase task. The erase/program suspend functionality allows compatibility with existing EEPROM emulation software packages. These devices are manufactured using 0.18µm process technology. Please refer to the Micron Web site (www.micron.com/ flash) for the latest data sheet. The Flash devices contain two separate banks of memory (bank a and bank b) for simultaneous READ and WRITE operations, which are available in the following bank segmentation configurations: • Bank a comprises one-fourth of the memory and contains 8 x 4K-word parameter blocks and 31 x 32K-word blocks. • Bank b represents three-fourths of the memory, is equally sectored, and contains 96 x 32K-word blocks. Figures 2 and 3 show the bottom and top memory organizations. DEVICE MARKING Due to the size of the package, Micron’s standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross referenced to the Micron part numbers in Table 1. Table 1 Cross Reference for Abbreviated Device Marks PART NUMBER MT28F642D20FN-705 TET MT28F642D20FN-705 BET MT28F642D20FN-804 TET MT28F642D20FN-804 BET MT28F642D18FN-705 TET MT28F642D18FN-705 BET MT28F642D18FN-804 TET MT28F642D18FN-804 BET 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 PRODUCT MARKING SAMPLE MARKING MECHANICAL SAMPLE MARKING FW906 FW905 FW907 FW908 FW909 FW910 FW911 FW912 FX906 FX905 FX907 FX908 FX909 FX910 FX911 FX912 FY906 FY905 FY907 FY908 FY909 FY910 FY911 FY912 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY PART NUMBERING INFORMATION Micron’s low-power devices are available with several different combinations of features (see Figure 1). Valid combinations of features and their corresponding part numbers are listed in Table 2. Figure 1 Part Number Chart MT 28F 642 D20 FN-80 4 B ET Micron Technology Operating Temperature Range ET = Extended (-40ºC to +85ºC) Flash Family Boot Block Starting Address 28F = Dual-Supply Flash B = Bottom boot T = Top boot Density/Organization/Banks 642 = 64Mb (4,096K x 16) bank a = 1/4; bank b = 3/4 Burst Mode Frequency 4 = 40 MHz 5 = 54 MHz Read Mode Operation D = Asynchronous/Page/Burst Read Access Time Operating Voltage Range -70 = 70ns -80 = 80ns 18 = 1.70V–1.90V 20 = 1.80V–2.20V VCC 20 = 1.80V–2.25V VCCQ Package Code FN = 59-ball FBGA (8 x 7 grid) Table 2 Valid Part Number Combinations1 PART NUMBER MT28F642D20FN-705 TET MT28F642D20FN-705 BET MT28F642D20FN-804 TET MT28F642D20FN-804 BET MT28F642D18FN-705 TET MT28F642D18FN-705 BET MT28F642D18FN-804 TET MT28F642D18FN-804 BET ACCESS TIME (ns) BOOT BLOCK STARTING ADDRESS BURST FREQUENCY (MHz) OPERATING TEMPERATURE RANGE 70 70 80 80 70 70 80 80 Top Bottom Top Bottom Top Bottom Top Bottom 54 54 40 40 54 54 40 40 -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC NOTE: 1. For part number combinations not listed in this table, please contact your Micron representative. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY FUNCTIONAL BLOCK DIAGRAM PR Lock PR Lock Query Query/OTP OTP DQ0–DQ15 Manufacturer’s ID Data Input Buffer X DEC Bank 1 Blocks Y/Z DEC Y/Z Gating/Sensing Device ID Block Lock RCR Data Register ID Reg. RST# CE# WE# Status Reg. CSM OE# Program/ Erase Pump Voltage Generators WSM DQ0–DQ15 Output Multiplexer I/O Logic A0–A21 Output Buffer Address Input Buffer Address CNT WSM WAIT# ADV# Address Latch CLK 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 Address Multiplexer Y/Z DEC Y/Z Gating/Sensing X DEC Bank 2 Blocks BSM 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 2 Bottom Boot Block Device Block 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 Bank b = 48Mb Block Size Address Range (K-bytes/ (x16) K-words) 64/32 3F8000h–3FFFFFh 64/32 3F0000h–3F7FFFh 64/32 3E8000h–3EFFFFh 64/32 3E0000h–3E7FFFh 64/32 3D8000h–3DFFFFh 64/32 3D0000h–3D7FFFh 64/32 3C8000h–3CFFFFh 64/32 3C0000h–3C7FFFh 64/32 3B8000h–3BFFFFh 64/32 3B0000h–3B7FFFh 64/32 3A8000h–3AFFFFh 64/32 3A0000h–3A7FFFh 64/32 398000h–39FFFFh 64/32 390000h–397FFFh 64/32 388000h–38FFFFh 64/32 380000h–387FFFh 64/32 378000h–37FFFFh 64/32 370000h–377FFFh 64/32 368000h–36FFFFh 64/32 360000h–367FFFh 64/32 358000h–35FFFFh 64/32 350000h–357FFFh 64/32 348000h–34FFFFh 64/32 340000h–347FFFh 64/32 338000h–33FFFFh 64/32 330000h–337FFFh 64/32 328000h–32FFFFh 64/32 320000h–327FFFh 64/32 318000h–31FFFFh 64/32 310000h–317FFFh 64/32 308000h–30FFFFh 64/32 300000h–307FFFh 64/32 2F8000h–2FFFFFh 64/32 2F0000h–2F7FFFh 64/32 2E8000h–2EFFFFh 64/32 2E0000h–2E7FFFh 64/32 2D8000h–2DFFFFh 64/32 2D0000h–2D7FFFh 64/32 2C8000h–2CFFFFh 64/32 2C0000h–2C7FFFh 64/32 2B8000h–2BFFFFh 64/32 2B0000h–2B7FFFh 64/32 2A8000h–2AFFFFh 64/32 2A0000h–2A7FFFh 64/32 298000h–29FFFFh 64/32 290000h–297FFFh 64/32 288000h–28FFFFh 64/32 280000h–287FFFh 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 Block 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 Bank b = 48Mb Block Size Address Range (K-bytes/ (x16) K-words) 64/32 278000h–27FFFFh 64/32 270000h–277FFFh 64/32 268000h–26FFFFh 64/32 260000h–267FFFh 64/32 258000h–25FFFFh 64/32 250000h–257FFFh 64/32 248000h–24FFFFh 64/32 240000h–247FFFh 64/32 238000h–23FFFFh 64/32 230000h–237FFFh 64/32 228000h–22FFFFh 64/32 220000h–227FFFh 64/32 218000h–21FFFFh 64/32 210000h–217FFFh 64/32 208000h–20FFFFh 64/32 200000h–207FFFh 64/32 1F8000h–1FFFFFh 64/32 1F0000h–1F7FFFh 64/32 1E8000h–1EFFFFh 64/32 1E0000h–1E7FFFh 64/32 1D8000h–1DFFFFh 64/32 1D0000h–1D7FFFh 64/32 1C8000h–1CFFFFh 64/32 1C0000h–1C7FFFh 64/32 1B8000h–1BFFFFh 64/32 1B0000h–1B7FFFh 64/32 1A8000h–1AFFFFh 64/32 1A0000h–1A7FFFh 64/32 198000h–19FFFFh 64/32 190000h–197FFFh 64/32 188000h–18FFFFh 64/32 180000h–187FFFh 64/32 178000h–17FFFFh 64/32 170000h–177FFFh 64/32 168000h–16FFFFh 64/32 160000h–167FFFh 64/32 158000h–15FFFFh 64/32 150000h–157FFFh 64/32 148000h–14FFFFh 64/32 140000h–147FFFh 64/32 138000h–13FFFFh 64/32 130000h–137FFFh 64/32 128000h–12FFFFh 64/32 120000h–127FFFh 64/32 118000h–11FFFFh 64/32 110000h–117FFFh 64/32 108000h–10FFFFh 64/32 100000h–107FFFh 5 Block 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank a = 16Mb Block Size Address Range (K-bytes/ (x16) K-words) 64/32 0F8000h–0FFFFFh 64/32 0F0000h–0F7FFFh 64/32 0E8000h–0EFFFFh 64/32 0E0000h–0E7FFFh 64/32 0D8000h–0DFFFFh 64/32 0D0000h–0D7FFFh 64/32 0C8000h–0CFFFFh 64/32 0C0000h–0C7FFFh 64/32 0B8000h–0BFFFFh 64/32 0B0000h–0B7FFFh 64/32 0A8000h–0AFFFFh 64/32 0A0000h–0A7FFFh 64/32 098000h–09FFFFh 64/32 090000h–097FFFh 64/32 088000h–08FFFFh 64/32 080000h–087FFFh 64/32 078000h–07FFFFh 64/32 070000h–077FFFh 64/32 068000h–06FFFFh 64/32 060000h–067FFFh 64/32 058000h–05FFFFh 64/32 050000h–057FFFh 64/32 048000h–04FFFFh 64/32 040000h–047FFFh 64/32 038000h–03FFFFh 64/32 030000h–037FFFh 64/32 028000h–02FFFFh 64/32 020000h–027FFFh 64/32 018000h–01FFFFh 64/32 010000h–017FFFh 64/32 008000h–00FFFFh 8/4 007000h–007FFFh 8/4 006000h–006FFFh 8/4 005000h–005FFFh 8/4 004000h–004FFFh 8/4 003000h–003FFFh 8/4 002000h–002FFFh 8/4 001000h–001FFFh 8/4 000000h–00FFFh Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 3 Top Boot Block Device Block 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 Bank a = 16Mb Block Size Address Range (K-bytes/ (x16) K-words) 8/4 3FF000h–3FFFFFh 8/4 3FE000h–3FEFFFh 8/4 3FD000h–3FDFFFh 8/4 3FC000h–3FCFFFh 8/4 3FB000h–3FBFFFh 8/4 3FA000h–3FAFFFh 8/4 3F9000h–3F9FFFh 8/4 3F8000h–3F8FFFh 64/32 3F0000h–3F7FFFh 64/32 3E8000h–3EFFFFh 64/32 3E0000h–3E7FFFh 64/32 3D8000h–3DFFFFh 64/32 3D0000h–3D7FFFh 64/32 3C8000h–3CFFFFh 64/32 3C0000h–3C7FFFh 64/32 3B8000h–3BFFFFh 64/32 3B0000h–3B7FFFh 64/32 3A8000h–3AFFFFh 64/32 3A0000h–3A7FFFh 64/32 398000h–39FFFFh 64/32 390000h–397FFFh 64/32 388000h–38FFFFh 64/32 380000h–387FFFh 64/32 378000h–37FFFFh 64/32 370000h–377FFFh 64/32 368000h–36FFFFh 64/32 360000h–367FFFh 64/32 358000h–35FFFFh 64/32 350000h–357FFFh 64/32 348000h–34FFFFh 64/32 340000h–347FFFh 64/32 338000h–33FFFFh 64/32 330000h–337FFFh 64/32 328000h–32FFFFh 64/32 320000h–327FFFh 64/32 318000h–31FFFFh 64/32 310000h–317FFFh 64/32 308000h–30FFFFh 64/32 300000h–307FFFh 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 Block 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Bank b = 48Mb Block Size Address Range (K-bytes/ (x16) K-words) 64/32 2F8000h–2FFFFFh 64/32 2F0000h–2F7FFFh 64/32 2E8000h–2EFFFFh 64/32 2E0000h–2E7FFFh 64/32 2D8000h–2DFFFFh 64/32 2D0000h–2D7FFFh 64/32 2C8000h–2CFFFFh 64/32 2C0000h–2C7FFFh 64/32 2B8000h–2BFFFFh 64/32 2B0000h–2B7FFFh 64/32 2A8000h–2AFFFFh 64/32 2A0000h–2A7FFFh 64/32 298000h–29FFFFh 64/32 290000h–297FFFh 64/32 288000h–28FFFFh 64/32 280000h–287FFFh 64/32 278000h–27FFFFh 64/32 270000h–277FFFh 64/32 268000h–26FFFFh 64/32 260000h–267FFFh 64/32 258000h–25FFFFh 64/32 250000h–257FFFh 64/32 248000h–24FFFFh 64/32 240000h–247FFFh 64/32 238000h–23FFFFh 64/32 230000h–237FFFh 64/32 228000h–22FFFFh 64/32 220000h–227FFFh 64/32 218000h–21FFFFh 64/32 210000h–217FFFh 64/32 208000h–20FFFFh 64/32 200000h–207FFFh 64/32 1F8000h–1FFFFFh 64/32 1F0000h–1F7FFFh 64/32 1E8000h–1EFFFFh 64/32 1E0000h–1E7FFFh 64/32 1D8000h–1DFFFFh 64/32 1D0000h–1D7FFFh 64/32 1C8000h–1CFFFFh 64/32 1C0000h–1C7FFFh 64/32 1B8000h–1BFFFFh 64/32 1B0000h–1B7FFFh 64/32 1A8000h–1AFFFFh 64/32 1A0000h–1A7FFFh 64/32 198000h–19FFFFh 64/32 190000h–197FFFh 64/32 188000h–18FFFFh 64/32 180000h–187FFFh 6 Block 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bank b = 48Mb Block Size Address Range (K-bytes/ (x16) K-words) 64/32 178000h–17FFFFh 64/32 170000h–177FFFh 64/32 168000h–16FFFFh 64/32 160000h–167FFFh 64/32 158000h–15FFFFh 64/32 150000h–157FFFh 64/32 148000h–14FFFFh 64/32 140000h–147FFFh 64/32 138000h–13FFFFh 64/32 130000h–137FFFh 64/32 128000h–12FFFFh 64/32 120000h–127FFFh 64/32 118000h–11FFFFh 64/32 110000h–117FFFh 64/32 108000h–10FFFFh 64/32 100000h–107FFFh 64/32 0F8000h–0FFFFFh 64/32 0F0000h–0F7FFFh 64/32 0E8000h–0EFFFFh 64/32 0E0000h–0E7FFFh 64/32 0D8000h–0DFFFFh 64/32 0D0000h–0D7FFFh 64/32 0C8000h–0CFFFFh 64/32 0C0000h–0C7FFFh 64/32 0B8000h–0BFFFFh 64/32 0B0000h–0B7FFFh 64/32 0A8000h–0AFFFFh 64/32 0A0000h–0A7FFFh 64/32 098000h–09FFFFh 64/32 090000h–097FFFh 64/32 088000h–08FFFFh 64/32 080000h–087FFFh 64/32 078000h–07FFFFh 64/32 070000h–077FFFh 64/32 068000h–06FFFFh 64/32 060000h–067FFFh 64/32 058000h–05FFFFh 64/32 050000h–057FFFh 64/32 048000h–04FFFFh 64/32 040000h–047FFFh 64/32 038000h–03FFFFh 64/32 030000h–037FFFh 64/32 028000h–02FFFFh 64/32 020000h–027FFFh 64/32 018000h–01FFFFh 64/32 010000h–017FFFh 64/32 008000h–00FFFFh 64/32 000000h–007FFFh Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY BALL DESCRIPTIONS 59-BALL FBGA NUMBERS SYMBOL TYPE DESCRIPTION E8, D8, C8, B8, A8, B7, A7, C7, A2, B2, C2, A1, B1, C1, D2, D1, D4, B6, A6, C6, B3, C3 A0–A21 Input Address Inputs: Inputs for the addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. B4 CLK Input Clock: Synchronizes the Flash memory to the system operating frequency during synchronous burst mode READ operations. When configured for synchronous burst mode READs, address is latched on the first rising (or falling, depending upon the read configuration register setting) CLK edge when ADV# is active or upon a rising ADV# edge, whichever occurs first. CLK is ignored during asynchronous access READ and WRITE operations and during READ PAGE ACCESS operations.1 C4 ADV# Input Address Valid: Indicates that a valid address is present on the address inputs. Addresses are latched on the rising edge of ADV# during READ and WRITE operations. ADV# may be tied active during asynchronous READ and WRITE operations.1 A5 VPP Input Program/Erase Enable: [0.9V–2.20V or 11.4V–12.6V] Operates as input at logic levels to control complete device protection. Provides factory programming compatibility when driven to 11.4V–12.6V. E7 CE# Input Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. F8 OE# Input Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. C5 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command state machine (CSM) or to the memory array. B5 RST# Input Reset: When RST# is a logic LOW, the device is in reset mode, which drives the outputs to High-Z and resets the write state machine (WSM). When RST# is at logic HIGH, the device is in standard operation. When RST# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode. D6 WP# Input Write Protect: Controls the lock down function of the flexible locking feature. F7, E6, E5, G5, DQ0–DQ15 E4, G3, E3, G1, G7, F6, F5, F4, D5, F3, F2, E2 D3 WAIT# Input/ Output Data Inputs/Outputs: Inputs array data on the second CE# and WE# cycle during PROGRAM command. Inputs commands to the command user interface when CE# and WE# are active. DQ0–DQ15 output data when CE# and OE# are active. Output Wait: Provides data valid feedback during continuous burst read access. The signal is gated by OE# and CE#. This signal is always kept at a valid logic level. NOTE: 1. The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. The WAIT# signal can be ignored when operating in asynchronous or page mode, as it is always held at logic “1” or “0,” depending on the RCR8 setting (see Table 9). (continued on next page) 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY BALL DESCRIPTIONS (continued) 59-BALL FBGA NUMBERS SYMBOL TYPE DESCRIPTION A4, G4 VCC Supply Device Power Supply: [1.70V–1.90V (MT28F642D18) or 1.80V–2.20V (MT28F642D20)] Supplies power for device operation. E1, G6 VCCQ Supply I/O Power Supply: [1.70V–1.90V (MT28F642D18) or 1.80V–2.25V (MT28F642D20)] Supplies power for input/output buffers. G2, G8 V SS Q Supply I/O Ground. Do not float any ground ball. A3, F1 VSS Supply Do not float any ground ball. D7 – – 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 Contact ball is not physically present. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY COMMAND STATE MACHINE (CSM) Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external microprocessors and the internal write state machine (WSM). The available commands are listed in Table 3, their definitions are given in Table 4, and their descriptions in Table 5. Program and erase algorithms are automated by an on-chip WSM. Table 6 shows the CSM transition states. Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate algorithm. The algorithm generates the necessary timing signals to control the device internally and accomplish the requested operation. A command is valid only if the exact sequence of WRITEs is completed. After the WSM completes its task, the WSM status bit (SR7) is set to a logic HIGH level (1) (see Table 8), allowing the CSM to respond to the full command set again. needed, can be a WRITE or a READ depending upon the command. During a READ operation, control signals CE#, ADV#, and OE# must be at a logic LOW level (VIL), and WE# and RST# must be at logic HIGH (VIH). Table 7 illustrates the bus operations for all the modes: write, read, reset, standby, and output disable. When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a command code be entered into the CSM. For each of the memory partitions, an on-chip status register is available. These two registers enable the progress of various operations that take place on a memory bank to be monitored. Either of the two status registers is interrogated by entering a READ STATUS REGISTER command onto the CSM (cycle 1), specifying an address within the memory partition boundary, and reading the register data on I/Os DQ0–DQ7 (cycle 2). Status register bits SR0–SR7 correspond to DQ0–DQ7 (see Table 8). OPERATIONS Device operations are selected by entering a standard JEDEC 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/Os DQ0–DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control signals CE#, ADV#, and WE# must be at a logic LOW level (VIL), and OE# and RST# must be at logic HIGH (VIH). The second operation, when COMMAND DEFINITION Once a specific command code has been entered, the WSM executes an internal algorithm, generating the necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and data for each of the bus cycles. Table 3 Command State Machine Codes For Device Mode Selection COMMAND DQ0–DQ7 10h 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 CODE ON DEVICE MODE Accelerated programming algorithm (APA) 20h 40h 50h 60h 60h Block erase setup Program setup Clear status register Protection configuration setup Set read configuration register 70h 90h 98h B0h C0h Read status register Read protection configuration register Read query Program/erase suspend Protection register program/lock D0h D1h FFh Program/erase resume – erase confirm Check block erase confirm Read array 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY STATUS REGISTER The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored by toggling OE# and CE# and reading the resulting status code on I/Os DQ0–DQ7. The high-order I/Os (DQ8–DQ15) are set to 00h internally, so only the loworder I/Os (DQ0–DQ7) need to be interpreted. Address lines select the status register pertinent to the selected memory partition. Register data is updated and latched on the falling edge of ADV# or the rising (falling) edge of CLK when ADV# is LOW during synchronous burst mode, or on the falling edge of OE# or CE#, whichever occurs last. Latching the data prevents errors from occurring if the register input changes during status register monitoring. The status register provides a reading of the internal state of the WSM to the external microprocessor. During periods when the WSM is active, the status register can be polled to determine the WSM status. Table 8 defines the status register bits. After monitoring the status register during a PROGRAM/ERASE operation, the data appearing on DQ0–DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM. COMMAND STATE MACHINE OPERATIONS The CSM decodes instructions for the commands listed in Table 3. The 8-bit command code is input to the device on DQ0–DQ7 (see Table 3 for CSM codes and Table 4 for command definitions). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested. Table 4 Command Definitions FIRST BUS CYCLE COMMAND OPERATION ADDRESS1 DATA READ ARRAY WRITE WA FFh READ PROTECTION CONFIGURATION REGISTER WRITE IA 90h READ STATUS REGISTER WRITE BA 70h CLEAR STATUS REGISTER WRITE BA 50h READ QUERY WRITE QA 98h BLOCK ERASE SETUP WRITE BA 20h PROGRAM SETUP WRITE WA 40h ACCELERATED PROGRAMMING ALGORITHM (APA) WRITE WA 10h PROGRAM/ERASE SUSPEND WRITE BA B0h PROGRAM/ERASE RESUME – ERASE CONFIRM WRITE BA D0h LOCK BLOCK WRITE BA 60h UNLOCK BLOCK WRITE BA 60h LOCK DOWN BLOCK WRITE BA 60h CHECK BLOCK ERASE WRITE BA 20h PROTECTION REGISTER PROGRAM WRITE PA C0h PROTECTION REGISTER LOCK WRITE LPA C0h SET READ CONFIGURATION REGISTER WRITE RCD 60h NOTE: 1. WA: Word address of memory location to be written, or read IA: Identification code address BA: Address within the block ID: Identification code data SRD: Data read from the status register QA: Query code address QD: Query code data 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 WD: PA: PD: LPA: RCD: X: 10 SECOND BUS CYCLE OPERATION ADDRESS1 DATA READ READ IA X ID SRD READ WRITE WRITE WRITE QA BA WA WA QD D0h WD WD WRITE WRITE WRITE WRITE WRITE WRITE WRITE BA BA BA BA PA LPA RCD 01h D0h 2Fh D1h PD FFFDh 03h Data to be written at the location WA Protection register address Data to be written at the location PA Lock protection register address Data to be written in the read configuration register “Don’t Care” Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 5 Command Descriptions CODE DEVICE MODE BUS CYCLE DESCRIPTION 10h APA First Prepares the CSM for an ACCELERATED PROGRAM ALGORITHM (APA) command. 20h Erase Setup First Prepares the CSM for the ERASE command. If the next command is not a CHECK BLOCK ERASE or ERASE CONFIRM command, the command will be ignored, and the bank will go to the read status mode and wait for another command. 40h Program Setup First A two-cycle command: The first cycle prepares for a PROGRAM operation, and the second cycle latches addresses and data and initiates the WSM to execute the program algorithm. The Flash outputs status register data on the rising edge of ADV#, or on the rising clock edge when ADV# is LOW during synchronous burst mode, or on the falling edge of OE# or CE#, whichever occurs first. 50h Clear Status Register First The WSM can set the block lock status (SR1), VPP status (SR3), program status (SR4), and erase status (SR5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this command clears those bits to “0.” 60h Protection Configuration Setup First Prepares the CSM for changes to the block locking status. If the next command is not BLOCK UNLOCK, BLOCK LOCK, or BLOCK LOCK DOWN, the command will be ignored, and the device will go to the read status mode. Set Read Configuration Register First Puts the device into the set read configuration mode so that it will be possible to set the option bits related to burst read mode. 70h Read Status Register First Places the device into a read status register mode. Reading the device will output the contents of the status register for the addressed bank. The device will automatically enter this mode for the addressed bank after a PROGRAM or ERASE operation has been initiated. 90h Read Protection Configuration First Puts the device into the read protection configuration mode so that reading the device will output the manufacturer/device codes, block lock status, protection register, or protection register lock status. 98h Read Query First Puts the device into the read query mode so that reading the device will output common flash interface information. B0h Program Suspend First Issuing this command will suspend the currently executing PROGRAM/ERASE/CHECK BLOCK ERASE operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR2) or erase suspend (SR6) bit, and the WSM status bit (SR7) to a “1” (ready). The WSM will continue to idle in the suspend state, regardless of the state of all input control signals except RST#, which will immediately shut down the WSM and the remainder of the chip if RST# is driven to VIL. Erase Suspend Check Block Erase Suspend (continued on next page) 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 5 Command Descriptions (continued) CODE DEVICE MODE C0h D0h BUS CYCLE DESCRIPTION Program Device Protection Register First Writes a specific code into the device protection register. Lock Device Protection Register First Locks the device protection register; data can no longer be changed. Second If the previous command was an ERASE SETUP command, then the CSM will close the address and data latches, and it will begin erasing the block indicated on the address balls. During programming/erase, the device will respond only to the READ STATUS REGISTER, PROGRAM SUSPEND, or ERASE SUSPEND command. It will output status register data on the rising edge of ADV#, or on the rising clock edge when ADV# is LOW during synchronous burst mode, or on the falling edge of OE# or CE#, whichever occurs last. Erase Confirm Program/Erase/ Check Block Erase Resume First If a PROGRAM, ERASE or CHECK BLOCK ERASE operation was previously suspended, this command will resume the operation. FFh Read Array First During read array mode, array data will be output on the data bus. 01h Lock Block Second If the previous command was PROTECTION CONFIGURATION SETUP, the CSM will latch the address and lock the block indicated on the address bus. 03h Read Configuration Register Data Second If the previous command was SET READ CONFIGURATION REGISTER, the configuration bits presented on the address bus will be stored into the read configuration register. 2Fh Lock Down Second If the previous command was PROTECTION CONFIGURATION SETUP, the CSM will latch the address and lock down the block indicated on the address bus. D0h Unlock Block Second If the previous command was PROTECTION CONFIGURATION SETUP, the CSM will latch the address and unlock the block indicated on the address bus. If the block had been previously set to lock down, this operation will have no effect. D1h Check Block Erase Confirm Second If the previous command was ERASE SETUP, the CSM will close the address latches and check to see that the block is completely erased. 00h Invalid/Reserved 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 Unassigned command that should not be used. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY READ PROTECTION CONFIGURATION DATA The read protection configuration mode outputs five types of information: the manufacturer/device identifier, the block locking status, the read configuration register, the protection register, and PR lock status. Two bus cycles are required for this operation: the chip identification data is read by entering the command code 90h on DQ0–DQ7 and the identification code address on the address lines. Control signals CE#, ADV#, and OE# must be at a logic LOW level (VIL), and WE# and RST# must be at a logic HIGH level (VIH) to read data from the protection configuration register. Data is available on DQ0–DQ15. After data is read from the protection configuration register, the READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. See Table 13 for further details. During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PROGRAM SUSPEND command only. During an ERASE cycle, the CSM responds to an ERASE SUSPEND command only. When the WSM has completed its task, the WSM status bit (SR7) is set to a logic HIGH level and the CSM responds to the full command set. The CSM stays in the current command state until the microprocessor issues another command. The WSM successfully initiates an ERASE or PROGRAM operation only when VPP is within its correct voltage range. CLEAR STATUS REGISTER The internal circuitry can set, but not clear, the block lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear these status bits and synchronize to the internal operations. When the status bits are cleared, the device returns to the read array mode. READ QUERY The read query mode outputs common flash interface (CFI) data when the device is read (see Table 15). Two bus cycles are required for this operation. It is possible to access the query by writing the read query command code 98h on DQ0–DQ7 to the bank containing address 0h. Control signals CE#, ADV#, and OE# must be at a logic LOW level (VIL) and WE# and RST# must be at a logic HIGH level (VIH) to read data from the query. The CFI data structure contains information such as block size, density, command set, and electrical specifications. To return to read array mode, write the read array command code FFh on DQ0–DQ7. READ OPERATIONS The following READ operations are available: READ ARRAY, READ PROTECTION CONFIGURATION REGISTER, READ QUERY and READ STATUS REGISTER. READ ARRAY The array is read by entering the command code FFh on DQ0–DQ7. Control signals CE#, ADV#, and OE# must be at a logic LOW level (VIL) and WE# and RST# must be at a logic HIGH level (VIH) to read data from the array. Data is available on DQ0–DQ15. Any valid address within any of the blocks selects that address and allows data to be read from that address. Upon initial power-up or device reset, the device defaults to the read array mode. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 READ STATUS REGISTER The status register is read by entering the command code 70h on DQ0–DQ7. Two bus cycles are required for this operation: one to enter the command code and a second to read the status register. The addresses for both cycles must be in the same partition. In a READ cycle, the address is latched on the rising edge of the ADV# signal. Register data is updated and latched on the falling edge of ADV# or the rising (falling) CLK when ADV# is LOW during burst mode, or on the falling edge of OE# or CE#, whichever occurs last. 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 6 Command State Machine Transition Table Present state of the present partition Command input to the present partition (and next state of the present partition) 03h Write RCR confirm 2Fh 01h Lock Lock down confirm confirm C0h 60h OTP Lock/Unlock setup /Lock down, write RCR setup 98h Read query 90h Read device ID 50h 70h Clear Read status status register B0h Program /Erase suspend D0h BE confirm, P/E resume, ULB confirm Read array Read array 20h 10h/40h FFh Erase Program Read setup setup array SR7 Data when read State Mode Present state of the other partition 1 Setup 2 Busy 3 Idle 4 Erase suspend 5 Prog. suspend 6 Setup 7 Busy Read array OTP setup Lock/RCR setup Read query Read ID Read array Read status Read array Read array Erase setup Program Read setup array 1 Array Array Read array Read array Read array Read array Read array OTP setup Lock/RCR setup Read query Read ID Read array Read status Read array Read array Erase setup Program Read setup array 1 CFI Query 8 Idle 9 Erase suspend 10 Prog. suspend 11 Setup 12 Busy 13 Idle 14 Erase suspend 15 Prog. suspend 16 Setup 17 Busy Read array Read array Read Read array Read array Read array OTP setup Lock/RCR setup Read query Read ID Read array Read status Read array Read array Erase setup Program Read setup array 1 ID Device ID Read array Read array Read array Read array Read array OTP setup Lock/RCR setup Read query Read ID Read array Read status Read array Read array Erase setup Program Read setup array 1 Status Status 18 Idle 19 Erase suspend 20 Prog. suspend 21 Idle 22 Idle 23 Setup 24 Busy 25 Idle 26 Erase suspend 27 Prog. suspend Read array Read array Lock/RCR setup Read array Read array Protection register busy 1 Status Setup Protection register busy 0 Status Busy 1 Status Done Read query Read ID Read array Read status OTP setup Read array Erase setup Read array Lock/RCR setup Read query Read ID Read array Read status Read array Program Read setup array 1 Read array Read array Status Done P r o t e c t i o n r e g i s t e r (continued on the next page) 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 6 Command State Machine Transition Table (continued) Present state of the present partition Command input to the present partition (and next state of the present partition) 03h Write RCR confirm Set RCR 2Fh 01h Lock Lock down confirm confirm C0H 60h OTP Lock/Unlock setup /Lock down, write RCR setup 98h Read query LB/ULB 90h 50h Read Clear device ID status register 70h Read status B0h Program /Erase suspend Lock/ RCR Error Lock/RCR Error D0h BE confirm, P/E resume, ULB confirm LB/ULB Read array Read array 20h 10h/40h FFh Erase Program Read setup setup array Lock / RCR Error SR7 Data when read State 1 Status Setup Mode Present state of the other partition 28 Any state 29 Setup 30 Busy Read array OTP setup Lock/RCR setup Read query Read ID Read array Read array Read status Read array Erase setup Program Read setup array 1 Status Error 31 Idle 32 Erase suspend 33 Prog. suspend 34 Setup 35 Busy Read array Read array Read array Read array Read array OTP setup Lock/RCR setup Read query Read ID Read array Read array Read status Read array Erase setup Program Read setup array 1 Status Lock/ Unlock Lock/ RCR 36 Idle 37 Erase suspend 38 Prog. suspend 39 Setup 40 Busy 41 Idle 42 Erase suspend 43 Prog. suspend Read array Read array Read array Read array Read array OTP setup Lock/RCR setup Read query Read ID Read array Read array Read status Read array Erase setup Program Read setup array 1 Array Set RCR Read array Read array Program Busy PS read status Program Busy Program busy Read array 1 Status Setup 44 Any state 0 Status Busy 45 Idle 46 Setup 47 Busy 48 Idle 49 Erase suspend 50 Prog. suspend Read array Program Read array OTP setup Lock/RCR setup Read query Read ID Read array Read status Read array Read array Erase setup Program Read setup array 1 Status Done Read array Read array Program read array Lock/RCR setup Program suspend read query Program suspend read ID Program suspend read array Program Program suspend suspend Program suspend read Program busy read read array status array 1 Status Read status Program suspend 51 Setup 52 Idle 53 Erase suspend (continued on the next page) 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 6 Command State Machine Transition Table (continued) Present state of the present partition Command input to the present partition (and next state of the present partition) 03h Write RCR confirm 2Fh 01h Lock Lock down confirm confirm C0h 60h OTP Lock/Unlock setup /Lock down, write RCR setup Program suspend read array Program suspend read array Program suspend read array Set RCR Lock/RCR setup Lock/RCR setup Lock/RCR setup LB/ULB 98h Read query 90h 50h Read Clear device ID status register Program suspend read query Program suspend read ID Program suspend read query Program suspend read ID Program suspend read query Program suspend read ID 70h Read status B0h Program /Erase suspend D0h BE confirm, P/E resume, ULB confirm Program suspend read array Program Program suspend suspend Program suspend read Program busy read read array status array Program suspend read array Program Program suspend suspend Program suspend read Program busy read read array status array Program suspend read array Program Program suspend suspend Program suspend read Program busy read read array status array Lock/ RCR Error Lock/RCR Error LB/ULB Read array Read array 20h 10h/40h FFh Erase Program Read setup setup array Lock/RCR Error SR7 Data when read State 1 Array Read array Mode Present state of the other partition 54 1 1 1 ID CFI Status Read ID Program suspend Read Query Setup Idle 56 Erase suspend 57 Setup 58 Idle 59 Erase suspend 60 Setup 61 Idle 62 Erase suspend 63 Idle 64 Setup 65 Busy Read array OTP setup Lock/RCR setup Read query Read ID Read array Read array Read status Read array Erase setup Program Read setup array 1 Status Error 66 Idle 67 Erase suspend 68 Prog. suspend Read array Read array Read array Read array Setup 55 Erase 69 Setup 70 Busy 71 Idle 72 Erase suspend 73 Prog. suspend 74 Idle Read array OTP setup Lock/RCR setup Read query Read ID Read array Read array Read status Read array Erase setup Program Read setup array 1 Status Done Read array Read array Block erase busy ES read status Erase busy 0 Status Busy (continued on the next page) 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 6 Command State Machine Transition Table (continued) Present state of the present partition Command input to the present partition (and next state of the present partition) 03h Write RCR confirm 2Fh 01h Lock Lock down confirm confirm C0h 60h OTP Lock/Unlock setup /Lock down, write RCR setup Erase suspend read array Lock/RCR setup 98h Read query Erase suspend read query 90h 50h Read Clear device ID status register Erase suspend read ID Erase suspend read array 70h Read status Erase suspend read status B0h Program /Erase suspend D0h BE confirm, P/E resume, ULB confirm ES read array Erase busy 20h 10h/40h FFh Erase Program Read setup setup array Erase busy Data when read State Mode Erase suspend read array Erase suspend read array ES read array SR7 ES read array Prog. setup 1 Array ES read array Read array ES read array ES read array Erase suspend read array Lock/RCR setup Erase suspend read query Erase suspend read ID Erase suspend read array Erase suspend read status Erase busy Erase suspend read array ES read array ES read array Lock/RCR setup Erase suspend read query Erase suspend read ID Erase suspend read array Erase suspend read status ID Read ID Erase suspend read array Erase busy ES read array Prog. setup ES read array 1 ES read array Erase suspend read array 1 Erase busy Erase busy Erase suspend Erase suspend read array Erase suspend read array ES read array CFI Read query ES read array Prog. setup 1 Status Setup ES read array ES read array ES read array Erase suspend read array Lock/RCR setup Erase suspend read query Erase suspend read ID Erase suspend read array Erase suspend read status Erase busy Erase suspend read array Status Error Erase suspend read array ES read array Erase busy ES read array ES read array 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 1 17 Prog. setup ES read array 1 Status Done Present state of the other partition 75 Setup 76 Busy 77 Idle 78 Prog. suspend 79 Setup 80 Busy 81 Idle 82 Prog. suspend 83 Setup 84 Busy 85 Idle 86 Prog. suspend 87 Setup 88 Busy 89 Idle 90 Prog. suspend Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 7 Bus Operations MODE RST# CE# ADV# OE# WE# ADDRESS DQ0-DQ15 Read (array, status registers, device identification register, or query) VIH VIL VIL VIL VIH X DOUT Standby VIH VIH X X X X High-Z Output Disable VIH VIL X VIH VIH X High-Z Reset VIL X X X X X High-Z Write VIH VIL VIL VIH VIL X DIN Table 8 Status Register Bit Definitions WSMS ESS ES PS VPPS PSS BLS R 7 6 5 4 3 2 1 0 STATUS BIT # STATUS REGISTER BIT DESCRIPTION SR7 WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy Check WSM bit to determine word program or block erase completion before checking program or erase status bits. SR6 ERASE SUSPEND STATUS (ESS) 1 = BLOCK ERASE Suspended 0 = BLOCK ERASE in Progress/Completed When ERASE SUSPEND is issued, WSM halts execution and sets both WSMS and ESS bits to “1.” ESS bit remains set to “1” until an ERASE RESUME command is issued. SR5 ERASE/CHECK BLOCK ERASE STATUS (ES) 1 = Error in BLOCK ERASE/ CHECK BLOCK ERASE 0 = Successful BLOCK ERASE When this bit is set to “1” and ERASE CONFIRM is issued, WSM has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to “1” and CHECK BLOCK ERASE CONFIRM is issued, WSM has checked the block for its erase state, and the block is not erased. SR4 PROGRAM STATUS (PS) 1 = Error in PROGRAM 0 = Successful PROGRAM When this bit is set to “1,” WSM has attempted but failed to program a word. SR3 VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP = OK The VPP status bit does not provide continuous indication of the VPP level. The WSM interrogates the VPP level only after the program or erase command sequences have been entered and informs the system if VPP < 0.9V. The VPP level is also checked before the PROGRAM/ERASE is verified by the WSM. SR2 PROGRAM SUSPEND STATUS (PSS) 1 = PROGRAM Suspended 0 = PROGRAM in Progress/Completed When PROGRAM SUSPEND is issued, WSM halts execution and sets both WSM and PSS bits to “1.” PSS bit remains set to “1” until a PROGRAM RESUME command is issued. SR1 BLOCK LOCK STATUS (BLS) 1 = PROGRAM/ERASE Attempted on a Locked Block; Operation Aborted 0 = No Operation to Locked Blocks If a PROGRAM or ERASE operation is attempted to one of the locked blocks, this is set by the WSM. The operation specified is aborted and the device is returned to read status mode. SR0 RESERVED FOR FUTURE ENHANCEMENT This bit is reserved for future use. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY PROGRAMMING OPERATIONS There are two CSM commands for programming: PROGRAM SETUP and ACCELERATED PROGRAMMING ALGORITHM (see Table 3). For in-factory programming, the APA, along with an optimized set of programming parameters, minimizes chip programming time when 11.4V ≤ VPP ≤ 12.6V. For in-system programming, when 0.9V ≤ VPP ≤ 2.2V, the APA and the 32 single-word buffer significantly improve both the system throughput and the average programming time when compared with standard programming practices. The accelerated programming functionality executes and verifies the APA without microprocessor intervention. This relieves the microprocessor from constantly monitoring the progress of the programming and erase activity, freeing up valuable memory bus bandwidth. This increases the system throughput. PROGRAM SETUP COMMAND After the 40h command code is entered on DQ0DQ7, the WSM takes over and correctly sequences the device to complete the PROGRAM operation. The WRITE operation may be monitored through the status register (see the Status Register section). During this time, the CSM will only respond to a PROGRAM SUSPEND command until the PROGRAM operation has been completed, after which time, all commands to the CSM become valid again. The PROGRAM operation can be suspended by issuing a PROGRAM SUSPEND command (B0h). Once the WSM reaches the suspend state, it allows the CSM to respond only to READ ARRAY, READ STATUS REGISTER, READ PROTECTION CONFIGURATION, READ QUERY, PROGRAM SETUP, or PROGRAM RESUME. During the PROGRAM SUSPEND operation, array data should be read from an address other than the one being programmed. To resume the PROGRAM operation, a PROGRAM RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 4 for programming operation and Figure 5 for program suspend and program resume). Taking RP# to VIL during programming aborts the PROGRAM operation. ERASE OPERATIONS An ERASE operation must be used to initialize all bits in an array block to “1s.” After BLOCK ERASE CONFIRM is issued, the CSM responds only to an ERASE SUSPEND command until the WSM completes its task. Block erasure inside the memory array sets all bits within the address block to logic 1s. Erase is accomplished only by blocks; data at single address locations within the array cannot be erased individually. The block to be erased is selected by using any valid address within that block. Block erasure is initiated by a command sequence to the CSM: BLOCK ERASE SETUP (20h) followed by BLOCK ERASE CONFIRM (D0h) (see Figure 7). A two-command erase sequence protects against accidental erasure of memory contents. When the BLOCK ERASE CONFIRM command is complete, the WSM automatically executes a sequence of events to complete the block erasure. During this sequence, the block is programmed with logic 0s, data is verified, all bits in the block are erased, and finally verification is performed to ensure that all bits are correctly erased. Monitoring of the ERASE operation is possible through the status register (see the Status Register section). During the execution of an ERASE operation, the ERASE SUSPEND command (B0h) can be entered to direct the WSM to suspend the ERASE operation. Once the WSM has reached the suspend state, it allows the CSM to respond only to the READ ARRAY, READ STATUS REGISTER, READ QUERY, READ CHIP PROTECTION CONFIGURATION, PROGRAM SETUP, PROGRAM RESUME, ERASE RESUME, and LOCK SETUP (see the Block Locking section). During the ERASE SUSPEND operation, array data must be read from a block other than the one being erased. To resume the ERASE ACCELERATED PROGRAMMING ALGORITHM COMMAND The accelerated programming algorithm (APA) is intended for in-system and in-factory use. Its 32 single-word internal buffer enables fast data stream programming. The APA is activated when a 10h command is written. Upon activation, the word address and the data sequences must be provided to the WSM, without polling SR7. The same starting address must be provided for each data word. After all 32 sequences are issued, the status register reports a busy condition. Figure 6 shows the APA flowchart. If the data stream is shorter than 32 words, use FFFFh to complete the data stream. Also, ensure the starting address is aligned with a 32-word boundary. The APA is fully concurrent. For example, it can be interrupted and resumed during programming. When the APA is active, only a read access in the other bank is allowed. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY operation, an ERASE RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 8). It is also possible that an ERASE in any bank can be suspended and a WRITE to another block in the same bank can be initiated. After the completion of a WRITE, an ERASE can be resumed by writing an ERASE RESUME command. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 After an ERASE command completion, it is possible to check if the block has been erased successfully, using the CHECK BLOCK ERASE command. Two bus cycles are required for this operation: one to set up the CHECK BLOCK ERASE and the second one to start the execution of the command. If, after the operation, the SR5 bit is set to “0,” the operation has been completed succesfully. If it is set to “1,” there has been an error during the BLOCK ERASE operation. 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 4 Automated Word Programming Flowchart BUS OPERATION COMMAND COMMENTS WRITE WRITE PROGRAM SETUP Data = 40h or 10h Addr = Address of word to be programmed WRITE WRITE DATA Data = Word to be programmed Addr = Address of word to be programmed Start Issue PROGRAM SETUP Command and Word Address READ Status register data Toggle OE# or CE# to update status register Standby Check SR7 1 = Ready, 0 = Busy Issue Word Address and Word Data PROGRAM SUSPEND Loop Read Status Register Bits Repeat for subsequent words. Write FFh after the last word programming operation to reset the device to read array mode. NO NO PROGRAM SUSPEND? SR7 = 1? YES YES Full Status Register Check (optional)1 Word Program Completed BUS OPERATION COMMAND COMMENTS FULL STATUS REGISTER CHECK FLOW Read Status Register Bits SR1 = 0? NO PROGRAM Attempted on a Locked Block YES NO SR3 = 0? Standby Check SR1 1 = Detect locked block Standby Check SR32 1 = Detect VPP LOW Standby Check SR43 1 = Word program error VPP Range Error YES NO SR4 = 0? Word Program Failed YES Word Program Passed NOTE: 1. Full status register check can be done after each word or after a sequence of words. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation attempts. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 5 PROGRAM SUSPEND/ PROGRAM RESUME Flowchart BUS OPERATION COMMAND COMMENTS WRITE Start Issue PROGRAM SUSPEND Command READ Status register data Toggle OE# or CE# to update status register Standby Check SR7 1 = Ready Standby Check SR2 1 = Suspended WRITE Read Status Register Bits READ NO WRITE SR7 = 1? PROGRAM Data = B0h SUSPEND READ ARRAY Data = FFh Read data from block other than that being programmed PROGRAM Data = D0h RESUME YES NO SR2 = 1? PROGRAM Complete YES Issue READ ARRAY Command Finished Reading ? NO YES Issue PROGRAM RESUME Command PROGRAM Resumed 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 6 Accelerated Program Algorithm Flowchart BUS OPERATION COMMAND WRITE WRITE Data = 10h ACCELERATED Addr = Start address PROGRAM ALGORITHM SETUP WRITE WRITE DATA Start NO SR3 = 0? Data = Word to be programmed Addr = Start address READ Status register data Toggle OE# or CE# to update status register Standby Check SR7 1 = Ready, 0 = Busy YES Issue the ACCELERATED PROGRAMMING ALGORITHM Command (10h) and Word Address COMMENTS Issue 32 sequences of Word Data NO SR7 = 1? YES PROGRAM Complete 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 7 BLOCK ERASE Flowchart BUS OPERATION COMMAND COMMENTS WRITE WRITE ERASE SETUP Data = 20h Block Addr = Address within block to be erased WRITE ERASE Data = D0h Block Addr = Address within block to be erased Start Issue ERASE SETUP Command and Block Address Issue BLOCK ERASE CONFIRM Command and Block Address ERASE SUSPEND Loop Read Status Register Bits READ Status register data Toggle OE# or CE# to update status register Standby Check SR7 1 = Ready, 0 = Busy Repeat for subsequent blocks. Write FFh after the last BLOCK ERASE operation to reset the device to read array mode. NO NO ERASE SUSPEND? SR 7 = 1? YES YES Full Status Register Check (optional)1 BLOCK ERASE Completed BUS OPERATION COMMAND COMMENTS FULL STATUS REGISTER CHECK FLOW Read Status Register Bits NO SR1 = 0? ERASE Attempted on a Locked Block Standby Check SR1 1 = Detect locked block Standby Check SR32 1 = Detect VPP block Standby Check SR53 1 = BLOCK ERASE error YES NO SR3 = 0? VPP Range Error YES NO SR5 = 0? BLOCK ERASE Failed YES BLOCK ERASE Passed NOTE: 1. Full status register check can be done after each block or after a sequence of blocks. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 8 ERASE SUSPEND/ERASE RESUME Flowchart BUS OPERATION COMMAND COMMENTS WRITE Start Issue ERASE SUSPEND Command Read Status Register Bits ERASE SUSPEND Data = B0h READ Status register data Toggle OE# or CE# to update status register Standby Check SR7 1 = Ready Standby Check SR6 1 = Suspended WRITE READ ARRAY READ Data = FFh Read data from block other than that being erased. NO SR7 = 1? WRITE ERASE RESUME YES Data = D0h NO SR6 = 1? YES READ or PROGRAM? ERASE Complete PROGRAM READ Issue READ ARRAY Command PROGRAM Loop (Note 1) NO READ or PROGRAM Complete? YES Issue ERASE RESUME Command ERASE Continued2 NOTE: 1. See Word Programming Flowchart for complete programming procedure. 2. See BLOCK ERASE Flowchart for complete erasure procedure. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 9 CHECK BLOCK ERASE Flowchart BUS OPERATION COMMAND COMMENTS WRITE ERASE SETUP Data = 20h Block Addr = Address within block to be checked WRITE CHECK BLOCK ERASE CONFIRM Data = D1h Block Addr = Address within block to be checked Start Issue ERASE SETUP Command and Block Address Issue CHECK BLOCK ERASE CONFIRM Command and Block Address READ Status register data Toggle OE# or CE# to update status register Standby Check SR7 and SR5 NO SR7 = 1? YES NO SR5 = 0? Error YES BLOCK ERASE Complete 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY READ-WHILE-WRITE/ERASE CONCURRENCY READ CONFIGURATION The device supports three read configurations: asynchronous, synchronous burst mode, and page mode. The bit RCR15 (see Table 9) in the read configuration register sets the read configuration. Asynchronous random mode is the default read mode. At power-up, the RCR is set to BFCFh. Status registers and the device identification register support asynchronous and single synchronous READ operations only. It is possible for the device to read from one bank while erasing/writing to another bank. Once a bank enters the WRITE/ERASE operation, the other bank automatically enters read array mode. For example, during a READ CONCURRENCY operation, if a PROGRAM/ERASE command is issued in bank a, then bank a changes to the read status mode and bank b defaults to the read array mode. The device will read from bank b if the latched address resides in bank b (see Figure 10). Similarly, if a PROGRAM/ERASE command is issued in bank b, then bank b changes to read status mode and bank a defaults to read array mode. When returning to bank a, the device will read PROGRAM/ ERASE status if the latched address resides in bank a. A correct bank address must be specified to read the status register after returning from a concurrent read in the other bank. When reading the CFI or the chip protection register, concurrent operation is not allowed on the top boot device. Concurrent READ of the CFI or the chip protection register is only allowed when a PROGRAM or ERASE operation is performed on bank b on the bottom boot device. For a bottom boot device, reading of the CFI table or the chip protection register is only allowed if bank b is in read array mode. For a top boot device, reading of the CFI table or the chip protection register is only allowed if bank a is in read array mode. Figure 10 READ-While-WRITE Concurrency READ CONFIGURATION REGISTER (RCR) MODE The SET READ CONFIGURATION REGISTER command is a WRITE operation to the read configuration register (RCR). It is a two-cycle command sequence. Read configuration setup is written, followed by a second write that specifies the data to be written to the read configuration register. The data is placed on the address bus A0–A15, and it is latched on the rising edge of ADV#, CE#, or WE#, whichever occurs first. The read configuration provides the read mode (burst, synchronous, or asynchronous), burst order, latency counter, and burst length. After executing this command, the device returns to read array mode. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 27 Bank a 1 - Erasing/writing to bank a 2 - Erasing in bank a can be suspended, and a WRITE to another block in bank a can be initiated. 3 - After the WRITE in that block is complete, an ERASE can be resumed by writing an ERASE RESUME command. Bank b 1 - Reading bank a 1 - Erasing/writing to bank b 2 - Erasing in bank b can be suspended, and a WRITE to another block in bank b can be initiated. 3 - After the WRITE in that block is complete, an ERASE can be resumed by writing an ERASE RESUME command. 1 - Reading from bank b Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 9 Read Configuration Register RM R LC2 LC1 LC0 WSP HDO WC 15 14 13 12 11 10 9 8 BS CC R DPD BW BL2 BL1 BL0 7 6 5 4 3 2 1 0 BIT # DESCRIPTION FUNCTION 15 Read Mode (RM) 0 = Synchronous Burst Access Mode 1 = Asynchronous/Page Access Mode (default) 14 Reserved Default = 0 Latency Counter (LC) Sets the number of clock cycles before valid data out: 000 = Code 0 - reserved 001 = Code 1 - reserved 010 = Code 2 - reserved 011 = Code 3 100 = Code 4 101 = Code 5 110 = Code 6 - reserved 111 = Code 7 - reserved (default) 10 Wait Signal Polarity (WSP) 0 = WAIT signal is active LOW 1 = WAIT signal is active HIGH (default) 9 Hold Data Out (HDO) Sets the data output configuration: 0 = Hold data for one clock 1 = Hold data for two clocks (default) 8 Wait Configuration (WC) Controls the behavior of the WAIT# output signal: 0 = WAIT# asserted during delay 1 = WAIT# asserted one data cycle before delay (default) 7 Burst Sequence (BS) Specifies the order in which data is addressed in synchronous burst mode: 0 = Interleaved 1 = Linear (default) 6 Clock Configuration (CC) Defines the clock edge on which the BURST operation starts and data is referenced: 0 = Falling edge 1 = Rising edge (default) 5 Reserved Default = 0 4 Deep Power-Down (DPD) 0 = No DPD mode (default) 1 = DPD mode 3 Burst Wrap (BW) 0 = Burst wraps within the burst length 1 = No burst wrap (default) 2–0 Burst Length (BL) Sets the number of words the device will output in burst mode: 001 = 4 words 010 = 8 words 111 = Continuous burst (default) 13–11 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY LATENCY COUNTER The latency counter provides the number of clocks that must elapse after ADV# is set active before data will be available. This value depends on the input clock frequency. See Table 10 for the specific input clock frequency configuration code. Also, see Figure 11 for the timing diagrams pertinent to codes 2, 3, and 4. Table 10 illustrates the data output latency from ADV#, active asynchronous access, and system strobe for different latency counter codes. WAIT# CONFIGURATION The wait configuration bit, RCR8, sets the behavior of the WAIT# output signal. The WAIT# signal can be active during output delay or one data cycle before delay, when continuous burst length is enabled. WAIT# = 1 indicates valid data when RCR10 = 0. WAIT# = 0 indicates invalid data when RCR10 = 0. The setting of WAIT# before or during the delay (RCR8) will depend on the system and CPU characteristic. If RCR3 = 1 (no wrap mode), then WAIT# can also be enabled in a fouror eight-word burst if the no-wrap burst crosses the first eight-word boundary. HOLD DATA OUTPUT CONFIGURATION The hold data output configuration specifies for how many clocks data will be held valid. (See Figure 12.) Figure 11 Latency Counter CLK VIH VIL A0–A20 VIH VIL ADV# VALID ADDRESS VIH VIL Code 3 VOH VALID OUTPUT DQ0–DQ15 VO L VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT Code 4 VOH DQ0–DQ15 VO L UNDEFINED Figure 12 Hold Data Output Configuration CLK 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 Hold Data 1 CLK DQ0–DQ15 Hold Data 2 CLK DQ0–DQ15 VALID OUTPUT VALID OUTPUT VALID OUTPUT 29 VALID OUTPUT VALID OUTPUT VALID OUTPUT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY BURST SEQUENCE The burst sequence specifies the address order of the data in synchronous burst mode. It can be programmed as either linear or interleaved burst order. Continuous burst length only supports linear burst order. See Table 11 for more details. CLOCK CONFIGURATION The clock configuration configures the starting burst cycle, output data, and WAIT# signal to be asserted on the rising or falling edge of the clock. Table 10 Clock Frequency vs. First Access Latency1 FREQUENCY PERIOD (MHz) (ns) 40 54 25 18.5 LATENCY COUNTER CONFIGURATION 3 4 CLK CYCLES SYSTEM STROBE FOR FIRST (ns) DATA 4 100 5 92.5 NOTE: 1. Data is valid only if tAKS is applied. Table 11 Sequence and Burst Length STARTING ADDRESS . (DEC) 0 1 2 3 4 5 6 7 ... 14 15 ... 0 1 2 3 4 5 6 7 ... 14 15 WRAP RCR3 0 0 0 0 0 0 0 0 ... 0 0 ... ... 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 NO WRAP 4-WORD BURST LENGTH 8-WORD BURST LENGTH RCR3 LINEAR 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 INTERLEAVED 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 ... ... ... ... 1 1 1 1 1 1 1 1 ... 1 1 ... 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 ... NA NA NA NA … ... ... ... 30 LINEAR 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 ... INTERLEAVED 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 ... ... 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 ... ... NA NA NA NA NA NA NA NA ... CONTINUOUS BURST LINEAR 0-1-2-3-4-5-6-… 1-2-3-4-5-6-7-… 2-3-4-5-6-7-8-… 3-4-5-6-7-8-9-… 4-5-6-7-8-9-10-… 5-6-7-8-9-10-11-… 6-7-8-9-10-11-12-… 6-7-8-9-10-11-12-13-… ... 14-15-16-17-18-19-20-.. 15-16-17-18-19-20-21-.. ... 0-1-2-3-4-5-6-… 1-2-3-4-5-6-7-… 2-3-4-5-6-7-8-… 3-4-5-6-7-8-9-… 4-5-6-7-8-9-10-… 5-6-7-8-9-10-11… 6-7-8-9-10-11-12… 7-8-9-10-11-12-13… ... 14-15-16-17-18-19-20-… 15-16-17-18-19-20-21-… Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY BURST LENGTH The burst length defines the number of words the device outputs. The device supports a burst length of four or eight words. The device can also be set in continuous burst mode. In this mode the device linearly outputs data until the internal burst counter reaches the end of the burstable address space. RCR2 sets the burst length. BURST WRAP The burst wrap option, RCR3, signals if a four- or an eight-word linear burst access wraps within the burst length or whether it crosses the eight-word boundary. In wrap mode (RCR3 = 0) the four- or eight-word access will wrap within the four or eight words, respectively. In no-wrap mode (RCR3 = 1), the device operates similarly to a continuous burst. For example, in a four-word burst, no-wrap mode, the possible linear burst sequences that do not assert WAIT# are: 0-1-2-3 8-9-10-11 1-2-3-4 9-10-11-12 2-3-4-5 10-11-12-13 3-4-5-6 11-12-13-14 4-5-6-7 12-13-14-15 The worst-case delay is seen at the end of the eightword boundary: 7-8-9-10 and 15-16-17-18. In a fourword burst, wrap mode, no WAIT# is asserted and the possible wrap sequences are: 0-1-2-3 5-6-7-4 1-2-3-0 6-7-4-5 2-3-0-1 7-4-5-6 3-0-1-2 8-9-10-11 4-5-6-7 9-10-11-8 etc. Refer to Table 11 for a list of acceptable sequences. When the continuous burst option is selected, the internal address wraps to 000000h if the device is read past the last address. CONTINUOUS BURST LENGTH During continuous burst mode operation, the Flash memory may have an output delay when the burst sequence crosses the first eight-word boundary. Also, in four- or eight-word bursts with the burst wrap set to no wrap (RCR3 = 1), the Flash memory may have an output delay when the burst sequence crosses the first eight-word boundary. The starting address dictates whether or not a delay occurs. If the starting address is aligned with an eight-word boundary, the delay is not seen. For a four-word burst, if the starting address is aligned with a four-word boundary, a delay is not seen. If the starting address is at the end of an eight-word boundary, the output delay is the maximum delay, equal to the latency counter setting. The delay happens only once during a continuous burst access. If the burst never crosses an eight-word boundary, the WAIT# is not asserted. The activation of WAIT# informs the system if this output delay occurs. Table 12 Block Locking State Transition WP# DQ1 DQ0 NAME ERASE/PROG ALLOWED LOCK UNLOCK LOCK DOWN 0 0 0 Unlocked Yes To [001] No Change To [011] 0 0 1 Locked (Default) No No Change To [000] To [011] 0 1 1 Lock Down No No Change No Change No Change 1 0 0 Unlocked Yes To [101] No Change To [111] 1 0 1 Locked No No Change To [100] To [111] 1 1 0 Lock Down Disabled Yes To [111] No Change To [111] 1 1 1 Lock Down Disabled No No Change To [110] No Change 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY WAIT# SIGNAL IN BURST MODE In the continuous burst mode or in the four- or eightword burst mode with no wrap (RCR3 = 1), the output WAIT# informs the system when data is valid. When WAIT# is asserted during delay (RCR8 = 0), WAIT# = 1 indicates valid data and WAIT# = 0 indicates invalid data. If RCR8 = 0, WAIT# is asserted on the same cycle on which the delay occurs. If RCR8 = 1, WAIT# is asserted one cycle before the delay occurs. vert to the locked state when the device is reset or powered down. The LOCK DOWN function is dependent on the WP# input. When WP# = 0, blocks in lock down [011] are protected from program, erase, and lock status changes. When WP# = 1, the lock down function is disabled ([111]), and locked down blocks can be individually unlocked by a software command to the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and unlocked [110] as desired while WP# remains HIGH. When WP# goes LOW, blocks that were previously locked down return to the locked down state [011] regardless of any changes made while WP# was HIGH. Device reset or power-down resets all locks, including those in lock down, to locked state (see Table 13). BLOCK LOCKING The Flash devices provide a flexible locking scheme that allows each block to be individually locked or unlocked with no latency. The devices offer two-level protection for the blocks. The first level allows software-only control of block locking (for data that needs to be changed frequently), while the second level requires hardware interaction before locking can be changed (code which does not require frequent updates). Control signals WP#, DQ1, and DQ0 define the state of a block; for example, state [001] means WP# = 0, DQ1 = 0 and DQ0 = 1. Table 12 defines all of the possible locking states. READING A BLOCK’S LOCK STATUS The lock status of every block can be read in the read device identification mode. To enter this mode, write 90h to the device. Subsequent READs at block address +00002 will output the lock status of that block. The lowest two outputs, DQ0 and DQ1, represent the lock status. DQ0 indicates the block lock/unlock status and is set by the LOCK command and cleared by the UNLOCK command. It is also automatically set when entering lock down. DQ1 indicates lock down status and is set by the LOCK DOWN command. It can only be cleared by reset or power-down, not by software. Table 12 shows the locking state transition scheme. NOTE: All blocks are software-locked upon completion of a power-up sequence. LOCKED STATE After a power-up sequence completion, or after a reset sequence, all blocks are locked (states [001] or [101]). This means full protection from alteration. Any PROGRAM or ERASE operations attempted on a locked block will return an error on bit SR1 of the status register. The status of a locked block can be changed to unlocked or lock down using the appropriate software commands. Writing the lock command sequence, 60h followed by 01h, can lock an unlocked block. LOCKING OPERATIONS DURING ERASE SUSPEND Changes to block lock status can be performed during an ERASE SUSPEND by using the standard locking command sequences to unlock, lock, or lock down. This is useful in the case when another block needs to be updated while an ERASE operation is in progress. To change block locking during an ERASE operation, first write the ERASE SUSPEND command (B0h), then check the status register until it indicates that the ERASE operation has been suspended. Next, write the desired lock command sequence to block lock, and the lock status will be changed. After completing any desired LOCK, READ, or PROGRAM operation, resume the ERASE operation with the ERASE RESUME command (D0h). If a block is locked or locked down during an ERASE SUSPEND operation on the same block, the locking status bits will be changed immediately. Then, when the ERASE is resumed, the ERASE operation will complete. A locking operation cannot be performed during a PROGRAM SUSPEND. UNLOCKED STATE Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the locked state when the device is reset or powered down. An unlocked block can be locked or locked down using the appropriate software command sequence, 60h followed by D0h (see Table 4). LOCKED DOWN STATE Blocks that are locked down (state [011]) are protected from PROGRAM and ERASE operations, but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked down by writing the lock down command sequence, 60h followed by 2Fh. Locked down blocks re4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY STATUS REGISTER ERROR CHECKING Using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. Following protection configuration setup (60h), an invalid command will produce a lock command error (SR4 and SR5 will be set to “1”) in the status register. If a lock command error occurs during an ERASE SUSPEND, SR4 and SR5 will be set to “1” and will remain at “1” after the ERASE SUSPEND is resumed. When the ERASE is complete, any possible error during the ERASE cannot be detected via the status register because of the previous locking command error. A similar situation happens if an error occurs during a program operation error nested within an ERASE SUSPEND. READING THE CHIP PROTECTION REGISTER The chip protection register is read in the device identification mode. To enter this mode, load the 90h command to the bank containing address 00h. Once in this mode, READ cycles from addresses shown in Table 13 retrieve the specified information. To return to the read array mode, write the READ ARRAY command (FFh). Figure 13 Protection Register Memory Map 88h CHIP PROTECTION REGISTER 85h A 128-bit chip protection register can be used to fulfill the security considerations in the system (preventing device substitution). The 128-bit security area is divided into two 64-bit segments. The first 64 bits are programmed at the manufacturing site with a unique 64-bit unchangeable number. The other segment is left blank for customers to program as desired. (See Figure 13). 4 Words User-Programmed 84h 4 Words Factory-Programmed 81h 80h PR Lock 0 Table 13 Chip Configuration Addressing1 ITEM ADDRESS 2 DATA Manufacturer Code (x16) 00000h 002Ch Device Code Top boot configuration Bottom boot configuration 00001h Block Lock Configuration Block is unlocked Block is locked Block is locked down XX002h Lock DQ0 = 0 DQ0 = 1 DQ1 = 1 Read Configuration Register 00005h RCR Chip Protection Register Lock 80h PR Lock Chip Protection Register 1 81h–84h Factory Data Chip Protection Register 2 85h–88h User Data · · · · · 44B6 44B7 NOTE: 1. Other locations within the configuration address space are reserved by Micron for future use. 2. “XX” specifies the block address of lock configuration. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY PROGRAMMING THE CHIP PROTECTION REGISTER The first 64 bits (PR1) of the chip protection register (addresses 81h–84h) are programmed with a unique identifier at the factory. DQ0 of the PR lock register (address 80h) is programmed to a “0” state, locking the first 64 bits and preventing any further programming. The second 64 bits (PR2) is a user area (addresses 85h–88h), where the user can program any information into this area as long as DQ1 of the PR lock register remains unprogrammed. After DQ1 of the PR lock register is programmed, no further programming is allowed on PR2. The programming sequence is similar to array programming except that the PROTECTION REGISTER PROGRAMMING SETUP command (C0h) is issued instead of an ARRAY PROGRAMMING SETUP command (40h), followed by the data to be programmed at addresses 85h–88h. To program the PR lock bit for PR2 (to prevent further programming), use the above sequence on address 80h, with data of FFFDh (DQ1 = 0). quence, clock, and burst length are configured setting the related bits. All blocks in both banks can be burst read. The BURST READ works across the bank boundary in the following way: 1. In a READ operation there is no bank boundary as far as burst access is concerned. If, for example, a burst starts in bank a, the application can keep clocking until the bank boundary is reached and then read from bank b. If the application keeps clocking beyond the last location of bank b, the internal counter restarts from bank a first address. (See Figure 14.) 2. If one bank is in program or erase mode and the application starts a burst access in that bank, then the status register data is returned. The internal address counter is incremented at every clock pulse. 3. If a burst access is started in one bank and the bank boundary is crossed, and the other bank is in program or erase mode, then the status register data is returned as the first location of the bank. If the application keeps clocking, the internal address counter gets incremented at every clock cycle. If bank end is crossed, then data from the other bank is returned as shown in Figure 14. ASYNCHRONOUS READ MODE The asynchronous read mode is the default read configuration state. To use the device in an asynchronous-only application, ADV# and CLK must be tied to VSS and WAIT# should be floated. Toggling the address lines from A0 to A21, the access is purely random (tAA). The ADV# signal must be toggled to latch the address, and the CE# signal and the OE# signal must go LOW. In this case the data is placed on the data bus and the processor is ready to receive the data. Figure 14 Bank Boundary Wrapping (Bottom Boot Example) SYNCHRONOUS BURST READ MODE The burst read mode is used to achieve a faster data rate than is possible with asynchronous read mode. The rising edge of the clock (CLK) is used to latch the address with CE# and ADV# LOW (see timing diagram: Single Synchronous READ Operation). The burst read configuration is set in the read configuration register, where frequency, data output, WAIT# signal, burst se- 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 34 Bank a start address 0 00000h Bank a end address 0 FFFFFh Bank b start address 0 100000h Bank b end address 1 3FFFFFh Bank a bank boundary Bank b Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY ASYNCHRONOUS PAGE READ MODE After power-up or reset, the device operates in page mode over the whole memory array. The page size can be customized at the factory to four or eight words as required; but if no specification is made, the normal size is eight words. The initial portion of the page mode cycle is the same as the asynchronous access cycle. Holding CE# LOW and toggling addresses A0–A2 allows random access of other words in the page. ming, the device continues to draw current until the operation is complete. AUTOMATIC POWER SAVE (APS) MODE Substantial power savings are realized during periods when the array is not being read and the device is in the active mode. During this time the device switches to the automatic power save mode. When the device switches to this mode, ICC is reduced to a level comparable to ICC4. Further power savings can be realized by applying a logic HIGH level on CE# to place the device in standby mode. The low level of power is maintained until another operation is initiated. In this mode, the I/Os retain the data from the last memory address read until a new address is read. This mode is entered automatically if no address or control signals toggle. VPP/VCC PROGRAM AND ERASE VOLTAGES The Flash devices provide in-system programming and erase with VPP in the 0.9V–2.20V range. The 12V VPP mode programming is offered for compatibility with existing programming equipment, and it allows the APA execution as well. The device can withstand 100,000 WRITE/ERASE operations, irrespective of the external VPP applied because the memory cells are always programmed using the internal power sources. This provides an optimal voltage profile in order to minimize the programming stress. In addition to the flexible block locking, the VPP programming voltage can be held LOW for absolute hardware write protection of all blocks in the Flash device. When VPP is below VPPLK, any PROGRAM or ERASE operation will result in an error, prompting the corresponding status register bit (SR3) to be set. During WRITE and ERASE operations, the WSM monitors the VPP voltage level. WRITE/ERASE operations are allowed only when VPP is within the ranges specified in Table 14. When VCC is below VLKO, any WRITE/ERASE operation will be disabled. DEVICE RESET To correctly reset the Flash devices, the RST# signal must be asserted (RST# = VIL) for a minimum of tRP. After reset, the device can be accessed for a READ operation with a delayed access time of tRWH from the rising edge of RST#. RST# should be tied to the system reset to ensure that correct system initialization occurs. Please refer to the timing diagram for further details. DEEP POWER-DOWN When RCR4 = 1, deep power-down can be enabled. In this configuration, applying a logic LOW to RST# reduces the current to ICC10 and resets all the internal registers, with the exception of the RCR and the individual block protection status. To exit this mode, a wait time of 100µs (tRWHDP) must elapse after a logic HIGH is applied to RST#. During the wait time, the device performs a full power-up sequence, and the power consumption may exceed the standby current limits. Table 14 VPP Range (V) In System In Factory MIN 0.9 11.4 POWER-UP SEQUENCE MAX 2.2 12.6 The following power-up sequence is recommended to initialize internal chip operations: • At power-up, RST# should be kept at VIL for 2µs after VCC reaches VCC (MIN). • VCCQ should not come up before VCC. • V PP should be kept at V IL to maximize data integrity. When the power-up sequence is completed, RST# should be brought to VIH. To ensure a proper power-up, the rise time of RST# (10%–90%) should be < 10µs. STANDBY MODE ICC supply current is reduced by applying a logic HIGH level on CE# and RST# to enter the standby mode. In the standby mode, the outputs are High-Z. Applying a CMOS logic HIGH level on CE# and RST# reduces the current to ICC4 (MAX). If the device is deselected during an ERASE operation or during program- 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum DC voltage on VPP may overshoot to +13.5V for periods < 20ns. ABSOLUTE MAXIMUM RATINGS* Voltage to Any Ball Except VCC and VPP with Respect to VSS ....................... -0.5V to +2.45V VPP Voltage (for BLOCK ERASE and PROGRAM with Respect to VSS) ................. -0.5V to +13.5V** VCC and VCCQ Supply Voltage with Respect to VSS ....................... -0.3V to +2.45V Output Short Circuit Current ............................... 100mA Operating Temperature Range ............ -40oC to +85oC Storage Temperature Range ............... -55oC to +125oC Soldering Cycle .......................................... 260oC for 10s RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN MAX UNITS Operating temperature tA -40 +85 VCC supply voltage (MT28F642D18) VCC 1.70 1.90 V VCC supply voltage (MT28F642D20) o NOTES C VCC 1.80 2.20 V I/O supply voltage (VCC = 1.70–1.90V) VCCQ 1.70 1.90 V I/O supply voltage (VCC = 1.80–2.25V) VCCQ 1.80 2.25 V VPP voltage, when used as logic control VPP1 0.9 2.20 V VPP in-factory programming voltage VPP2 11.4 12.6 V Block erase cycling VPP = VPP1 VPP1 100,000 – Cycles Block erase cycling VPP = VPP2 VPP2 – 100 Cycles 1 NOTE: 1. VPP = VPP2 is a maximum of 10 cumulative hours. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Figure 15 AC Input/Output Reference Waveform VCC Input VCC/2 VCCQ/2 Test Points Output VSS AC test inputs are driven at VCC for a logic 1 and VSS for a logic 0. Input timing begins at VCC/2, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns. Figure 16 Output Load Circuit VCC 14.5K I/O 14.5K 30pF VSS CAPACITANCE (TA = +25ºC; f = 1 MHz) PARAMETER/CONDITION 1 Input Capacitance Output Capacitance 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 37 SYMBOL TYP MAX UNITS C 7 12 pF COUT 9 12 pF Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY DC CHARACTERISTICS1 MT28F642D20 MT28F642D18 PARAMETER SYMBOL MIN TYP MAX Input Low Voltage VIL 0 – 0.4 V 2 Input High Voltage VIH VCCQ - 0.4V – VCCQ V 2 Output Low Voltage IOL = 100µA VOL – – 0.1 V Output High Voltage IOH = -100µA VOH VCCQ - 0.1V – – V VPP Lockout Voltage VPPLK – – 0.4 V VPP During PROGRAM/ERASE Operations VPP1 0.9 – 2.2 V VPP2 11.4 – 12.6 V VCC Program/Erase Lock Voltage VLKO 1 – – V Input Leakage Current IL – – 1 µA Output Leakage Current IOZ 0.2 – 1 µA VCC Read Current Asynchronous Random Read, 70ns cycle ICC1 – – 15 mA VCC Page Mode Read Current, 70ns/30ns cycle ICC2 – – 5 mA 3, 4 VCC Burst Mode Read Current, 18.5ns cycle ICC3 – – 10 mA 4 VCC Standby Current ICC4 – 25 50 µA VCC Program Current ICC5 – – 55 mA VCC Erase Current ICC6 – – 65 mA VCC Erase Suspend Current ICC7 – 25 50 µA 5 VCC Program Suspend Current ICC8 – 25 50 µA 5 Read-While-Write Current ICC9 – – 80 mA Deep Power-Down Current ICC10 – 15 25 µA VPP Current (Read, Standby, Erase Suspend, Program Suspend) VPP ≤ VCC VPP ≥ VCC IPP1 – – – – 1 200 µA µA NOTE: 1. 2. 3. 4. 5. UNITS NOTES 3, 4 All currents are in RMS unless otherwise noted. VIL may decrease to -0.4V, and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns. APS mode reduces ICC to approximately ICC4 levels. Test conditions: VCC = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL. ICC7 and ICC8 values are valid when the device is deselected. Any READ operation performed while in suspend mode will have an additional current draw of suspend current (ICC7 or ICC8). 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY ASYNCHRONOUS READ CYCLE TIMING REQUIREMENTS1 PARAMETER Address setup to ADV# HIGH CE# LOW to ADV# HIGH READ cycle time Address to output delay CE# LOW to output delay ADV# LOW to output delay ADV# pulse width LOW ADV# pulse width HIGH Address hold from ADV# HIGH Page address access OE# LOW to output delay RST# HIGH to output delay CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# change RST# deep power-down SYMBOL t AVS t CVS tRC tAA tACE tAADV tVP tVPH tAVH tAPA tAOE tRWH tOD tOH t RWHDP -70 MIN MAX 10 10 70 70 70 70 10 10 3 30 25 – 15 0 100 -80 MIN MAX 10 10 80 80 80 80 10 10 3 30 25 – 25 0 100 UNITS NOTES ns ns ns ns ns ns ns µs 2 BURST READ CYCLE TIMING REQUIREMENTS1 -705 PARAMETER CLK period CLK HIGH (LOW) time CLK fall (rise) time Address valid set up to clock ADV# LOW set to CLK CE# LOW set to CLK CLK to output delay Output hold from CLK Address hold from CLK CLK to WAIT# delay CE# HIGH between subsequent synchronous READs SYMBOL tCLK tKP tKHKL tAKS tVKS tCKS tACLK tKOH tAKH tKHTL tCBPH MIN 18.5 5 -804 MAX MIN 25 7.5 3 7 7 9 MAX 5 7 7 13 15 3.5 10 20 5 10 15 20 20 20 UNITS ns ns ns ns ns ns ns ns ns ns ns NOTE: 1. See Figures 17 and 18 for timing requirements and load configuration. 2. For the MT28F642D18, tRWH = 250ns (MAX); for the MT28F642D20, tRWH = 200ns (MAX). 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY WRITE CYCLE TIMING REQUIREMENTS -70/-80 PARAMETER HIGH recovery to WE# going LOW CE# setup to WE# going LOW Write pulse width ADV# pulse width Data setup to WE# going HIGH Address setup to WE# going HIGH ADV# setup to WE# going HIGH Address setup to ADV# going HIGH CE# hold from WE# HIGH Data hold from WE# HIGH Address hold from WE# HIGH Address hold to ADV# going HIGH Write pulse width High RST# pulse width WP# setup to WE# going HIGH VPP setup to WE# going HIGH Write recovery before Read WP# hold from valid SRD VPP hold from valid SRD WE# HIGH to data valid SYMBOL tRS tCS tWP tVP tDS tAS tVS tAVS tCH tDH tAH tAVH tWPH tRP tRHS tVPS tWOS tRHH tVPPH tWB MIN 150 0 70 10 70 50 70 10 0 0 0 3 30 100 0 200 50 0 0 MAX tAA + 50 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ERASE AND PROGRAM TIMING REQUIREMENTS -70/-80 PARAMETER 4 KW parameter block program time 32 KW parameter block program time Word program time 4 KW parameter block erase time 32 KW parameter block erase time Program suspend latency Erase suspend latency Chip programming time (APA) 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 TYP 40 320 8 0.3 0.5 5 5 40 MAX 800 6,400 10,000 6 6 10 20 20 UNITS ms ms µs s s µs µs s Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY SINGLE ASYNCHRONOUS READ OPERATION A0–A21 VIH VALID ADDRESS VIL tAA tRC tOD VIH ADV# VIL VIH CE# VIL tACE VIH OE# VIL tOH VIH WE# WAIT#1 VIL VOH VOL High-Z tAOE VOH DQ0–DQ15 RST# High-Z VALID OUTPUT VOL tRWH VIH VIL UNDEFINED READ TIMING PARAMETERS -70 SYMBOL MIN -80 UNITS t AOE 70 70 25 80 80 25 ns ns ns tR C 70 80 ns t ACE MIN -70 MAX t AA MAX SYMBOL MIN -80 MAX t RWH 2 – 15 tO D tO H MIN 0 0 MAX UNITS – 25 ns ns ns NOTE: 1. WAIT# is shown active LOW. 2. For the MT28F642D18, tRWH = 250ns (MAX); for the MT28F642D20, tRWH = 200ns (MAX). 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY ASYNCHRONOUS PAGE MODE READ OPERATION A3–A21 VIH VALID ADDRESS VIL A0–A2 VIH VALID ADDRESS VALID ADDRESS VIL VALID ADDRESS VALID ADDRESS tAA VIH ADV# VIL tOD VIH CE# VIL tACE VIH OE# VIL VIH WE# WAIT#1 VIL VOH High-Z VOL tAOE VOH DQ0–DQ15 tAPA VALID OUTPUT High-Z VOL VALID OUTPUT tOH VALID OUTPUT VALID OUTPUT tRWH VIH RST# VIL UNDEFINED READ TIMING PARAMETERS -70 SYMBOL tAA tACE MIN tAOE tRC -80 MAX 70 70 25 70 MIN -70 MAX 80 80 UNITS ns ns 25 80 ns ns SYMBOL tRWH1 tOD tOH MIN -80 MAX – 15 0 MIN 0 MAX – 25 UNITS ns ns ns NOTE: 1. WAIT# is shown active LOW. 2. For the MT28F642D18, tRWH = 250ns (MAX); for the MT28F642D20, tRWH = 200ns (MAX). 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY SINGLE SYNCHRONOUS READ OPERATION CLK VIH VIL tAKS A0–A21 VIH tAKH VALID ADDRESS VIL tAA tAVH ADV# tVPH VIH VIL tAADV tVP tVKS CE# tOD VIH VIL tACE tCVS tCKS OE# VIH VIL WE# VIH VIL WAIT#1 VOH VOL High-Z tKOH tAOE tOH DQ0–DQ15 VOH VALID OUTPUT High-Z VO L tACLK UNDEFINED READ TIMING PARAMETERS -70 SYMBOL tAKS tVKS MIN 7 -80 MAX MIN 7 -70 MAX UNITS ns SYMBOL t AADV MIN 7 9 7 13 ns ns tVP tVPH 10 10 3.5 10 5 10 ns ns tAVH 3 tAKH tCVS 10 10 tCKS tKOH t AA tACE 70 70 80 80 MIN MAX 80 UNITS 10 10 3 tAOE 25 25 ns t OD 15 25 ns ns t OH ns ns -80 MAX 70 0 0 NOTE: 1. WAIT# is shown active LOW. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY 4-WORD SYNCHRONOUS BURST OPERATION CLK VIH VIL tAKS A0–A21 VIH tAKH VALID ADDRESS VIL tAA ADV# tVPH VIH VIL tAADV tVP tCBPH tVKS CE# tOD VIH VIL tACE tCVS tCKS OE# VIH VIL WE# VIH VIL WAIT#1 VOH VOL High-Z High-Z tKOH tAOE DQ0–DQ15 VOH VALID OUTPUT High-Z VO L tOH VALID OUTPUT VALID OUTPUT VALID OUTPUT tACLK UNDEFINED READ TIMING PARAMETERS -70 SYMBOL tAKS tVKS tCKS tKOH tAKH tCVS MIN 7 -70 -80 MAX MIN 7 MAX SYMBOL t AADV UNITS ns 7 9 3.5 7 13 5 ns ns ns tVP 10 10 10 10 ns tAOE t AA tACE 70 70 MIN tVPH 10 10 tAVH 3 t OH ns ns MIN 0 MAX 80 UNITS 25 25 ns ns 10 10 3 25 15 t OD 80 80 -80 MAX 70 0 ns NOTE: 1. WAIT# is shown active LOW. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY CONTINUOUS BURST READ SHOWING AN OUTPUT DELAY WITH RCR8 = 0(1) CLK VIH VIL tKP tCLK A0–A21 tKHKL VIH VIL ADV# VIH VIL CE# VIH VIL OE# VIH VIL WE# VIH VIL WAIT#1 tKHTL tKHTL VOH VOL DQ0–DQ15 VOH VALID OUTPUT VO L VALID OUTPUT INVALID OUTPUT VALID OUTPUT VALID OUTPUT tKOH tACLK UNDEFINED READ TIMING PARAMETERS -70 SYMBOL tCLK tKP MIN 18.5 MIN 25 5 tKHKL -70 -80 MAX MAX 7.5 3 5 SYMBOL UNITS ns MIN t ACLK tKOH ns ns t KHTL -80 MAX MIN 15 3.5 MAX UNITS 20 ns ns ns 5 15 20 NOTE: 1. WAIT# is shown active LOW. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY TWO-CYCLE PROGRAMMING/ERASE OPERATION A0–A21 VIH VALID ADDRESS VIL tAVS tAVH tAS VALID ADDRESS tAH tVPH VIH ADV# VALID ADDRESS VIL tVP tVS VIH CE# VIL tCS tWOS tCH VIH OE# VIL tWPH VIH WE# VIL VIH DQ0–DQ15 CMD/ DATA High-Z VIL CMD/ DATA tRS STATUS tDS tCH VIH RST# tWB CMD VIL tRHS tRHH tVPS tVPPH VIH WP# VIL VIPPH VIPPLK VPP V IL UNDEFINED WRITE TIMING PARAMETERS -70/-80 SYMBOL t RS t CS MIN 150 0 MAX -70/-80 UNITS ns ns SYMBOL t AH tAVH 70 10 ns ns tWPH 70 50 70 ns ns ns t RHS ns ns t RHH t CH 10 0 t DH 0 ns t WB tWP tVP t DS t AS tVS tAVS 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 tRP tVPS tWOS tVPPH 46 MIN 0 MAX UNITS ns 3 30 100 ns ns ns 0 200 ns ns 50 0 0 ns ns ns t AA + 50 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY RESET OPERATION CE# VIH VIL RST# VIH VIL tRP OE# VIH VIL DQ0–DQ15 VOH VOL tRWH READ AND WRITE TIMING PARAMETERS -70 SYMBOL tRWH1 tRP MIN 100 -80 MAX – MIN 100 MAX – UNITS ns ns NOTE: 1. For the MT28F642D18, tRWH = 250ns (MAX); for the MT28F642D20, tRWH = 200ns (MAX). 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 15 CFI OFFSET DATA DESCRIPTION 0 2Ch Manufacturer code 1 B6h Top boot block device code B7h Bottom boot block device code 02 – 0F reserved 10,11 0051, 0052 12 0059 13, 14 0003, 0000 Primary OEM command set 15, 16 0039, 0000 Address for primary extended table 17, 18 0000, 0000 Alternate OEM command set 19, 1A 0000, 0000 Address for OEM extended table 1B 0017 VDD MIN for Erase/Write; Bit7–Bit4 Volts in BCD, Bit3–Bit0 100mV in BCD Reserved “QR” “Y” 1C 0022 VDD MAX for Erase/Write; Bit7–Bit4 Volts in BCD, Bit3–Bit0 100mV in BCD 1D 00B4 VPP MIN for Erase/Write; Bit7–Bit4 Volts in Hex, Bit3–Bit0 100mV in BCD, 0000 = VPP pin 1E 00C6 VPP MAX for Erase/Write; Bit7–Bit4 Volts in Hex, Bit3–Bit0 100mV in BCD, 0000 = VPP pin 1F 0003 Typical timeout for single byte/word program, 2n µs, 0000 = not supported 20 0000 Typical timeout for maximum size multiple byte/word program, 2n µs, 0000 = not supported 21 0009 Typical timeout for individual block erase, 2n ms, 0000 = not supported 22 0000 Typical timeout for full chip erase, 2n ms, 0000 = not supported 23 000C Maximum timeout for single byte/word program, 2n µs, 0000 = not supported 24 0000 Maximum timeout for maximum size multiple byte/word program, 2n µs, 0000 = not supported 25 0003 Maximum timeout for individual block erase, 2n ms, 0000 = not supported 26 0000 Maximum timeout for full chip erase, 2n ms, 0000 = not supported 27 0017 Device size, 2n bytes 28 0001 Bus interface, x8 = 0, x16 = 1, x8/x16 = 2 29 0000 Flash device interface description, 0000 = async 2A, 2B 0000, 0000 2C 0003 2D, 2E 005F–0000 0007–0000 Bottom boot block device erase block region information 1, 8 blocks … 2F, 30 0000–0001 Top boot block device …..of 64KB 0020–0000 Bottom boot block device …..of 8KB 31, 32 001E–0000 31 blocks of 33, 34 0000–0001 ……64KB 0007–0000 Top boot block device …8 blocks of 005F–0000 Bottom boot block device …96 blocks of 35, 36 Maximum number of bytes in multibyte program or page, 2n Number of erase block regions within device (4K words and 32K words) Top boot block device erase block region information 1, 96 blocks … (continued on next page) 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY Table 15 (continued) CFI OFFSET DATA 37, 38 0020–0000 Top boot block device …..of 8KB 0000–0001 Bottom boot block device …..of 64KB 39, 3A 0050, 0052 “PR” 3B 0049 “I” 3C 0030 Major version number, ASCII 3D 0031 Minor version number, ASCII 3E 3F 40 41 00E6 0003 0000 0000 Optional Feature and Command Support Bit 0 Chip erase supported no = 0 Bit 1 Suspend erase supported = yes = 1 Bit 2 Suspend program supported = yes = 1 Bit 3 Chip lock/unlock supported = no = 0 Bit 4 Queued erase supported = no = 0 Bit 5 Instant individual block locking supported = yes = 1 Bit 6 Protection bits supported = yes = 1 Bit 7 Page mode read supported = yes = 1 Bit 8 Synchronous read supported = yes = 1 Bit 9 Simultaneous operation supported = yes = 1 42 0001 Program supported after erase suspend = yes 43, 44 0003, 0000 45 0018 46 00C0 VPP supply optimum, 00 = not supported, D7–D4 Hex V, D3–D0 100mV 47 0001 Number of protection register files in JEDEC ID space 48, 49 0080, 0000 Lock bytes LOW address, lock bytes HIGH address 4A, 4B 0003, 0003 2n factory programmed bytes, 2n user programmable bytes 4C 0003 Background Operation 0000 = Not used 0001 = 4% block split 0002 = 12% block split 0003 = 25% block split 0004 = 50% block split 4D 0072 Burst Mode Type 0000 = No burst mode 00x1 = 4 words MAX 00x2 = 8 words MAX 00x3 = 16 words MAX 001x = Linear burst, and/or 002x = Interleaved burst, and/or 003x = Continuous burst 4E 0002 Page 0000 0001 0002 0003 0004 4F 0000 Not used 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 DESCRIPTION Bit 0 block lock status active = yes, Bit 1 block lock down active = yes VCC supply optimum, 00 = not supported, D7–D4 BCD V, D3–D0 100mV Mode Type = No page mode = 4-word page = 8-word page = 16-word page = 32-word page 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY 59- BALL FBGA 0.10 C 0.80 ±0.075 SEATING PLANE SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 37% Pb, 2%Ag SOLDER BALL PAD: Ø .27mm C SUBSTRATE: PLASTIC LAMINATE 8.00 ±0.10 5.25 BALL #1 ID 0.75 TYP BALL A8 ENCAPSULATION MATERIAL: EPOXY NOVOLAC BALL A1 59X Ø 0.35 TYP SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.33 0.75 TYP CL BALL #1 ID 4.50 12.00 ± 0.10 2.25 ±0.05 6.00 ±0.05 1.50 (4X) CL 2.625 ±0.05 4.00 ±0.05 SUPPORT BALLS (4X) 1.20 MAX NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. DATA SHEET DESIGNATION Advance: This data sheet contains initial descriptions of products still under development. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 4 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY REVISION HISTORY Rev. 3, ADVANCE .................................................................................................................................................................... 8/02 • Clarified device specific VCC, VCCQ and VPP voltages. Rev. 2, ADVANCE .................................................................................................................................................................... 7/02 • Changed low power consumption voltage from 1.90V to 2.20V • Corrected top boot block device address range for blocks 123 and 125 • Corrected Output Disable row in Bus Operations table • Updated Status Register section • Updated command descriptions • Updated flowcharts • Updated Read-While-Write/EraseConcurrency section • Updated Read Configuration Register table • Corrected addresses in Bank Boundary Wrapping figure • Updated timing diagrams • Corrected CFI table Original document, ADVANCE, Rev. 1 ............................................................................................................................... 3/02 4 Meg x 16 Async/Page/Burst Flash Memory MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc.