MICRON MT46V128M8

PRELIMINARY‡
1Gb: x4, x8, x16
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
MT46V256M4 – 64 MEG X 4 X 4 BANKS
MT46V128M8 – 32 MEG X 8 X 4 BANKS
MT46V64M16 – 16 MEG X 16 X 4 BANKS
For the latest data sheet revisions, please refer to the
Micron Web site: www.micron.com/datasheets
Features
Figure 1: Pin Assignment (Top View)
66-pin TSOP
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two
–one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
• tRAS lockout supported (tRAP = tRCD)
OPTIONS
• Configuration
256 Meg x 4 (64 Meg x 4 x 4 banks)
128 Meg x 8 (32 Meg x 8 x 4 banks)
64 Meg x 16 (16 Meg x 16 x 4 banks)
• Plastic Package – OCPL
66-pin TSOP(400 mil width, 0.65mm
pin pitch)
66-pin TSOP Lead-Free (400 mil width,
0.65mm pin pitch)
• Timing – Cycle Time
7.5ns @ CL = 2.5 (DDR266B)1, 2
• Temperature Rating
Commercial Temperature
(0°C to +70°C)
NOTE:
x4
x8
x16
VDD
VDD
VDD
NC
DQ0
DQ0
VDDQ VDDQ VDDQ
NC
DQ1
NC
DQ0
DQ1
DQ2
VSSQ
VSSQ
VssQ
NC
DQ3
NC
NC
DQ2
DQ4
VDDQ VDDQ VDDQ
NC
NC
DQ5
DQ1
DQ3
DQ6
VSSQ
VSSQ
VssQ
NC
DQ7
NC
NC
NC
NC
VDDQ VDDQ VDDQ
NC
NC LDQS
A13
A13
A13
VDD
VDD
VDD
DNU
DNU
DNU
NC
NC
LDM
WE#
WE#
WE#
CAS#
CAS#
CAS#
RAS#
RAS#
RAS#
CS#
CS#
CS#
NC
NC
NC
BA0
BA0
BA0
BA1
BA1
BA1
A10/AP A10/AP A10/AP
A0
A0
A0
A1
A1
A1
A2
A2
A2
A3
A3
A3
VDD
VDD
VDD
MARKING
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
x16
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
DNU
VREF
VSS
UDM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x8
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x4
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
256 MEG X 4 128 MEG X 8 64 MEG X 16
Configuration
256M4
128M8
64M16
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
TG
P
64 Meg x 4 x 4
banks
8K
16K (A0–A13)
4(BA0,BA1)
4K(A0–A9,
A11, A12)
32 Meg x 8 x 4 16 Meg x 16 x 4
banks
banks
8K
8K
16K (A0–A13)
16K (A0–A13)
4(BA0,BA1)
4(BA0,BA1)
2K(A0–A9, A11)
1K(A0–A9)
Key Timing Parameters
-75
None
CLOCKRATE
SPEED
GRADE
CL=2**
CL=2.5**
DATA-OUT
WINDOW*
ACCESS
WINDOW
DQS–DQ
SKEW
-75
100 MHz
133MHz
2.5ns
±0.75ns
+0.5ns
* Minimum clock rate @ CL= 2.5
** CL = CAS (Read) Latency
1. Supports PC2100 modules with 2.5-3-3 timing
2. Supports PC1600 modules with 2-2-2 timing,
09005aef8076894f
1gbBDDRx4x8x16_1.fm - Rev. A 3/03 EN
‡PRODUCTS
1
©2003 Micron Technology, Inc.
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
1Gb DDR SDRAM Part Numbers
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or
WRITE command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the
burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full
drive option outputs are SSTL_2, Class II compatible.
Example Part Number: MT46V64M16TG-75
-
MT46V
Configuration
Package
Speed
Special
Options
Temperature
Operating Temp
Standard
Configuration
256 Meg x4
256M4
128 Meg x8
128M8
64 Meg x16
Special Options
Standard
64M16
Package
400 mil TSOP
TG
400 mil TSOP Lead-Free
P
-75
Speed Grade
tCK=7.5ns, CL = 2.5
General Description
The 1Gb DDR SDRAM is a high-speed CMOS,
dynamic
random-access
memory
containing
1,073,741,824 bits. It is internally configured as a quadbank DRAM.
The 1Gb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 1Gb DDR SDRAM effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The
x16 offering has two data strobes, one for the lower
byte and one for the upper byte.
The 1Gb DDR SDRAM operates from a differential
clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
09005aef8076894f
1gbBDDRx4x8x16_1.fm - Rev. A 3/03 EN
NOTE: 1. The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
2. Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ
collectively, unless specifically stated otherwise. Additionally, the x16 is divided into
two bytes, the lower byte and upper byte.
For the lower byte (DQ0 through DQ7) DM
refers to LDM and DQS refers to LDQS. For
the upper byte (DQ8 through DQ15) DM
refers to UDM and DQS refers to UDQS.
3. Complete functionality is described
throughout the document and any page or
diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
4. Any specific requirement takes precedence
over a general statement.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
TABLE OF CONTENTS
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1Gb DDR SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Power-down (CKE Not Active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
09005aef8076894f
1gbDDRx4x8x16TOC.fm - Rev. A 3/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
Figure 41:
Figure 42:
Figure 43:
Figure 44:
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Figure 49:
Figure 50:
Figure 51:
Pin Assignment (Top View) 66-pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Functional Block Diagram 256 Meg x4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Functional Block Diagram 128 Meg x8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Functional Block Diagram 64 Meg x16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK£3 . . . . . . . . . . . . . . . . . . . . . .18
READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
READ Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Consecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
WRITE to READ - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
WRITE to READ - Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
WRITE to READ - Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
WRITE to PRECHARGE - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
WRITE to Precharge – Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
WRITE to PRECHARGE Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Input Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
SSTL_2 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Derating Data Valid Window (tQH - tDQSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Full Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Full Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Reduced Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Reduced Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Data Output Timing – tAC and tDQSCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Initialize And Load Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Bank Read - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Bank Read - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Bank Write - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Bank Write - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Write - DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
66-Pin Plastic TSOP (400 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
09005aef8076894f
1gbDDRx4x8x16LOF.fm - Rev. A 3/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Ball/Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Truth Table – Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Truth Table – DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Truth Table – Current State Bank n - Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Truth Table – Current State Bank n - Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
AC Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Clock Input Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Capacitance (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Capacitance (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
IDD Specifications and Conditions (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
IDD Specifications and Conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
IDD Test Cycle Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .52
Input Slew Rate Derating Values for Addresses and Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Input Slew Rate Derating Values for DQ, DQS, and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Normal Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Reduced Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
09005aef8076894f
1gbDDRx4x8x16LOT.fm - Rev. A 3/03 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 2: Functional Block Diagram 256 Meg x4
CKE
CK#
CK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTERS
REFRESH 14
COUNTER
16
ROWADDRESS
MUX
14
14
BANK0
ROWADDRESS
16,384
LATCH
&
DECODER
CK
BANK0
MEMORY
ARRAY
(16,384 x 2,048 x 8)
DLL
DATA
4
8
READ
LATCH
SENSE AMPLIFIERS
4
MUX
DRVRS
4
1
DQS
GENERATOR
(16,384)
DQ0–
DQ3
COL0
I/O GATING
DM MASK LOGIC
2
A0-A13,
BA0, BA1
16
ADDRESS
REGISTER
2
8
BANK
CONTROL
LOGIC
1
COLUMN
DECODER
COLUMNADDRESS
COUNTER/
LATCH
DQS
1
MASK
2048
12
DQS
INPUT
REGISTERS
11
8
WRITE
FIFO
&
DRIVERS
clk
out
1
1
1
4
4
4
4
2
8
clk
in DATA
CK
RCVRS
DM
4
1
COL0
1
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 3: Functional Block Diagram 128 Meg x8
CKE
CK#
CK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTERS
REFRESH 14
COUNTER
16
ROWADDRESS
MUX
14
14
BANK0
ROWADDRESS
16,384
LATCH
&
DECODER
CK
BANK0
MEMORY
ARRAY
(16,384 x 1,024 x 16)
DLL
DATA
8
16
READ
LATCH
SENSE AMPLIFIERS
8
MUX
DRVRS
8
1
DQS
GENERATOR
(16,384)
DQ0–
DQ7
COL0
I/O GATING
DM MASK LOGIC
2
A0-A13,
BA0, BA1
16
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
1
COLUMN
DECODER
COLUMNADDRESS
COUNTER/
LATCH
DQS
1
MASK
1024
11
DQS
INPUT
REGISTERS
8
10
16
WRITE
FIFO
&
DRIVERS
clk
out
1
1
1
8
8
8
8
2
16
clk
in DATA
CK
RCVRS
DM
8
1
COL0
1
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 4: Functional Block Diagram 64 Meg x16
CKE
CK#
CK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTERS
REFRESH 14
COUNTER
16
ROWADDRESS
MUX
14
14
BANK0
ROWADDRESS
16,384
LATCH
&
DECODER
CK
BANK0
MEMORY
ARRAY
(16,384 x 512 x 32)
DLL
DATA
16
32
READ
LATCH
SENSE AMPLIFIERS
16
MUX
DRVRS
16
2
DQS
GENERATOR
(16,384)
DQ0–
DQ16
COL0
I/O GATING
DM MASK LOGIC
2
A0-A13,
BA0, BA1
16
ADDRESS
REGISTER
2
32
BANK
CONTROL
LOGIC
2
COLUMN
DECODER
COLUMNADDRESS
COUNTER/
LATCH
DQS L/H
2
MASK
512
10
DQS
INPUT
REGISTERS
9
32
WRITE
FIFO
&
DRIVERS
clk
out
2
2
2
16
16
4
32
clk
in DATA
CK
RCVRS
LDM, UDM
32
16
16
1
COL0
1
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 1:
Ball/Pin Descriptions
TSOP
NUMBERS
SYMBOL
TYPE
DESCRIPTION
45, 46
CK, CK#
Input
44
CKE
Input
24
CS#
Input
23, 22,
21
47
20, 47
RAS#, CAS#,
WE#
DM
LDM, UDM
Input
26, 27
BA0, BA1
Input
29, 30, 31, 32,
35, 36, 37, 38,
39, 40, 28
41, 42
17
A0, A1, A2, A3,
A4, A5, A6, A7,
A8, A9, A10,
A11, A12
A13
Input
2, 4, 5,
7, 8, 10,
11, 13, 54,
56, 57, 59,
60, 62, 63,
65
DQ0–DQ2
DQ3–DQ5
DQ6–DQ8
DQ9–DQ11
DQ12–DQ14
DQ15
I/O
Clock: CK and CK# are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK and
negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal
clock, input buffers and output drivers. Taking CKE LOW provides
PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),
or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the outputs. CKE
must be maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER- DOWN.
Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an
SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied
and until CKE is first brought HIGH, after which it becomes a SSTL_2 input
only.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a
WRITE access. DM is sampled on both edges of DQS. Although DM pins are
input-only, the DM loading is designed to match that of DQ and DQS pins.
For the x16, LDM is DM for DQ0–DQ7 and UDM is DM for DQ8–DQ15. Pin
20 is a NC on x4 and x8.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands,
to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the
PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or
all banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD
MODE REGISTER command.
Data Input/Output: Data bus for x16
(DQ4–DQ15 are NC for the x4)
(DQ8–DQ16 are NC for the x8)
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
Input
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 1:
Ball/Pin Descriptions (Continued)
TSOP
NUMBERS
SYMBOL
TYPE
2, 5, 8,
11, 56, 59,
62, 65
DQ0–DQ2
DQ3–DQ5
DQ6, DQ7
I/O
Data Input/Output: Data bus for x8
(DQ4–DQ7 are NC for the x4)
5, 11, 56,
62
51
16
51
DQ0–DQ2
DQ3
DQS
LDQS
UDQS
I/O
Data Input/Output: Data bus for x4
I/O
14, 25,
43, 53
19, 50
NC
–
Data Strobe: Output with read data, input with write data. DQS is edgealigned with read data, centered in write data. It is used to capture data.
For the x16, LDQS is DQS for DQ0–DQ7 and UDQS is DQS for DQ8–DQ15.
Pin 16 (E7) is NC on x4 and x8.
No Connect: These pins should be left unconnected.
Do Not Use: Must float to minimize noise on VREF.
DNU
–
3, 9, 15, 55, 61
VDDQ
Supply
6, 12, 52, 58, 64
VSSQ
VDD
VSS
VREF
Supply
1, 18, 33
34, 48, 66
49
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
Supply
Supply
Supply
DESCRIPTION
DQ Power Supply: +2.5V ±0.2V. Isolated on the die for improved noise
immunity.
DQ Ground. Isolated on the die for improved noise immunity.
Power Supply: +2.5V ±0.2V.
Ground.
SSTL_2 reference voltage.
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Functional Description
The 1Gb DDR SDRAM is a high-speed CMOS,
dynamic
random-access
memory
containing
1,073,741,824 bits. The 1Gb DDR SDRAM is internally
configured as a quad-bank DRAM.
The 1Gb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 1Gb DDR SDRAM consists of a
single 2n-bit wide, one-clock-cycle data transfer at the
internal DRAM core and two corresponding n-bit
wide, one-half-clock-cycle data transfers at the I/O
pins.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0-A13 select the row). The
address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must
be initialized. The following sections provide detailed
information covering device initialization, register definition, command descriptions, and device operation.
power supply and reference voltages are stable, and
the clock is stable, the DDR SDRAM requires a 200µs
delay prior to applying an executable command.
Once the 200µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE
should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be
applied. Next a LOAD MODE REGISTER command
should be issued for the extended mode register (BA1
LOW and BA0 HIGH) to enable the DLL, followed by
another LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL
and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset
and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the
all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode
register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL)
is required. Following these requirements, the DDR
SDRAM is ready for normal operation.
Register Definition
Mode Register
The mode register is used to define the specific
mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in
Figure 5 on page 12. The mode register is programmed
via the MODE REGISTER SET command (with BA0 = 0
and BA1 = 0) and will retain the stored information
until it is programmed again or the device loses power
(except for bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded)
when all banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of
these requirements will result in unspecified operation.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A13 specify the
operating mode.
Initialization
DDR SDRAMs must be powered up and initialized
in a predefined manner. Operational procedures other
than those specified may result in undefined operation. Power must first be applied to VDD and VDDQ
simultaneously, and then to VREF (and to the system
VTT). VTT must be applied after VDDQ to avoid device
latch-up, which may cause permanent damage to the
device. VREF can be applied any time after VDDQ but is
expected to be nominally coincident with VTT. Except
for CKE, inputs are not recognized as valid until after
VREF is applied. CKE is an SSTL_2 input but will detect
an LVCMOS LOW level after VDD is applied. After CKE
passes through VIH, it will transition to a SSTL 2 signal
and remain as such until power is cycled. Maintaining
an LVCMOS LOW level on CKE during power-up is
required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until
driven in normal operation (by a read access). After all
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11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 5: Mode Register Definition
Burst Length
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being programmable, as shown in Figure 5. The burst length determines the maximum number of column locations that
can be accessed for a given READ or WRITE command.
Burst lengths of 2, 4, or 8 locations are available for
both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-Ai when the burst length is set to two,
by A2-Ai when the burst length is set to four and by A3Ai when the burst length is set to eight (where Ai is the
most significant column address bit for a given configuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
15 14
0* 0*
9
8
7
Operating Mode
6
5
4
3
2
1
0
Mode Register (Mx)
CAS Latency BT Burst Length
* M15 and M14 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Burst Length
M2 M1 M0
M3 = 0
0
0
0
Reserved
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Burst Type
M3
0
Sequential
1
Interleaved
CAS Latency
M6 M5 M4
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 2, Burst
Definition, on page 13.
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Address Bus
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
2.5
1
1
1
Reserved
M13 M12 M11 M10 M9 M8 M7
12
M6-M0
Operating Mode
0
0
0
0
0
0
0
Valid
Normal Operation
0
0
0
0
0
1
0
Valid
Normal Operation/Reset DLL
-
-
-
-
-
-
-
-
All other states reserved
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 2:
Figure 6: CAS Latency
Burst Definition
ORDER OF ACCESSES WITHIN A
BURST
BURST
LENGTH
STARTING
COLUMN
ADDRESS
2
NOTE:
TYPE=
INTERLEAVED
0
0-1
0-1
1
1-0
1-0
T1
T2
READ
NOP
NOP
T3
T3n
NOP
CL = 2
A1
A0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A2
A1
A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
DQS
DQ
CK#
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK
COMMAND
NOP
CL = 2.5
DQS
DQ
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDQSCK
TRANSITIONING DATA
1. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
Table 3:
2. For a burst length of two, A1-Ai select the twodata-element block; A0 selects the first access
within the block.
DON’T CARE
CAS Latency (CL)
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
3. For a burst length of four, A2-Ai select the fourdata-element block; A0-A1 select the first access
within the block.
SPEED
CL = 2
CL = 2.5
-75
75 £ f £ 100
75 £ f £ 133
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7-A13
each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A13 each set to
zero, bit A8 set to one, and bits A0-A6 set to the desired
values. Although not required by the Micron device,
JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL,
it should always be followed by a LOAD MODE REGISTER command to select normal operating mode.
All other combinations of values for A7-A13 are
reserved for future use and/or test modes. Test modes
and reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
4. For a burst length of eight, A3-Ai select the eightdata-element block; A0-A2 select the first access
within the block.
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2, or 2.5 clocks, as shown in Figure 6.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 3
indicates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
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T2n
CK
COMMAND
A0
4
8
TYPE=
SEQUENTIAL
T0
CK#
13
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©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Extended Mode Register
during power-up initialization and upon returning to
normal operation after having disabled the DLL for the
purpose of debug or evaluation. (When the device
exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable, and output drive strength. These functions are controlled via
the bits shown in Figure 7. The extended mode register
is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when
all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating any subsequent operation. Violating either of these
requirements could result in unspecified operation.
Figure 7: Extended Mode Register
Definition
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
15 14 13 12 11 10 9 8 7 6 5
Operating Mode
01 11
4
3
2
1
0
Extended Mode
Register (Ex)
DS DLL
E0
DLL
0
Enable
1
Disable
E12
Output Drive Strength
The normal drive strength for all outputs are specified to be SSTL_2, Class II. The x16 supports a programmable option for reduced drive. This option is
intended for the support of the lighter load and/or
point-to-point environments. The selection of the
reduced drive strength will alter the DQ pins and DQS
pins from SSTL_2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of
the SSTL_2, Class II drive strength.
E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2
Drive Strength
0
Normal
1
Reduced
Operating Mode
0
0
0
0
0
0
0
0
0
0
0
0
Valid
Reserved
–
–
–
–
–
–
–
–
–
–
–
–
–
Reserved
NOTE:
1. E15 and E14 (BA1 and BA0) must be “0, 1” to
select the Extended Mode Register vs. the base
Mode Register.
2. The reduced drive strength option is not supported on the x4 and x8 versions, and is only
available on the x16 version.
DLL Enable/Disable
When the part is running without the DLL enabled,
device functionality may be altered. The DLL must be
enabled for normal operation. DLL enable is required
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E1, E0
Address Bus
3. The QFC# option is not supported.
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Commands
Table 4 and Table 5 provide a quick reference of
available commands. This is followed by a verbal
description of each command. Two additional Truth
Table 4:
Tables, Table 7 on page 41, and Table 8 on page 43,
appear following the Operation section, provide current state/next state information.
Truth Table – Commands
Note 1 applies to all commands
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
CS#
RAS#
CAS#
WE#
ADDR
NOTES
H
L
L
L
L
L
L
L
X
H
L
H
H
H
L
L
X
H
H
L
L
H
H
L
X
H
H
H
L
L
L
H
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
9
9
3
4
4
8
5
6, 7
L
L
L
L
Op-Code
2
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A13 provide the op-code to
be written to the selected mode register.
3. BA0-BA1 provide bank address and A0-A13 provide row address.
4. BA0-BA1 provide bank address; A0-Ai provide column address, (where i=9 for x16, i=9, 11 for x8, and i=9,11, 12 for x4) A10 HIGH
enables the auto precharge feature (non persistent), and A10 LOW disables the auto precharge feature.
5. A10 LOW: BA0-BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; for within the Self Refresh mode all inputs and I/Os are “Don’t Care” except
for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts
with auto precharge enabled and for write bursts.
9. DESELECT and NOP are functionally interchangeable.
Table 5:
Truth Table – DM Operation
Note 1 applies to all commands
NAME (FUNCTION)
DM
DQ
Write Enable
Write Inhibit
L
H
Valid
X
NOTE:
1. Used to mask write data; provided coincident with the corresponding data.
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15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
DESELECT
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
WRITE burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Input data
appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered
LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will
not be executed to that byte/column location.
The DESELECT function (CS# HIGH) prevents new
commands from being executed by the DDR SDRAM.
The DDR SDRAM is effectively deselected. Operations
already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
instruct the selected DDR SDRAM to perform a NOP
(CS# is LOW with RAS#, CAS#, and WE# equal HIGH).
This prevents unwanted commands from being registered during idle or wait states. Operations already in
progress are not affected.
PRECHARGE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0–A13 selects the row.
This row remains active (or open) for accesses until a
precharge command is issued to that bank. A precharge command must be issued before opening a different row in the same bank.
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (tRP) after the precharge
command is issued. Except in the case of concurrent
auto precharge, where a READ or WRITE command to
a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not
violate any other timing parameters. Input A10 determines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise
BA0, BA1 are treated as “Don’t Care.” Once a bank has
been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command
will be treated as a NOP if there is no open row in that
bank (idle state), or if the previously open row is
already in the process of precharging.
READ
Auto Precharge
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0–Ai (where i = 9 for x16; 9, 11 for x8; or 9, 11,
12 for x4) selects the starting column location. The
value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row
will remain open for subsequent accesses.
Auto precharge is a feature which performs the
same individual-bank precharge function described
above, but without requiring an explicit command.
This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is
addressed with the READ or WRITE command is automatically performed upon completion of the READ or
WRITE burst. Auto precharge is nonpersistent in that it
is either enabled or disabled for each individual Read
or Write command. This device supports concurrent
auto precharge if the command to the other bank does
not interrupt the data transfer to the current bank.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This “earliest valid stage” is determined as if an explicit
PRECHARGE command was issued at the earliest possible time, without violating tRAS (MIN), as described
LOAD MODE REGISTER
The mode registers are loaded via inputs A0–A13.
See mode register descriptions in the Register Definition section. The LOAD MODE REGISTER command
can only be issued when all banks are idle, and a subsequent executable command cannot be issued until
t
MRD is met.
ACTIVE
WRITE
The WRITE command is used to initiate a burst
write access to an active row. The value on the BA0,
BA1 inputs selects the bank, and the address provided
on inputs A0–Ai (where i = 9 for x16; 9, 11 for x8; or 9,
11, 12 for x4) selects the starting column location. The
value on input A10 determines whether or not auto
09005aef8076894f
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16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
for each burst type in the Operation section of this
data sheet. The user must not issue another command
to the same bank until the precharge time (tRP) is
completed.
JEDEC requirement by one clock. This maximum
absolute interval is to allow future support for DLL
updates internal to the DDR SDRAM to be restricted to
AUTO REFRESH cycles, without allowing excessive
drift in tAC between updates.
Although not a JEDEC requirement, to provide for
future functionality features, CKE must be active
(High) during the AUTO REFRESH period. The AUTO
REFRESH period begins when the AUTO REFRESH
command is registered and ends tRFC later.
BURST TERMINATE
The BURST TERMINATE command is used to truncate read bursts (with auto precharge disabled). The
most recently registered READ command prior to the
BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet. The
open page which the READ burst was terminated from
remains open.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled
(LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon
exiting SELF REFRESH (A DLL reset and 200 clock
cycles must then occur before a READ command can
be issued). Input signals except CKE are “Don’t Care”
during SELF REFRESH. VREF voltage is also required
for the SELF REFRESH full duration.
The procedure for exiting self refresh requires a
sequence of commands. First, CK and CK# must be
stable prior to CKE going back HIGH. Once CKE is
HIGH, the DDR SDRAM must have NOP commands
issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple
algorithm for meeting both refresh and DLL requirements is to apply NOPs for tXSNR time, then a DLL
Reset and NOPs for 200 additional clock cycles before
applying any other command.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the DDR SDRAM and is analogous to CAS#-BEFORERAS# (CBR) refresh in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time
a refresh is required. All banks must be idle before an
AUTO REFRESH command is issued.
The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care”
during an AUTO REFRESH command. The 1Gb DDR
SDRAM requires AUTO REFRESH cycles at an average
interval of 7.8125µs (maximum).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight
AUTO REFRESH commands can be posted to any
given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command
and the next AUTO REFRESH command is 9 x 7.8125µs
(70.3µs). Note the JEDEC specifications only allows 8 x
7.8125µs, thus the Micron specification exceeds the
09005aef8076894f
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17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Operations
Bank/Row Activation
Before any READ or WRITE commands can be
issued to a bank within the DDR SDRAM, a row in that
bank must be “opened.” This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 8.
After a row is opened with an ACTIVE command, a
READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock
edge after the ACTIVE command on which a READ or
WRITE command can be entered. For example, a tRCD
specification of 20ns with a 133 MHz clock (7.5ns
period) results in 2.7 clocks rounded to 3. This is
reflected in Figure 9, which covers any case where 2 <
t
RCD (MIN)/tCK £ 3. (Figure 9 also shows the same
case for tRCD; the same procedure is used to convert
other specification limits from time units to clock
cycles).
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access overhead. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t
RRD.
Figure 9: Example: Meeting tRCD (tRRD)
T0
T1
ACT
NOP
T2
Figure 8: Activating a Specific Row in a
Specific Bank
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0-A13
RA
BA0, BA1
BA
RA = Row Address
BA = Bank Address
MIN When 2 < tRCD (tRRD) MIN/tCK£3
T3
T4
T5
T6
T7
NOP
NOP
RD/WR
NOP
CK#
CK
COMMAND
A0-A13
BA0, BA1
NOP
Row
ACT
Row
Bank x
Col
Bank y
Bank y
tRCD
tRRD
DON’T CARE
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18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
READs
command, where x equals the number of desired data
element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 12 on page 22. A
READ command can be initiated on any clock cycle
following a previous READ command. Nonconsecutive
read data is shown for illustration in Figure 13 on
page 23. Full-speed random read accesses within a
page (or pages) can be performed as shown in
Figure 14 on page 24.
Data from any READ burst may be truncated with a
BURST TERMINATE command, as shown in Figure 15
on page 25. The BURST TERMINATE latency is equal
to the read (CAS) latency, i.e., the BURST TERMINATE
command should be issued x cycles after the READ
command, where x equals the number of desired data
element pairs (pairs are required by the 2n-prefetch
architecture).
Data from any READ burst must be completed or
truncated before a subsequent WRITE command can
be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in
Figure 16 on page 26. The tDQSS (NOM) case is shown;
the tDQSS (MAX) case has a longer bus idle time.
(tDQSS [MIN] and tDQSS [MAX] are defined in the section on WRITEs.)
A READ burst may be followed by, or truncated with,
a PRECHARGE command to the same bank provided
that auto precharge was not activated. The PRECHARGE command should be issued x cycles after the
READ command, where x equals the number of
desired data element pairs (pairs are required by the
2n-prefetch architecture). This is shown in Figure 17
on page 27. Following the PRECHARGE command, a
subsequent command to the same bank cannot be
issued until both tRAS and tRP has been met. Note that
part of the row precharge time is hidden during the
access of the last data elements.
READ bursts are initiated with a READ command, as
shown in Figure 10 on page 20.
The starting column and bank addresses are provided with the READ command and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is precharged at the completion of the burst.
NOTE:
For the READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available following the CAS latency after the READ command.
Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (i.e., at
the next crossing of CK and CK#). Figure 11 on page 21
shows general timing for each possible CAS latency
setting. DQS is driven by the DDR SDRAM along with
output data. The initial LOW state on DQS is known as
the read preamble; the LOW state coincident with the
last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other
commands have been initiated, the DQs will go HighZ. A detailed explanation of tDQSQ (valid data-out
skew), tQH (data-out window hold), the valid data window are depicted in Figure 38 on page 60 and Figure 39
on page 61. A detailed explanation of tDQSCK (DQS
transition skew to CK) and tAC (data-out transition
skew to CK) is depicted in Figure 40 on page 62.
Data from any READ burst may be concatenated
with or truncated with data from a subsequent READ
command. In either case, a continuous flow of data
can be maintained. The first data element from the
new burst follows either the last element of a completed burst or the last desired data element of a longer
burst which is being truncated. The new READ command should be issued x cycles after the first READ
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 10: READ Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
x4: A0–A9, A11, A12
x8: A0–A9, A11
x16: A0–A9
x4: A13
x8: A12, A13
x16: A11, A12, A13
CA
EN AP
A10
DIS AP
BA0,1
BA
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON’T CARE
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 11: READ Burst
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
T4
T5
NOP
NOP
T4
T5
NOP
NOP
CK#
CK
COMMAND
ADDRESS
NOP
Bank a,
Col n
CL = 2
DQS
DO
n
DQ
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK#
CK
COMMAND
ADDRESS
NOP
Bank a,
Col n
CL = 2.5
DQS
DO
n
DQ
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DO n = data-out from column n.
2. Burst length = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
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21
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 12: Consecutive READ Bursts
T0
T1
T2
COMMAND
READ
NOP
READ
ADDRESS
Bank,
Col n
T2n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
NOP
NOP
NOP
Bank,
Col b
CL = 2
DQS
DO
n
DQ
T0
T1
T2
COMMAND
READ
NOP
READ
ADDRESS
Bank,
Col n
DO
b
T2n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
NOP
NOP
NOP
Bank,
Col b
CL = 2.5
DQS
DO
n
DQ
DO
b
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DO n (or b) = data-out from column n (or column b).
2.
3.
4.
5.
6.
Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).
Three subsequent elements of data-out appear in the programmed order following DO n.
Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Example applies only when READ commands are issued to same device.
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 13: Nonconsecutive READ Bursts
T0
T1
T2
COMMAND
READ
NOP
NOP
ADDRESS
Bank,
Col n
T2n
T3
T3n
T4
T5
NOP
NOP
T5n
T6
CK#
CK
READ
NOP
Bank,
Col b
CL = 2
DQS
DO
n
DQ
T0
T1
T2
COMMAND
READ
NOP
NOP
ADDRESS
Bank,
Col n
DO
b
T2n
T3
T3n
T4
T5
NOP
NOP
T5n
T6
CK#
CK
READ
NOP
Bank,
Col b
CL = 2.5
DQS
DO
n
DQ
DO
b
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DO n (or b) = data-out from column n (or column b).
2.
3.
4.
5.
6.
Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).
Three subsequent elements of data-out appear in the programmed order following DO n.
Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Example applies when READ commands are issued to different devices or nonconsecutives READS
09005aef8076894f
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©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 14: Random READ Accesses
T0
T1
T2
T2n
T3
T3n
T4
COMMAND
READ
READ
READ
READ
ADDRESS
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
T4n
T5
T5n
CK#
CK
NOP
NOP
CL = 2
DQS
DO
n
DQ
DO
n'
T2n
DO
x
T0
T1
T2
T3
COMMAND
READ
READ
READ
READ
ADDRESS
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
DO
x'
T3n
DO
b
T4
DO
b'
T4n
DO
g
T5
T5n
CK#
CK
NOP
NOP
CL = 2.5
DQS
DO
n
DQ
DO
n'
DO
x
DON’T CARE
DO
x'
DO
b
DO
b'
TRANSITIONING DATA
NOTE:
1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
2.
3.
4.
5.
Burst length = 2, 4 or 8 (if 4 or 8, the following burst interrupts the previous).
n' or x' or b' or g' indicates the next data-out following DO n or DO x or DO b or DO g, respectively.
READs are to an active row in any bank.
Shown with nominal tAC, tDQSCK, and tDQSQ.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 15: Terminating a READ Burst
T0
T1
T2
READ
BST5
NOP
T2n
T3
T4
T5
NOP
NOP
NOP
T3
T4
T5
NOP
NOP
NOP
CK#
CK
COMMAND
ADDRESS
Bank a,
Col n
CL = 2
DQS
DO
n
DQ
T0
T1
T2
READ
BST5
NOP
T2n
CK#
CK
COMMAND
ADDRESS
Bank a,
Col n
CL = 2.5
DQS
DO
n
DQ
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DO n = data-out from column n.
2.
3.
4.
5.
Burst length = 4.
Subsequent element of data-out appears in the programmed order following DO n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
BST = BURST TERMINATE command, page remains open.
09005aef8076894f
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 16: READ to WRITE
T0
T1
T2
COMMAND
READ
BST7
NOP
ADDRESS
Bank,
Col n
T2n
T3
T4
T4n
T5
T5n
CK#
CK
WRITE
NOP
NOP
Bank,
Col b
tDQSS
(NOM)
CL = 2
DQS
DO
n
DQ
DI
b
DM
T0
T1
T2
READ
BST7
NOP
T2n
T3
T4
T5
T5n
CK#
CK
COMMAND
ADDRESS
NOP
WRITE
NOP
Bank a,
Col n
tDQSS
(NOM)
CL = 2.5
DQS
DI
b
DO
n
DQ
DM
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DO n = data-out from column n.
2.
3.
4.
5.
6.
7.
DI b = data-in from column b.
Burst length = 4 in the cases shown (applies for bursts of 8 as well; if the burst length is 2, the BST command shown can be NOP).
One subsequent element of data-out appears in the programmed order following DO n.
Data-in elements are applied following DI b in the programmed order.
Shown with nominal tAC, tDQSCK, and tDQSQ.
BST = BURST TERMINATE command, page remains open.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 17: READ to PRECHARGE
T0
T1
T2
READ
NOP
PRE
T2n
T3
T3n
T4
T5
NOP
ACT
CK#
CK
COMMAND6
ADDRESS
Bank a,
Col n
NOP
Bank a,
(a or all)
Bank a,
Row
tRP
CL = 2
DQS
DO
n
DQ
T0
T1
T2
READ
NOP
PRE
T2n
T3
T3n
T4
T5
NOP
ACT
CK#
CK
COMMAND6
ADDRESS
Bank a,
Col n
NOP
Bank a,
(a or all)
Bank a,
Row
tRP
CL = 2.5
DQS
DO
n
DQ
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DO n = data-out from column n.
2.
3.
4.
5.
6.
Burst length = 4, or an interrupted burst of 8.
Three subsequent elements of data-out appear in the programmed order following DO n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
READ to PRECHARGE equals two clocks, which allows two data pairs of data-out.
A READ command with AUTO-PRECHARGE enabled, provided tRAS(min) is met, would cause a precharge to be performed at x
number of clock cycles after the READ command, where x = BL / 2.
7. PRE = PRECHARGE command; ACT = ACTIVE command.
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
WRITEs
Figure 18: WRITE Command
WRITE bursts are initiated with a WRITE command,
as shown in Figure 18.
The starting column and bank addresses are provided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is precharged at the completion of the burst and after the
t
WR time.
NOTE:
CK#
CK
CKE
CS#
RAS#
For the WRITE commands used in the following illustrations, auto precharge is disabled.
CAS#
During WRITE bursts, the first valid data-in element
will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS.
The LOW state on DQS between the WRITE command
and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in
element is known as the write postamble.
The time between the WRITE command and the
first corresponding rising edge of DQS (tDQSS) is
specified with a relatively wide range (from 75 percent to 125 percent of one clock cycle). All of the
WRITE diagrams show the nominal case, and where
the two extreme cases (i.e., tDQSS [MIN] and tDQSS
[MAX]) might not be intuitive, they have also been
included. Figure 19 on page 29 shows the nominal
case and the extremes of tDQSS for a burst of 4.
Upon completion of a burst, assuming no other
commands have been initiated, the DQ will remain
High-Z and any additional input data will be
ignored.
Data for any WRITE burst may be concatenated
with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data
can be maintained. The new WRITE command can be
issued on any positive edge of clock following the previous WRITE command. The first data element from
the new burst is applied after either the last element of
a completed burst or the last desired data element of a
longer burst which is being truncated. The new WRITE
command should be issued x cycles after the first
WRITE command, where x equals the number of
desired data element pairs (pairs are required by the
2n-prefetch architecture).
Figure 20 on page 30 shows concatenated bursts of
4. An example of nonconsecutive WRITEs is shown in
Figure 21 on page 31. Full-speed random write
accesses within a page or pages can be performed as
shown in Figure 22 on page 32.
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1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
HIGH
WE#
x4: A0–A9, A11, A12
x8: A0–A9, A11
x16: A0–A9
x4: A13
x8: A13
x16: A11, A12, A13
CA
EN AP
A10
DIS AP
BA0,1
BA
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON’T CARE
Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without
truncating the WRITE burst, tWTR should be met as
shown in Figure 23 on page 33.
Data for any WRITE burst may be truncated by a
subsequent READ command, as shown in Figure 24 on
page 34.
Note that only the data-in pairs that are registered
prior to the tWTR period are written to the internal
array, and any subsequent data-in should be masked
with DM as shown in Figure 25 on page 35.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE
without truncating the WRITE burst, tWR should be
met as shown in Figure 26 on page 36.
Data for any WRITE burst may be truncated by a
subsequent PRECHARGE command, as shown in
Figure 27 on page 37 and Figure 28 on page 38. Note
that only the data-in pairs that are registered prior to
the tWR period are written to the internal array, and
any subsequent data-in should be masked with DM as
shown in Figures 27 and 28. After the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until tRP is met.
28
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 19: WRITE Burst
T0
T1
T2
COMMAND
WRITE
NOP
NOP
ADDRESS
Bank a,
Col b
T2n
T3
CK#
CK
NOP
tDQSS (NOM)
DQS
tDQSS
DI
b
DQ
DM
tDQSS (MIN)
DQS
DQ
tDQSS
DI
b
DM
tDQSS (MAX)
DQS
DQ
tDQSS
DI
b
DM
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 20: Consecutive WRITE to WRITE
T0
T1
COMMAND
WRITE
NOP
ADDRESS
Bank,
Col b
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CK#
CK
tDQSS (NOM)
WRITE
NOP
NOP
NOP
Bank,
Col n
tDQSS
DQS
DQ
DI
b
DI
n
DM
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI b, etc. = data-in for column b, etc.
2.
3.
4.
5.
Three subsequent elements of data-in are applied in the programmed order following DI b.
Three subsequent elements of data-in are applied in the programmed order following DI n.
An uninterrupted burst of 4 is shown.
Each WRITE command may be to any bank.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 21: Nonconsecutive WRITE to WRITE
T0
T1
COMMAND
WRITE
NOP
ADDRESS
Bank,
Col b
T1n
T2
T2n
T3
T4
T4n
T5
T5n
CK#
CK
tDQSS (NOM)
NOP
WRITE
NOP
NOP
Bank,
Col n
tDQSS
DQS
DQ
DI
n
DI
b
DM
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI b, etc. = data-in for column b, etc.
2.
3.
4.
5.
Three subsequent elements of data-in are applied in the programmed order following DI b.
Three subsequent elements of data-in are applied in the programmed order following DI n.
An uninterrupted burst of 4 is shown.
Each WRITE command may be to any bank.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 22: Random WRITE Cycles
T0
T1
T1n
T2
T2n
T3
T3n
T4
COMMAND
WRITE
WRITE
WRITE
WRITE
WRITE
ADDRESS
Bank,
Col b
Bank,
Col x
Bank,
Col n
Bank,
Col a
Bank,
Col g
T4n
T5
T5n
CK#
CK
NOP
tDQSS (NOM)
DQS
DQ
DI
b
DI
b'
DI
x
DI
x'
DI
n
DI
n'
DI
a
DI
a'
DI
g
DI
g'
DM
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI b, etc. = data-in for column b, etc.
2. b', etc. = the next data-in following DI b, etc., according to the programmed burst order.
3. Programmed burst length = 2, 4, or 8 in cases shown.
4. Each WRITE command may be to any bank.
09005aef8076894f
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 23: WRITE to READ - Uninterrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
T6
T6n
READ
NOP
NOP
CK#
CK
COMMAND
NOP
NOP
tWTR
ADDRESS
tDQSS (NOM)
Bank a,
Col b
Bank a,
Col n
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
tDQSS (MIN)
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
tDQSS (MAX)
tDQSS
CL = 2
DQS
DQ
DI
b
DO
n
DM
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI b = data-in for column b, DO n = data-out for column n.
2.
3.
4.
5.
Three subsequent elements of data-in are applied in the programmed order following DI b.
An uninterrupted burst of 4 is shown.
t
WTR is referenced from the first positive CK edge after the last data-in pair.
The READ and WRITE commands are to same device. However, the READ and WRITE commands may be to different devices, in
which case tWTR is not required and the READ command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 24: WRITE to READ - Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T5
NOP
NOP
T5n
T6
T6n
CK#
CK
COMMAND
NOP
READ
NOP
tWTR
ADDRESS
Bank a,
Col b
tDQSS (NOM)
Bank a,
Col n
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
tDQSS (MIN)
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
tDQSS (MAX)
tDQSS
CL = 2
DQS
DQ
DI
b
DO
n
DM
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI b = data-in for column b, DO n = data-out for column n.
2.
3.
4.
5.
6.
7.
An interrupted burst of 4 is shown; two data elements are written.
One subsequent element of data-in is applied in the programmed order following DI b.
tWTR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T2 and T2n (nominal case) to register DM.
If the burst of 8 was used, DM and DQS would be required at T3 and T3n because the READ command would not mask these
two data elements.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 25: WRITE to READ - Odd Number of Data, Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T5
NOP
NOP
T5n
T6
T6n
CK#
CK
COMMAND
NOP
READ
NOP
tWTR
ADDRESS
tDQSS (NOM)
Bank a,
Col b
Bank a,
Col n
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
tDQSS (MIN)
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
tDQSS (MAX)
tDQSS
CL = 2
DQS
DQ
DI
b
DO
n
DM
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI b = data-in for column b, DO n = data-out for column n.
2.
3.
4.
5.
6.
An interrupted burst of 4 is shown; one data element is written.
WTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements).
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T1n, T2, and T2n (nominal case) to register DM.
If the burst of 8 was used, DM and DQS would be required at T3 - T3n because the READ command would not mask these data
elements.
t
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 26: WRITE to PRECHARGE - Uninterrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
NOP
PRE7
T6
CK#
CK
COMMAND
NOP
NOP
tWR
ADDRESS
tDQSS (NOM)
Bank a,
Col b
NOP
tRP
Bank,
(a or all)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MIN)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MAX)
tDQSS
DQS
DQ
DI
b
DM
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI b = data-in for column b.
2.
3.
4.
5.
Three subsequent elements of data-in are applied in the programmed order following DI b.
An uninterrupted burst of 4 is shown.
tWR is referenced from the first positive CK edge after the last data-in pair.
The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE commands may be to different devices, in which case tWR is not required and the PRECHARGE command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. PRE = PRECHARGE command.
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 27: WRITE to Precharge – Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
CK#
CK
COMMAND
NOP
NOP
PRE8
tWR
ADDRESS
Bank a,
Col b
tDQSS (NOM)
NOP
NOP
tRP
Bank,
(a or all)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MIN)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MAX)
tDQSS
DQS
DQ
DI
b
DM
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI b = data-in for column b.
2.
3.
4.
5.
6.
7.
8.
Subsequent element of data-in is applied in the programmed order following DI b.
An interrupted burst of 8 is shown; two data elements are written.
t
WR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T4 and T4n (nominal case) to register DM.
If the burst of 4 was used, DQS and DM would not be required at T3, T3n, T4 and T4n.
PRE = PRECHARGE command.
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 28: WRITE to PRECHARGE Odd Number of Data, Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
CK#
CK
COMMAND
NOP
NOP
PRE7
tWR
ADDRESS
Bank a,
Col b
tDQSS (NOM)
NOP
NOP
tRP
Bank,
(a or all)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MIN)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MAX)
tDQSS
DQS
DQ
DI
b
DM
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI b = data-in for column b.
2.
3.
4.
5.
6.
7.
An interrupted burst of 8 is shown; one data element is written.
WR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T4 and T4n (nominal case) to register DM.
If the burst of 4 was used, DQS and DM would not be required at T3, T3n, T4 and T4n.
PRE = PRECHARGE command.
t
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
PRECHARGE
Power-down (CKE Not Active)
The PRECHARGE command as shown in Figure 29,
is used to deactivate the open row in a particular bank
or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time
(tRP) after the PRECHARGE command is issued. Input
A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are
treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.
Unlike SDR SDRAMs, DDR SDRAMs require CKE to
be active at all times an access is in progress, from the
issuing of a READ or WRITE command until completion of the access. Thus a clock suspend is not supported. For READs, an access completion is defined
when the Read Postamble is satisfied; for WRITEs, an
access completion is defined when the Write Recovery
time (tWR) is satisfied.
Power-down as shown in Figure 30 on page 40, is
entered when CKE is registered LOW and all Table 6
(page 40)criteria are met. If power-down occurs when
all banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates
the input and output buffers, excluding CK, CK#, and
CKE. For maximum power savings, the DLL is frozen
during precharge power-down mode. Exiting powerdown requires the device to be at the same voltage and
frequency as when it entered power-down. However,
power-down duration is limited by the refresh requirements of the device (tREFC).
While in power-down, CKE LOW and a stable clock
signal must be maintained at the inputs of the DDR
SDRAM, while all other input signals are “Don’t Care.”
The power-down state is synchronously exited when
CKE is registered HIGH (in conjunction with a NOP or
DESELECT command). A valid executable command
may be applied one clock cycle later.
Figure 29: PRECHARGE Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A9, A11, A12, A13
ALL BANKS
A10
ONE BANK
BA0,1
BA
BA = Bank Address (if A10 is LOW;
otherwise “Don’t Care”)
DON’T CARE
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 30: Power-Down
T0
T1
CK#
T2 ( (
Ta0
Ta1
Ta2
))
((
))
CK
tIS
tIS
CKE
((
))
COMMAND
VALID
No READ/WRITE
access in progress
NOP
((
))
((
))
NOP
NOP
VALID
Exit power-down mode
Enter power-down mode
DON’T CARE
Table 6:
Truth Table – CKE
Notes: 1-6
CKEn-1
CKEn CURRENT STATE
L
L
L
H
H
L
H
H
Power-Down
Self Refresh
Power-Down
Self Refresh
All Banks Idle
Bank(s) Active
All Banks Idle
COMMANDn
ACTIONn
X
X
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTO REFRESH
See Table 7 on page 41
Maintain Power-Down
Maintain Self Refresh
Exit Power-Down
Exit Self Refresh
Precharge Power-Down Entry
Active Power-Down Entry
Self Refresh Entry
NOTES
6
NOTE:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2.
3.
4.
5.
Current state is the state of the DDR SDRAM immediately prior to clock edge n.
COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
All states and sequences not shown are illegal or reserved.
CKE must not drop low during a column access. For a READ, this means CKE must stay high until after the Read Postamble time;
for a WRITE, CKE must stay high until the WRITE Recovery Time (tWR) has been met.
6. Upon exit of the Self Refresh mode the DLL is automatically enabled, but a DLL Reset must still occur. A minimum of 200 clock
cycles is needed before applying a READ command for the DLL to lock. DESELECT or NOP commands should be issued on any
clock edges occurring during the tXSNR period.
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 7:
Truth Table – Current State Bank n - Command to Bank n
(Notes: 1-6; notes appear below and on next page)
CURRENT
STATE
Any
Idle
Row
Active
Read
(AutoPrecharge
Disabled)
Write
(AutoPrecharge
Disabled)
CS#
RAS# CAS#
WE#
COMMAND/ACTION
H
X
X
X
DESELECT (NOP/continue previous operation)
L
H
H
H
NO OPERATION (NOP/continue previous operation)
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
H
L
H
H
H
L
H
L
L
L
L
H
L
L
H
H
L
L
H
H
H
L
H
L
L
H
L
L
L
H
L
L
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
NOTES
7
7
10
10
8
10
10, 12
8
9
10, 11
10
8, 11
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 6 on page 40) and after tXSNR has been met (if
the previous state was self refresh).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those
allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands
to the other bank are determined by its current state and Table 7, Truth Table – Current State Bank n - Command to Bank n, on
page 41 and according to Table 8, Truth Table – Current State Bank n - Command to Bank m, on page 43.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the
bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met,
the bank will be in the “row active” state.
Read w/AutoPrecharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when
t
RP has been met. Once tRP is met, the bank will be in the idle state.
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Write w/AutoPrecharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when
t
RP has been met. Once tRP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be
applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is
met, the DDR SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met.
Once tMRD is met, the DDR SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is
met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
10.READs or WRITEs listed in the Command/Action column include Reads or Writes with auto precharge enabled and READs or
WRITEs with auto precharge disabled.
11.Requires appropriate DM masking.
12.A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to
end the READ burst prior to asserting a WRITE command.
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 8:
Truth Table – Current State Bank n - Command to Bank m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE
CS#
RAS#
CAS#
WE#
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
Any
Idle
Row
Activating,
Active, or
Precharging
Read
(AutoPrecharge
Disabled)
Write
(AutoPrecharge
Disabled)
Read
(With AutoPrecharge)
Write
(With AutoPrecharge)
COMMAND/ACTION
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
NOTES
7
7
7
7, 9
7, 8
7
7, 3a
7, 9, 3a
7, 3a
7, 3a
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been met (if the
previous state was self refresh).
2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable).
Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write:A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated
Read with Auto Precharge Enabled: See following text – 3a
Write with Auto Precharge Enabled: See following text – 3a
a. The read with auto precharge enabled or write with auto precharge enabled states can each
be broken into two parts: the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge
disabled and then followed with the earliest possible PRECHARGE command that still accesses
all of the data in the burst. For write with auto precharge, the precharge period begins when
t
WR ends, with tWR measured as if auto precharge was disabled. The access period starts with
registration of the command and ends where the precharge period (or tRP) begins.
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
This device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled any command to other
banks is allowed, as long as that command does not interrupt the read or write data
transfer already in process. In either case, all other related limitations apply (e.g., contention between read data and write data must be avoided).
b. The minimum delay from a read or write command with auto precharge enabled, to a command to a different bank is summarized below.
FROM COMMAND
TO COMMAND
MINIMUM DELAY
(WITH CONCURRENT AUTO PRECHARGE)
WRITE w/AP
READ or READ w/AP
[1 + (BL/2)] * tCK + tWTR
WRITE or WRITE w/AP
(BL/2) * tCK
PRECHARGE
1 tCK
ACTIVE
1 tCK
READ or READ w/AP
(BL/2) * tCK
WRITE or WRITE w/AP
[CLRU + (BL/2)] *tCK
PRECHARGE
1 tCK
ACTIVE
1 tCK
READ w/AP
NOTE:
CLRU = CAS Latency (CL) rounded up to the next integer
BL = Bust Length
4.
5.
6.
7.
AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
All states and sequences not shown are illegal or reserved.
READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or
WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to
end the READ burst prior to asserting a WRITE command.
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Relative to VSS ..............................................-1V to +3.6V
VREF and Inputs Voltage
Relative to VSS ..............................................-1V to +3.6V
I/O Pins Voltage
Relative to VSS ................................ -0.5V to VDDQ +0.5V
Operating Temperature, TA
(ambient, Commercial)............................... 0°C to +70°C
Storage Temperature (plastic) ...............-55°C to +150°C
Power Dissipation........................................................ 1W
Short Circuit Output Current .................................50mA
VDD Supply Voltage
Relative to Vss ............................................... -1V to +3.6V
VDDQ Supply Voltage
Table 9:
DC Electrical Characteristics and Operating Conditions
0°C £ TA £ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 1–5, 16, notes appear on page 54-57
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
VDD
VDDQ
2.3
2.3
2.7
2.7
V
V
VREF
VTT
VIH(DC)
VIL(DC)
II
0.49 x VDDQ
0.51 x VDDQ
V
36, 41,
36, 41,
44
6, 44
VREF - 0.04
VREF + 0.15
VREF + 0.04
VDD + 0.3
VREF - 0.15
V
V
7, 44
28
V
µA
28
2
IOZ
-5
5
µA
IOH
-16.8
-
mA
IOL
16.8
-
mA
IOHR
-9
-
mA
IOLR
9
-
mA
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
INPUT LEAKAGE CURRENT
Any input 0V £ VIN £ VDD, VREF PIN 0V £ VIN £ 1.35V
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V £ VOUT £ VDDQ)
OUTPUT LEVELS: Full drive option - x4, x8, x16
High Current (VOUT = VDDQ - 0.373V, minimum VREF,
minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF,
maximum VTT)
OUTPUT LEVELS: Reduced drive option - x16 only
High Current (VOUT = VDDQ - 0.763V, minimum VREF,
minimum VTT)
Low Current (VOUT = 0.763V, maximum VREF,
maximum VTT)
-0.3
-2
37, 39
38, 39
Table 10: AC Input Operating Conditions
0°C £ TA £ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 1–5, 14, 16, notes appear on page 54-57
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
VIH(AC)
VIL(AC)
VREF(AC)
VREF + 0.310
-
-
VREF - 0.310
0.51 x VDDQ
V
V
14, 28, 40
14, 28, 40
V
6
Input Low (Logic 0) Voltage
I/O Reference Voltage
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0.49 x VDDQ
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 31: Input Voltage Waveform
VDDQ (2.3V minimum)
VOH(MIN) (1.670V1 for SSTL2 termination)
System Noise Margin (Power/Ground,
Crosstalk, Signal Integrity Attenuation)
1.560V
VIHAC
1.400V
VIHDC
1.300V
1.275V
1.250V
1.225V
1.200V
VREF +AC Noise
VREF +DC Error
VREF -DC Error
VREF -AC Noise
1.100V
VILDC
0.940V
VINAC - Provides margin
between VOL (MAX) and VILAC
VILAC
Receiver
VOL (MAX)
(0.83V2 for SSTL2 termination)
Transmitter
NOTE: 1. VOH (MIN) with test load is 1.927V
2. VOL (MAX) with test load is 0.373V
3. Numbers in diagram reflect nomimal
values utilizing circuit below.
VSSQ
VTT
25Ω
25Ω
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1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
46
Reference
Point
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 11: Clock Input Operating Conditions
0°C £ TA £ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 1–5, 15, 16, 30; notes appear on page 54-57
PARAMETER/CONDITION
Clock Input Mid-Point Voltage; CK and CK#
Clock Input Voltage Level; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Crossing Point Voltage; CK and CK#
SYMBOL
MIN
MAX
UNITS
NOTES
VMP(DC)
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
1.15
-0.3
1.35
V
V
6, 9
6
V
V
6, 8
8
V
9
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.5 x VDDQ - 0.2 0.5 x VDDQ + 0.2
0.36
0.7
Figure 32: SSTL_2 Clock Input
2.80V
Maximum Clock Level
5
CK#
X
1.45V
1.05V
3
1
VMP (DC)
1.25V
VIX (AC)
2
VID (DC)
4
VID (AC)
X
CK
Minimum Clock Level
- 0.30V
5
NOTE:
1. This provides a minimum of 1.15V to a maximum of 1.35V, and is always half of VDDQ.
2.
3.
4.
5.
6.
7.
CK and CK# must cross in this region.
CK and CK# must meet at least VID(DC) min when static and is centered around VMP(DC)
CK and CK# must have a minimum 700mv peak to peak swing.
CK or CK# may not be more positive than VDDQ+ 0.3V or more negative than Vss - 0.3V.
For AC operation, all DC clock requirements must also be satisfied.
Numbers in diagram reflect nominal values.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 12: Capacitance (x4, x8)
(Note: 13; notes appear on page 54-57)
PARAMETER
Delta Input/Output Capacitance: DQ0-DQ3 (x4), DQ0-DQ7 (x8)
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, DQS, DM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SYMBOL
MIN
MAX UNITS
NOTES
DCIO
DCI1
DCI2
CIO
CI1
CI2
CI3
–
–
0.50
0.50
pF
pF
24
29
–
4.0
0.25
5.0
pF
pF
29
2.0
2.0
3.0
3.0
pF
pF
2.0
3.0
pF
Table 13: Capacitance (x16)
(Note: 13; notes appear on page 54-57)
PARAMETER
Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM
Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQ, LDQS, UDQS, LDM, UDM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
48
SYMBOL
MIN
MAX
UNITS
NOTES
DCIOL
DCIOU
DCI1
DCI2
CIO
CI1
CI2
CI3
–
0.50
pF
24
–
–
0.50
0.50
pF
pF
24
29
–
4.0
0.25
5.0
pF
pF
29
2.0
3.0
pF
2.0
2.0
3.0
3.0
pF
pF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 14: IDD Specifications and Conditions (x4, x8)
0°C £ TA £ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 1–5, 10, 12, 14; notes appear on page 54-57; See also Table 16, IDD Test Cycle Times, on page 51
MAX
PARAMETER/CONDITION
OPERATING CURRENT: One bank; Active-Precharge;
t
RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs
SYMBOL
-75
UNITS
NOTES
IDD0
145
mA
22, 48
IDD1
180
mA
22, 48
IDD2P
10
mA
23, 32, 50
IDD2F
60
mA
51
IDD3P
30
mA
23, 32, 50
IDD3N
45
mA
22
IDD4R
200
mA
22, 48
IDD4W
210
mA
22
IDD5
IDD5A
IDD6
IDD7
330
10
mA
mA
50
27, 50
9
485
mA
mA
11
22, 49
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address
and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode; tCK = tCK (MIN);
CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;
t
CK = tCK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
t
AUTO REFRESH BURST CURRENT:
RC = tRFC(MIN)
t
SELF REFRESH CURRENT: CKE £ 0.2V
RFC = 7.8us,
Standard
OPERATING CURRENT: Four bank interleaving READs
(Burst = 4) with auto precharge, tRC = minimum tRC allowed;
t
CK = tCK (MIN); Address and control inputs change only during
Active READ, or WRITE commands
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 15: IDD Specifications and Conditions (x16)
0°C £ TA £ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 1–5, 10, 12, 14; notes appear on page 54-57; See also Table 16, IDD Test Cycle Times, on page 51
MAX
PARAMETER/CONDITION
OPERATING CURRENT: One bank; Active-Precharge;
t
RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs
SYMBOL
-75
UNITS
NOTES
IDD0
145
mA
22, 48
IDD1
195
mA
22, 48
IDD2P
10
mA
23, 32, 50
IDD2F
60
mA
51
IDD3P
30
mA
23, 32, 50
IDD3N
45
mA
22
IDD4R
245
mA
22, 48
IDD4W
250
mA
22
IDD5
IDD5A
IDD6
IDD7
330
10
mA
mA
50
27, 50
9
495
mA
mA
11
22, 49
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address
and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode; tCK = tCK (MIN);
CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;
t
CK = tCK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
t
AUTO REFRESH BURST CURRENT:
RC = tRFC(MIN)
t
SELF REFRESH CURRENT: CKE £ 0.2V
RFC = 7.8us,
Standard
OPERATING CURRENT: Four bank interleaving READs
(Burst = 4) with auto precharge, tRC = minimum tRC allowed;
t
CK = tCK (MIN); Address and control inputs change only during
Active READ, or WRITE commands
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 16: IDD Test Cycle Times
Values reflect number of clock cycles for each test.
IDD TEST
IDD0
IDD1
IDD4R
IDD4W
IDD5
IDD5A
IDD7
SPEED
GRADE
CLOCK
CYCLE TIME
t
RRD
t
RCD
RAS
6
t
RP
RC
9
t
RFC
NA
t
REFI
CL
NA
NA
-75
7.5ns
-75
7.5ns
NA
NA
6
3
9
NA
NA
2.5
-75
7.5ns
NA
3
NA
NA
NA
NA
NA
2.5
-75
7.5ns
NA
3
NA
NA
NA
NA
NA
NA
-75
7.5ns
NA
NA
NA
3
NA
16
NA
NA
-75
7.5ns
NA
NA
NA
3
NA
NA
1,030
NA
-75
7.5ns
2/4
3
NA
3
10
NA
NA
2.5
51
3
t
NA
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
NA
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 17: Electrical Characteristics and Recommended AC Operating Conditions
0°C £ TA £ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 1–5, 14–17, 33, notes appear on page 54-57
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
-75
SYMBOL
tAC
tCH
tCL
t
CK (2.5)
t
CK (2)
tDH
tDS
tDIPW
t
DQSCK
t
DQSH
t
DQSL
tDQSQ
tDQSS
tDSS
tDSH
t
HP
t
HZ
tLZ
tIH
F
tIS
F
tIH
S
t
ISS
t
IPW
t
MRD
tQH
CL=2.5
CL=2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (slew rate ³ 1V/ns)
Address and control input setup time (slew rate ³ 1V/ns)
Address and control input hold time (slew rate @ 0.5V/ns)
Address and control input setup time (slew rate @ 0.5V/ns)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
tQHS
Data Hold Skew Factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window (DVW)
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
t
RAS
t
RAP
tRC
tRFC
tRCD
t
RP
t
RPRE
tRPST
tRRD
tWPRE
tWPRES
t
WPST
t
WR
tWTR
N/A
t
REFC
tREFI
t
VTD
t
XSNR
tXSRD
52
MIN
-0.75
0.45
0.45
7.5
10
0.5
0.5
1.75
-0.75
0.35
0.35
0.75
0.2
0.2
t
CH,tCL
MAX
+0.75
0.55
0.55
13
13
+0.75
0.5
1.25
+0.75
-0.75
.90
.90
1
1
2.2
15
tHP
-tQHS
0.75
40
120,000
20
65
120
20
20
0.9
1.1
0.4
0.6
15
0.25
0
0.4
0.6
15
1
tQH - tDQSQ
70.3
7.8
0
127.5
200
UNITS
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CK
tCK
ns
tCK
ns
t
CK
ns
tCK
ns
µs
µs
ns
ns
tCK
NOTES
30
30
45, 52
45, 52
26, 31
26, 31
31
25, 26
34
18,42
18,43
14
14
25, 26
35
50
42
20, 21
19
25
23
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 18: Input Slew Rate Derating Values for Addresses and Commands
0°C £ TA £ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 14; notes appear on page 54-57
SPEED
SLEW RATE
-75
-75
-75
0.500V / ns
0.400V / ns
0.300V / ns
t
t
IS
1.00
1.05
1.15
IH
UNITS
1
1
1
ns
ns
ns
Table 19: Input Slew Rate Derating Values for DQ, DQS, and DM
0°C £ TA £ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 31; notes appear on page 54-57
SPEED
SLEW RATE
-75
-75
-75
0.500V / ns
0.400V / ns
0.300V / ns
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
T
T
DH
UNITS
0.50
0.55
0.60
0.50
0.55
0.60
ns
ns
ns
DS
53
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC
characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for
the full voltage range specified.
3. Outputs (except for IDD measurements) measured
with equivalent load:
11. Enables on-chip refresh and address counters.
12. IDD specifications are tested after the device is
properly initialized, and is averaged at the defined
cycle rate.
13. This parameter is sampled. VDD=+2.5V±0.2V,
VDDQ=+2.5V±0.2V, VREF=VSS, f=100MHz, TA=25°C
VOUT(DC)=VDDQ/2, VOUT (peak to peak)=0.2V.
DM input is grouped with I/O pins, reflecting the
fact that they are matched in loading.
14. For slew rates less than 1V/ns and and greater
than or equal to 0.5V/ns. If the slew rate is less
than 0.5V/ns, timing must be derated: tIS has an
additional 50ps per each 100mV/ns reduction in
slew rate from the 500mV/ns. tIH has 0ps added,
that is, it remains constant. If the slew rate
exceeds 4.5V/ns, functionality is uncertain.
15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is VREF.
16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF
stabilizes, CKE 0.3 x VDDQ is recognized as LOW.
17. The output timing reference level, as measured at
the timing reference point indicated in Note 3, is
VTT.
18. tHZ and tLZ transitions occur in the same access
time windows as data valid transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
19. The intent of the Don’t Care state after completion
of the postamble is the DQS-driven signal should
either be high, low, or high-Z and that any signal
transition within the input switching region must
follow valid input requirements. That is, if DQS
transitions high (above VIHDC(MIN) then it must
not transition low (below VIHDC) prior to
t
DQSH(MIN).
20. This is not a device limit. The device will operate
with a negative value, but system performance
could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on tDQSS.
22. MIN (tRC or tRFC) for IDD measurements is the
smallest multiple of tCK that meets the mini-
VTT
Output
(VOUT)
50Ω
Reference
Point
30pF
4. AC timing and IDD tests may use a VIL-to-VIH
swing of up to 1.5V in the test environment, but
input timing is still referenced to VREF (or to the
crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals used to test
the device is 1V/ns in the range between VIL(AC)
and VIH(AC).
5. The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on VREF may not exceed ±2 percent of the
DC value. Thus, from VDDQ/2, VREF is allowed
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest VREF by-pass capacitor.
7. VTT is not applied directly to the device. VTT is a
system supply for signal termination resistors, is
expected to be set equal to VREF and must track
variations in the DC level of VREF.
8. VID is the magnitude of the difference between
the input level on CK and the input level on CK#.
9. The value of VIX and VMP are expected to equal
VDDQ/2 of the transmitting device and must track
variations in the DC level of the same.
10. IDD is dependent on output loading and cycle
rates. Specified values are obtained with minimum cycle times at CL = 2.5 with the outputs
open.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
23.
24.
25.
26.
mum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the
largest multiple of tCK that meets the maximum absolute value for tRAS.
The refresh period is 64ms. This equates to an
average refresh rate of 7.8125µs. However, an
AUTO REFRESH command must be asserted at
least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
The I/O capacitance per DQS and DQ byte/group
will not differ by more than this maximum
amount for any given device.
The data valid window is derived by achieving
other specifications - tHP (tCK/2), tDQSQ, and
t
QH (tQH = tHP - tQHS). The data valid window
derates in direct proportion to the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55, because functionality
is uncertain when operating beyond a 45/55
ratio. The data valid window derating curves are
provided in Figure 33 for duty cycles ranging
between 50/50 and 45/55.
Referenced to each output group: x4 = DQS with
DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS
with DQ0-DQ7; and UDQS with DQ8-DQ15.
27. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (tRFC [MIN]) else
CKE is LOW (i.e., during standby).
28. To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current
AC level through to the target AC level,
VIL(AC) or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue
to maintain at least the target DC level,
VIL(DC) or VIH(DC).
29. The Input capacitance per pin group will not differ by more than this maximum amount for any
given device.
30. CK and CK# input slew rate must be ³ 1V/ns
(³ 2V/ns if measured differentially).
31. DQ and DM input slew rates must not deviate
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to tDS and
t
DH for each 100mv/ns reduction in slew rate. For
If slew rate exceeds 4V/ns, functionality is uncertain.
32. VDD must not vary more than 4 percent if CKE is
not active while any bank is active.
Figure 33: Derating Data Valid Window (tQH - tDQSQ)
3.8
3.750
3.6
3.700
3.650
3.600
3.550
3.500
3.4
3.450
3.400
3.350
3.300
3.2
3.250
—— -75 @ tCK = 10ns
3.0
ns
—— -75 @ tCK = 7.5ns
2.8
2.6
2.500
2.463
2.425
2.388
2.4
2.350
2.313
2.275
2.238
2.200
2.2
2.163
2.125
2.0
1.8
50/50
49.5/50.5
49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Cl o ck Du ty C y c le
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 34: Full Drive Pull-Down
Characteristics
33. The clock is allowed up to ±150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
34. tHP (MIN) is the lesser of tCL minimum and tCH
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are not
allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command
being issued.
36. Any positive glitch must be less than 1/3 of the
clock cycle and not more than +400mV or 2.9V,
whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed either
-300mV or 2.2V, whichever is more positive.
37. Normal Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 34
b. The variation in driver pull-down current
within nominal limits of voltage and temperature is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 34.
c. The full variation in driver pull-up current
from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 35.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 35.
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature. f ) The
full variation in the ratio of the nominal pullup to pull-down current should be unity ±10
percent, for device drain-to-source voltages
from 0.1V to 1.0V.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
160
140
120
I OUT (mA)
100
80
60
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
Figure 35: Full Drive Pull-Up
Characteristics
0
-20
-40
I OUT (m A)
-60
-80
-100
-120
-140
-160
-180
-200
0.0
0.5
1.0
1.5
2.0
2.5
V DD Q - V OUT (V )
38. Reduced Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 36.
b. The variation in driver pull-down current
within nominal limits of voltage and temperature is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 36.
c. The full variation in driver pull-up current
from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 37.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 37.
56
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
40. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a
pulse width £ 3ns and the pulse width can not
be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width £ 3ns
and the pulse width can not be greater than 1/3
of the cycle rate.
41. VDD and VDDQ must track each other.
42. This maximum value is derived from the referenced test load. In practice, the values obtained in
a typical terminated design may reflect up to
310ps less for tHZ (MAX) and the last DVW. tHZ
(MAX) will prevail over tDQSCK (MAX) + tRPST
(MAX) condition. tLZ (MIN) will prevail over
t
DQSCK (MIN) + tRPRE (MAX) condition.
43. For slew rates of greater than 1V/ns the (LZ) transition will start about 310ps earlier.
44. During initialization, VDDQ, VTT, and VREF must be
equal to or less than VDD + 0.3V. Alternatively, VTT
may be 1.35V maximum during power up, even if
VDD/VDDQ are 0V, provided a minimum of 42W of
series resistance is used between the VTT supply
and the input pin.
45. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
46. Not used.
47. Reserved for future use.
48. Random addressing changing 50 percent of data
changing at every transfer.
49. Random addressing changing 100 percent of data
changing at every transfer.
50. CKE must be active (HIGH) during the entire time
a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
RFC has been satisfied.
51. IDD2N specifies the DQ, DQS and DM to be driven
to a valid high or low logic level. IDD2Q is similar
to IDD2F except IDD2Q specifies the address and
control inputs to remain stable. Although IDD2F,
IDD2N, and IDD2Q are similar, IDD2F is “worst
case.”
52. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset followed by 200 clock cycles before any Read command.
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4 for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
Figure 36: Reduced Drive Pull-Down
Characteristics
80
70
60
IOUT (mA)
50
40
30
20
10
0
0.0
0.5
1.0
1.5
2.
VOUT (V)
Figure 37: Reduced Drive Pull-Up
Characteristics
0
-10
-20
IOUT (mA)
-30
-40
-50
-60
-70
-80
0.0
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
39. The voltage levels used are derived from a minimum VDD level and the referenced test load. In
practice, the voltage levels obtained from a
properly terminated bus will provide significantly different voltage values.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
57
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 20: Normal Output Drive Characteristics
PULL-DOWN CURRENT (mA)
PULL-UP CURRENT (mA)
VOLTAGE
(V)
NOMINAL
LOW
NOMINAL
HIGH
MINIMUM
MAXIMUM
NOMINAL
LOW
NOMINAL
HIGH
MINIMUM
MAXIMUM
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
6.0
12.2
18.1
24.1
29.8
34.6
39.4
43.7
47.5
51.3
54.1
56.2
57.9
59.3
60.1
60.5
61.0
61.5
62.0
62.5
62.8
63.3
63.8
64.1
64.6
64.8
65.0
6.8
13.5
20.1
26.6
33.0
39.1
44.2
49.8
55.2
60.3
65.2
69.9
74.2
78.4
82.3
85.9
89.1
92.2
95.3
97.2
99.1
100.9
101.9
102.8
103.8
104.6
105.4
4.6
9.2
13.8
18.4
23.0
27.7
32.2
36.8
39.6
42.6
44.8
46.2
47.1
47.4
47.7
48.0
48.4
48.9
49.1
49.4
49.6
49.8
49.9
50.0
50.2
50.4
50.5
9.6
18.2
26.0
33.9
41.8
49.4
56.8
63.2
69.9
76.3
82.5
88.3
93.8
99.1
103.8
108.4
112.1
115.9
119.6
123.3
126.5
129.5
132.4
135.0
137.3
139.2
140.8
-6.1
-12.2
-18.1
-24.0
-29.8
-34.3
-38.1
-41.1
-43.8
-46.0
-47.8
-49.2
-50.0
-50.5
-50.7
-51.0
-51.1
-51.3
-51.5
-51.6
-51.8
-52.0
-52.2
-52.3
-52.5
-52.7
-52.8
-7.6
-14.5
-21.2
-27.7
-34.1
-40.5
-46.9
-53.1
-59.4
-65.5
-71.6
-77.6
-83.6
-89.7
-95.5
-101.3
-107.1
-112.4
-118.7
-124.0
-129.3
-134.6
-139.9
-145.2
-150.5
-155.3
-160.1
-4.6
-9.2
-13.8
-18.4
-23.0
-27.7
-32.2
-36.0
-38.2
-38.7
-39.0
-39.2
-39.4
-39.6
-39.9
-40.1
-40.2
-40.3
-40.4
-40.5
-40.6
-40.7
-40.8
-40.9
-41.0
-41.1
-41.2
-10.0
-20.0
-29.8
-38.8
-46.8
-54.4
-61.8
-69.5
-77.3
-85.2
-93.0
-100.6
-108.1
-115.5
-123.0
-130.4
-136.7
-144.2
-150.5
-156.9
-163.2
-169.6
-176.0
-181.3
-187.6
-192.9
-198.2
NOTE:
The above characteristics are specified under best, worst, and nominal process variation/conditions.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
58
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 21: Reduced Output Drive Characteristics
PULL-DOWN CURRENT (mA)
PULL-UP CURRENT (mA)
VOLTAGE
(V)
NOMINAL
LOW
NOMINAL
HIGH
MINIMUM
MAXIMUM
NOMINAL
LOW
NOMINAL
HIGH
MINIMUM
MAXIMUM
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3.4
6.9
10.3
13.6
16.9
19.9
22.3
24.7
26.9
29.0
30.6
31.8
32.8
33.5
34.0
34.3
34.5
34.8
35.1
35.4
35.6
35.8
36.1
36.3
36.5
36.7
36.8
3.8
7.6
11.4
15.1
18.7
22.1
25.0
28.2
31.3
34.1
36.9
39.5
42.0
44.4
46.6
48.6
50.5
52.2
53.9
55.0
56.1
57.1
57.7
58.2
58.7
59.2
59.6
2.6
5.2
7.8
10.4
13.0
15.7
18.2
20.8
22.4
24.1
25.4
26.2
26.6
26.8
27.0
27.2
27.4
27.7
27.8
28.0
28.1
28.2
28.3
28.3
28.4
28.5
28.6
5.0
9.9
14.6
19.2
23.6
28.0
32.2
35.8
39.5
43.2
46.7
50.0
53.1
56.1
58.7
61.4
63.5
65.6
67.7
69.8
71.6
73.3
74.9
76.4
77.7
78.8
79.7
-3.5
-6.9
-10.3
-13.6
-16.9
-19.4
-21.5
-23.3
-24.8
-26.0
-27.1
-27.8
-28.3
-28.6
-28.7
-28.9
-28.9
-29.0
-29.2
-29.2
-29.3
-29.5
-29.5
-29.6
-29.7
-29.8
-29.9
-4.3
-7.8
-12.0
-15.7
-19.3
-22.9
-26.5
-30.1
-33.6
-37.1
-40.3
-43.1
-45.8
-48.4
-50.7
-52.9
-55.0
-56.8
-58.7
-60.0
-61.2
-62.4
-63.1
-63.8
-64.4
-65.1
-65.8
-2.6
-5.2
-7.8
-10.4
-13.0
-15.7
-18.2
-20.4
-21.6
-21.9
-22.1
-22.2
-22.3
-22.4
-22.6
-22.7
-22.7
-22.8
-22.9
-22.9
-23.0
-23.0
-23.1
-23.2
-23.2
-23.3
-23.3
-5.0
-9.9
-14.6
-19.2
-23.6
-28.0
-32.2
-35.8
-39.5
-43.2
-46.7
-50.0
-53.1
-56.1
-58.7
-61.4
-63.5
-65.6
-67.7
-69.8
-71.6
-73.3
-74.9
-76.4
-77.7
-78.8
-79.7
NOTE:
The above characteristics are specified under best, worst, and nominal process variation/conditions.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
59
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 38: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window
T1
T2
T2n
T3
T3n
T4
CK#
CK
tHP5
tHP5
tHP5
tHP5
tDQSQ3
tDQSQ3
tQH4
tQH4
tHP5
tHP5
tDQSQ3
tDQSQ3
DQS1
DQ (Last data valid)
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ (First data no longer valid)
tQH4
tQH4
DQ (Last data valid)
T2
T2n
T3
T3n
DQ (First data no longer valid)
T2
T2n
T3
T3n
All DQ and DQS, collectively6
T2
T2n
T3
T3n
Data
Valid
window
Data
Valid
window
Data
Valid
window
Data
Valid
window
Earliest signal transition
Latest signal transition
NOTE:
1. DQ transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an “early DQS,” at
T3 is a “nominal DQS,” and at T3n is a “late DQS.”
2. For a x4, only two DQ apply.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last
valid DQ transition.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
60
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 39: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window
CK#
CK
T1
T2
tHP5
tHP5
T2n
T3
tHP5
tHP5
tDQSQ3
tDQSQ3
tQH4
tQH4
T3n
tHP5
T4
tHP5
tDQSQ3
tDQSQ3
LDQS1
tQH4
Lower Byte
DQ (Last data valid)2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ (First data no longer valid)2
tQH4
DQ (Last data valid)2
T2
T2n
T3
T3n
DQ (First data no longer valid)2
T2
T2n
T3
T3n
DQ0 - DQ7 and LDQS, collectively6
T2
T2n
T3
T3n
Data Valid
window
Data Valid
window
Data Valid
window
Data Valid
window
tDQSQ3
tDQSQ3
tDQSQ3
tDQSQ3
UDQS1
tQH4
tQH4
tQH4
DQ (Last data valid)7
T2
T2n
DQ (First data no longer valid)7
T2
T2n
DQ8 - DQ15 and UDQS, collectively6
T2
T2n
Data Valid
window
Data Valid
window
Upper Byte
DQ (Last data valid)7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ (First data no longer valid)7
tQH4
T3
T3
T3
T3n
T3n
T3n
Data Valid Data Valid
window
window
NOTE:
1. DQ transitioning after DQS transition define tDQSQ window. LDQS defines the lower byte and UDQS defines the
upper byte.
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last
valid DQ transition.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transition and is tQH minus tDQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
61
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 40: Data Output Timing – tAC and tDQSCK
T07
T1
T2
T3
T2n
T3n
T4
T4n
T5
T5n
T6
CK#
CK
tDQSCK1 (MAX) tHZ(MAX)
tDQSCK1 (MIN)
tDQSCK1 (MAX)
tDQSCK1 (MIN)
tLZ (MIN)
tRPST
tRPRE
DQS, or LDQS/UDQS2
DQ (Last data valid)
T2
T2n
T3
T3n
T4
T4n
T5
T5n
DQ (First data valid)
T2
T2n
T3
T3n
T4
T4n
T5
T5n
All DQ values, collectively3
T2
T2n
T3
T3n
T4
T4n
T5
T5n
tLZ (MIN)
tAC4 (MIN)
tAC4 (MAX)
tHZ (MAX)
NOTE:
1. tDQSCK is the DQS output window relative to CK and is the “long term” component of DQS skew.
2.
3.
4.
5.
6.
7.
DQ transitioning after DQS transition define tDQSQ window.
All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
t
AC is the DQ output window relative to CK, and is the “long term” component of DQ skew.
tLZ (MIN) and tAC (MIN) are the first valid signal transition.
t
HZ (MAX), and tAC (MAX) are the latest valid signal transition.
READ command with CL = 2 issued at T0.
Figure 41: Data Input Timing
T03
T1
T1n
T2
T2n
T3
CK#
CK
tDQSS
tDSH1 tDSS2
tDSH1 tDSS2
DQS
tDQSL tDQSH tWPST
tWPRES tWPRE
DI
b
DQ
DM
tDS
tDH
TRANSITIONING DATA
DON’T CARE
NOTE:
1. tDSH (MIN) generally occurs during tDQSS (MIN).
2. tDSS (MIN) generally occurs during tDQSS (MAX).
3. WRITE command issued at T0.
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
62
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 42: Initialize And Load Mode Registers
((
))
VDD
VDDQ
((
))
tVTD1
((
))
VTT1
VREF
((
))
CK#
((
))
((
))
T1
T0
CK
tCH
tIS
LVCMOS
LOW LEVEL
CKE
tCL
tIS
Td0
Te0
Tf0
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tIH
NOP
((
))
((
))
PRE
tCK
((
))
((
))
((
))
((
))
A0-A9,
A11, A12, A13
((
))
((
))
((
))
((
))
ALL BANKS
((
))
((
))
tIS
tIH
((
))
((
))
PRE
AR
((
))
((
))
((
))
((
))
AR
ACT5
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA
tIH
CODE
((
))
((
))
CODE
((
))
((
))
((
))
((
))
CODE
((
))
((
))
((
))
((
))
BA0 = L,
BA1 = L
tIH
CODE
tIS
((
))
((
))
((
))
((
))
((
))
((
))
LMR
((
))
((
))
tIS
((
))
((
))
((
))
((
))
LMR
tIS
BA0, BA1
Tc0
((
))
((
))
DM
A10
Tb0
((
))
((
))
tIH
((
))
((
))
((
))
COMMAND6
Ta0
((
))
((
))
tIH
BA0 = H,
BA1 = L
ALL BANKS
tIS
tIH
DQS
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
DQ
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
T = 200µs
Power-up: VDD and CK stable
tRP
tMRD
Load Extended
Mode Register
tMRD
tRP
tRFC
tRFC5
200 cycles of CK3
Load Mode
Register2
DON’T CARE
NOTE:
1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up.
VDDQ, VTT, and VREF, must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up,
even if VDD/VDDQ are 0V, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input
pin. Once initialized, VREF must always be powered with in specified range.
2. Reset the DLL with A8 = H while programming the operating parameters.
3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can
be issued.
4. The two AUTO REFRESH commands at Td0 and Te0 may be applied prior to the LOAD MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any
bank. If another LMR command is issued, the same operating parameter, previously issued, must be used.
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address.
-75
SYMBOL
t
CH
tCL
t
CK (2.5)
t
CK (2)
tIH
F
t
ISF
MIN
0.45
0.45
7.5
10
.90
.90
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
-75
MAX
0.55
0.55
13
13
UNITS
t
CK
tCK
ns
ns
ns
ns
SYMBOL
t
IHS
tIS
S
t
MRD
t
RFC
tRP
t
VTD
63
MIN
1
1
15
120
20
0
MAX
13
UNITS
ns
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 43: Power-Down Mode
T0
T1
T2
CK#
CK
tCK
tIS
tIH
tCH
tCL
tIS
COMMAND
tIS
ADDR
Ta2
((
))
tIH
VALID1
Ta1
tIS
CKE
tIS
Ta0
((
))
((
))
((
))
((
))
NOP
tIH
NOP
VALID
((
))
((
))
VALID
DQS
((
))
((
))
DQ
((
))
((
))
DM
((
))
((
))
VALID
tREFC
Enter 2
Power-Down
Mode
Exit
Power-Down
Mode
DON’T CARE
NOTE:
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is
precharge power-down. If this command is an ACTIVE (or if at least one row is already active), then the power-down
mode shown is active power-down.
2. No column accesses are allowed to be in progress at the time power-down is entered.
-75
SYMBOL
t
CH
t
CL
tCK (2.5)
MIN
0.45
0.45
7.5
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
-75
MAX
0.55
0.55
13
UNITS
t
CK
t
CK
ns
SYMBOL
t
CK (2)
t
IHF
tIS
F
64
MIN
10
.90
.90
MAX
13
UNITS
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 44: Auto Refresh Mode
T0
T2
T1
T3
T4
CK#
CK
tIS
tIH
CKE
tCL
tIH
NOP 2
PRE
NOP2
NOP2
AR
A0-A9, A11
A12, A131
ALL BANKS
A101
ONE BANK
tIS
BA0, BA11
Ta0
Ta1
((
))
((
))
VALID
tIS
COMMAND1
tCH
CK
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
NOP2, 3
AR 6
((
))
((
))
Tb0
Tb1
Tb2
NOP2
ACT
VALID
NOP2, 3
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
BA
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tIH
Bank(s)4
DQS5
DQ5
DM5
tRP
tRFC
tRFC5
DON’T CARE
NOTE:
1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active
during clock positive transitions.
3. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time, CKE must be active during clock positive transitions.
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active
banks).
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.
-75
SYMBOL
tCH
t
CL
t
CK (2.5)
tCK (2)
t
IHF
MIN
0.45
0.45
7.5
10
.90
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
-75
MAX
0.55
0.55
13
13
UNITS
tCK
t
CK
ns
ns
ns
SYMBOL
t
ISF
t
IHS
tIS
S
t
RFC
t
RP
65
MIN
.90
1
1
120
20
MAX
UNITS
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 45: Self Refresh Mode
T11
T0
((
))
((
))
CK#
CK1
tCH
tIS
tIH
tCL
tIS
Ta2
t IS
((
))
tIH
NOP
Ta1
tCK
tIS
CKE
COMMAND2
Ta01
((
))
((
))
AR
NOP
NOP
Tb1
Tb2
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
VALID3
tIS
VALID
((
))
((
))
VALID
((
))
((
))
VALID
tIH
ADDR
((
))
((
))
((
))
((
))
DQS
((
))
((
))
((
))
((
))
DQ
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
DM
tRP4
Tc1
VALID
VALID
tXSNR5
tXSRD6
Enter Self Refresh
Mode7
DON’T CARE
Exit Self Refresh Mode7
NOTE:
1. Clock must be stable until after the self refresh command has been registered. A change in clock frequency is
allowed before Ta0, provided it is within the specified tCK limits. Regardless, the clock must be stable before exiting
self refresh mode. That is, the clock must be cycling within specifications by Ta0.
2.
3.
4.
5.
NOPs are interchangeable with DESELECT commands, AR = AUTO REFRESH command.
Auto Refresh is not required at this point, but is highly recommended.
Device must be in the all banks idle state prior to entering self refresh mode.
tXSNR is required before any non-READ command can be applied. That is only NOP or DESELECT commands are allowed until
Tb1.
6. tXSRD (200 cycles of a valid CK and CKE = high) is required before any READ command can be applied.
7. As a general rule, any time Self Refresh Mode is exited, the DRAM may not re-enter the Self Refresh Mode until all rows have
been refreshed via the Auto Refresh command at the distributed refresh rate, tREFI, or faster. However, the following exception
is allowed. Self Refresh Mode may be re-entered anytime after exiting, if the following conditions are all met:
a. The DRAM had been in the Self Refresh Mode for a minimum of 200ms prior to exiting.
b. tXSNR and tXSRD are not violated.
c. At least two Auto Refresh commands are performed during each tREFI interval while the DRAM remains out of Self
Refresh mode.
8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.
-75
SYMBOL
t
CH
tCL
t
CK (2.5)
t
CK (2)
tIH
F
t
ISF
MIN
0.45
0.45
7.5
10
.90
.90
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
-75
MAX
0.55
0.55
13
13
UNITS
t
CK
tCK
ns
ns
ns
ns
SYMBOL
tIH
S
t
ISS
t
RFC
tRP
MIN
1
1
120
20
tXSNR
127.5
200
tXSRD
66
MAX
UNITS
ns
ns
ns
ns
ns
t
CK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 46: Bank Read - Without Auto Precharge
T1
T0
CK#
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
NOP6
ACT
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
COMMAND5
NOP6
NOP6
ACT
tIS
x4: A0-A9, A11, A12
x8: A0-A9, A11
x16: A0-A9
RA
x4: A13
x8: A12, A13
x16: A11, A12, A13
RA
PRE7
NOP6
READ2
NOP6
tIH
Col n
RA
RA
tIS
tIH
ALL BANKS
A10
RA
RA
3
ONE BANK
tIS
BA0, BA1
tIH
Bank x
Bank x4
Bank x
tRCD
Bank x
CL = 2
tRP
tRAS7
tRC
DM
tDQSCK (MIN)
Case 1: tAC (MIN) and tDQSCK (MIN)
tRPST
tRPRE
DQS
tLZ (MIN)
DO
n
DQ1
tLZ (MIN)
tAC (MIN)
tDQSCK(MAX)
Case 2: tAC (MAX) and tDQSCK (MAX)
tRPST
tRPRE
DQS
DO
n
DQ1
tAC (MAX)
tHZ (MAX)
TRANSITIONING DATA
DON’T CARE
NOTE:
1. DOn = data-out from column n; subsequent elements are provided in the programmed order.
2.
3.
4.
5.
6.
7.
8.
Burst length = 4 in the case shown.
Disable auto precharge.
“Don’t Care” if A10 is HIGH at T5.
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
The PRECHARGE command can only be applied at T5 if tRAS minimum is met.
Refer to Figure 38 on page 60, Figure 39 on page 61, and Figure 40 on page 62 for detailed DQS and DQ timing.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
67
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 47: Bank Read - With Auto Precharge
CK#
T1
T0
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
NOP5
ACT
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
COMMAND4
NOP5
NOP5
ACT
tIS
x4: A0-A9, A11, A12
x8: A0-A9, A11
x16: A0-A9
RA
x4: A13
x8: A12, A13
x16: A11, A12, A13
RA
A10
RA
READ2,6
NOP5
NOP5
NOP5
tIH
Col n
RA
RA
3
IS
BA0, BA1
tIS
RA
tIH
IH
Bank x
Bank x
tRCD, tRAP6
Bank x
CL = 2
tRP7
tRAS
tRC
DM
Case 1: tAC (MIN) and tDQSCK (MIN)
tDQSCK (MIN)
tRPST
tRPRE
DQS
tLZ(MIN)
DO
n
DQ1
tLZ (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
tAC (MIN)
tDQSCK (MAX)
tRPST
tRPRE
DQS
DO
n
DQ1
tAC (MAX)
tHZ (MAX)
TRANSITIONING DATA
DON’T CARE
NOTE:
1. DOn = data-out from column n; subsequent elements are provided in the programmed order.
2.
3.
4.
5.
6.
7.
8.
Burst length = 4 in the case shown.
Enable auto precharge.
ACT = ACTIVE, RA = Row Address, BA = Bank Address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
The READ command can only be applied at T3 if tRAP is satisfied at T3.
t
RP starts only after tRAS has been satisfied.
Refer to Figure 38 on page 60, Figure 39 on page 61, and Figure 40 on page 62 for detailed DQS and DQ timing.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
68
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 48: Bank Write - Without Auto Precharge
T1
T0
CK#
T2
T3
T4
T4n
T5
T5n
T6
T7
T8
NOP6
NOP6
PRE
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
COMMAND5
NOP6
NOP6
ACT
tIS
tIH
x4: A0-A9, A11, A12
x8: A0-A9, A11
x16: A0-A9
RA
x4: A13
x8: A12, A13
x16: A11, A12, A13
RA
A10
RA
Col n
tIS
tIS
BA0, BA1
NOP6
NOP6
WRITE2
tIH
ALL BANKS
3
ONE BANK
tIH
Bank x
Bank x4
Bank x
tWR
tRCD
tRP
tRAS
tDQSS (NOM)
DQS
tDQSL
tWPRES tWPRE
tDQSH tWPST
DI
b
DQ1
DM
tDS
tDH
TRANSITIONING DATA
DON’T CARE
NOTE:
1. DIn = data-in. from column n; subsequent elements are provided in the programmed order.
2.
3.
4.
5.
6.
7.
Burst length = 4 in the case shown.
Disable auto precharge.
“Don’t Care” if A10 is HIGH at T8.
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
See Figure 41, ”Data Input Timing,” on page 62 for detailed DQ timing.
-75
SYMBOL
tCH
t
CL
t
CK (2.5)
tCK (2)
tDH
tDS
tDQSH
t
DQSL
t
DQSS
tDSS
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
MIN
0.45
0.45
7.5
10
0.5
0.5
0.35
0.35
0.75
0.2
-75
MAX
UNITS
SYMBOL
MIN
0.55
0.55
13
13
tCK
tDSH
0.2
1
1
40
20
20
0.25
0
0.4
15
1.25
t
tIH
CK
ns
ns
ns
ns
tCK
t
CK
t
CK
tCK
tIS
S
S
tRAS
t
RCD
t
RP
tWPRE
tWPRES
tWPST
t
WR
69
MAX
UNITS
tCK
120,000
0.6
ns
ns
ns
ns
ns
tCK
ns
tCK
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 49: Bank Write - With Auto Precharge
T1
T0
CK#
T2
T3
T4
T4n
T5
T5n
T6
T7
NOP5
NOP5
T8
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
COMMAND4
NOP5
NOP5
ACT
tIS
NOP5
NOP5
WRITE2
NOP5
tIH
x4: A0-A9, A11, A12
x8: A0-A9, A11
x16: A0-A9
RA
x4: A13
x8: A12, A13
x16: A11, A12, A13
RA
A10
RA
Col n
3
tIS
BA0, BA1
tIS
tIH
tIH
Bank x
Bank x
tWR
tRCD
tRP
tRAS
tDQSS (NOM)
DQS
tWPRES tWPRE
tDQSL
tDQSH tWPST
DI
b
DQ1
DM
tDS
tDH
TRANSITIONING DATA
DON’T CARE
NOTE:
1. DIn = data-out from column n; subsequent elements are provided in the programmed order.
2.
3.
4.
5.
6.
Burst length = 4 in the case shown.
Enable auto precharge.
ACT = ACTIVE, RA = Row Address, BA = Bank Address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
See Figure 41, ”Data Input Timing,” on page 62 for detailed DQ timing.
-75
SYMBOL
t
CH
t
CL
t
CK (2.5)
t
CK (2)
t
DH
t
DS
t
DQSH
t
DQSL
t
DQSS
t
DSS
-75
MIN
MAX
0.45
0.45
7.5
10
0.5
0.5
0.35
0.35
0.75
0.2
0.55
0.55
13
13
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1.25
UNITS
SYMBOL
MIN
tDSH
0.2
1
1
40
20
20
0.25
0
0.4
15
t
CK
t
CK
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
tIH
tIS
S
S
tRAS
tRCD
tRP
WPRE
t
WPRES
tWPST
tWR
t
70
MAX
UNITS
tCK
120,000
0.6
ns
ns
ns
ns
ns
t
CK
ns
tCK
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 50: Write - DM Operation
T1
T0
CK#
T2
T3
T4
T4n
T5
T5n
T6
T7
T8
NOP6
NOP6
PRE
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
COMMAND5
NOP6
NOP6
ACT
tIS
tIH
x4: A0-A9, A11, A12
x8: A0-A9, A11
x16: A0-A9
RA
x4: A13
x8: A21, A13
x16: A11, A12, A13
RA
A10
RA
Col n
tIS
tIS
BA0, BA1
NOP6
NOP6
WRITE2
tIH
ALL BANKS
3
ONE BANK
tIH
Bank x
Bank x4
Bank x
tWR
tRCD
tRP
tRAS
tDQSS (NOM)
DQS
tDQSL
tWPRES tWPRE
tDQSH tWPST
DI
b
DQ1
DM
tDS
tDH
TRANSITIONING DATA
DON’T CARE
NOTE:
1. DIn = data-in from column n; subsequent elements are provided in the programmed order.
2.
3.
4.
5.
6.
7.
Burst length = 4 in the case shown.
Disable auto precharge.
“Don’t Care” if A10 is HIGH at T8.
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
See Figure 41, ”Data Input Timing,” on page 62 for detailed DQ timing.
-75
SYMBOL
t
CH
t
CL
t
CK (2.5)
t
CK (2)
t
DH
t
DS
t
DQSH
t
DQSL
t
DQSS
t
DSS
-75
MIN
MAX
0.45
0.45
7.5
10
0.5
0.5
0.35
0.35
0.75
0.2
0.55
0.55
13
13
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1.25
UNITS
SYMBOL
MIN
tDSH
0.2
1
1
40
20
20
0.25
0
0.4
15
t
CK
t
CK
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
tIH
tIS
S
S
tRAS
tRCD
tRP
WPRE
t
WPRES
tWPST
tWR
t
71
MAX
UNITS
tCK
120,000
0.6
ns
ns
ns
ns
ns
t
CK
ns
tCK
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 51: 66-Pin Plastic TSOP (400 mil)
SEE DETAIL A
22.22 ± 0.08
0.71
0.65 TYP
0.10 (2X)
0.32 ± .075 TYP
11.76 ±0.10
10.16 ±0.08
+0.03
0.15 -0.02
PIN #1 ID
GAGE PLANE
0.10
0.25
+0.10
-0.05
0.10
0.80 TYP
1.20 MAX
0.50 ±0.10
DETAIL A
NOTE:
1. All dimensions in millimeters
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
Data Sheet Designation
Preliminary: This data sheet contains initial characterization limits that are subject to change upon full
characterization of production devices.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
72
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
73
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
All other trademarks are the property of their respective owners
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
74
Micron Technology, Inc., reserves the right to change products or specifications without notice..
©2003 Micron Technology, Inc